diff --git a/.travis.yml b/.travis.yml index 5ac9084..3f6984a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -24,6 +24,8 @@ jobs: env: ARCH=riscv LLVM_IAS=1 - name: "ARCH=s390 BOOT=0" env: ARCH=s390 + - name: "ARCH=x86" + env: ARCH=x86 - name: "ARCH=x86_64 LD=ld.lld" env: ARCH=x86_64 LD=ld.lld # linux (cron only) @@ -62,6 +64,9 @@ jobs: - name: "ARCH=s390 BOOT=0 REPO=linux-next" env: ARCH=s390 REPO=linux-next if: type = cron + - name: "ARCH=x86 REPO=linux-next" + env: ARCH=x86 REPO=linux-next + if: type = cron - name: "ARCH=x86_64 LD=ld.lld REPO=linux-next" env: ARCH=x86_64 LD=ld.lld REPO=linux-next if: type = cron diff --git a/driver.sh b/driver.sh index 348817f..d5d5aaf 100755 --- a/driver.sh +++ b/driver.sh @@ -140,6 +140,12 @@ setup_variables() { OBJDUMP=${CROSS_COMPILE}objdump ;; + "x86") + config=i386_defconfig + make_target=bzImage + export ARCH=i386 + ;; + "x86_64") case ${REPO} in android-*) diff --git a/patches/llvm-all/linux-next/x86/x86-support-i386-with-Clang.patch b/patches/llvm-all/linux-next/x86/x86-support-i386-with-Clang.patch new file mode 100644 index 0000000..2cf51de --- /dev/null +++ b/patches/llvm-all/linux-next/x86/x86-support-i386-with-Clang.patch @@ -0,0 +1,237 @@ +From patchwork Mon May 4 23:03:08 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Nick Desaulniers +X-Patchwork-Id: 1236080 +Return-Path: +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 52B86C3A5A9 + for ; Mon, 4 May 2020 23:03:37 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 244512075B + for ; Mon, 4 May 2020 23:03:37 +0000 (UTC) +Authentication-Results: mail.kernel.org; + dkim=pass (2048-bit key) header.d=google.com header.i=@google.com + header.b="nSNYyMa0" +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728297AbgEDXDg (ORCPT + ); + Mon, 4 May 2020 19:03:36 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47956 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) + by vger.kernel.org with ESMTP id S1728182AbgEDXDf (ORCPT + ); + Mon, 4 May 2020 19:03:35 -0400 +Received: from mail-qt1-x849.google.com (mail-qt1-x849.google.com + [IPv6:2607:f8b0:4864:20::849]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 521C0C061A0E + for ; + Mon, 4 May 2020 16:03:34 -0700 (PDT) +Received: by mail-qt1-x849.google.com with SMTP id w12so5566qto.19 + for ; + Mon, 04 May 2020 16:03:34 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=google.com; s=20161025; + h=date:message-id:mime-version:subject:from:to:cc; + bh=riJtF6wnIn/7Sr6BY03T361JLi5EWFboyLscUDM7chc=; + b=nSNYyMa0Ag3IGJnIHcETMoofQRjf/uWCB3a1UEuCsnmr2sovLYdjfRQZ+qj89nWrgg + gpSRpqvvDAhNuzl+vZhHDzNm03hPwFuJTaEl5ewyOEHCnXrRCV4ca9h8GVKRwkc0AhUk + 6saCDJPR7AU2DxvR+RT0mXFsnVLSjh+k1tmdbdVqVHOEF9wpuw7QZJp5rwGQZJcBHaMH + KHYof6HN0q2S/jbiquH6KNObdD3gNh/8bNPvjM6gQFIZT0lZgZ9cDouRVQ7TktyA95kd + tgewVf0TPWAE/KtCrmbUZnVQF0OWf6KTZD5h8jbZwqHpfiOfAejwil16Qt3Kktuf7IFK + f1HQ== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; + bh=riJtF6wnIn/7Sr6BY03T361JLi5EWFboyLscUDM7chc=; + b=gDA3yEPrDlggGZ053aCCSuuQVkgyw+h7zNP6kVcWS6qWM1Pxfj6vwDN1Jse5nXKaTd + MurJhVh/3fFfpo0/yDN4R4KOObsidXYgwYek6HsCMJ05Y0EkA03TPO60An3rEnvzYbu1 + e7A6/dz5DdfdCyay5AZOCsL+ptaxBLqAZKEAKs+2+5m+tsspt7my/UHyECk+eOgawJ/q + S/dBAuqkGdmM5UfCf/SIGPF/6dXhLDQ9aE0Elsgs60POm8e3WrySmaC2gM4Su7sWBrKy + kr4ZDLWuBeigmlHXbW0WcVrlj0DY3zWVld64EUYNTRWtVA6hBGe37LvVZ/ZV/SX7LTQQ + Yk7g== +X-Gm-Message-State: AGi0PuY8zY5fdTfU5SHfROBWXk126w1JV8Yc4wo5tfY45HevM8/VYSv+ + eviYAweYRMneoGWDLrOkGeR8JJgIO4pF+dQyppg= +X-Google-Smtp-Source: + APiQypKKbbGIodBbmoNg+Bd3UCuudEFWI3amAwwTE7q4jyHkz+LOcM90+Fwj4xlOvneGVL1IDm7bbqoA5ZWEY6G3X/w= +X-Received: by 2002:a05:6214:1242:: with SMTP id + q2mr354063qvv.198.1588633412455; + Mon, 04 May 2020 16:03:32 -0700 (PDT) +Date: Mon, 4 May 2020 16:03:08 -0700 +Message-Id: <20200504230309.237398-1-ndesaulniers@google.com> +Mime-Version: 1.0 +X-Mailer: git-send-email 2.26.2.526.g744177e7f7-goog +Subject: [PATCH] x86: support i386 with Clang +From: Nick Desaulniers +To: Thomas Gleixner , + Ingo Molnar , Borislav Petkov +Cc: Nick Desaulniers , + Arnd Bergmann , + David Woodhouse , + Dmitry Golovin , + Linus Torvalds , + Dennis Zhou , Tejun Heo , + Christoph Lameter , x86@kernel.org, + "H. Peter Anvin" , + Al Viro , + Josh Poimboeuf , + Masami Hiramatsu , + Peter Zijlstra , + linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +GCC and Clang are architecturally different, which leads to subtle +issues for code that's invalid but clearly dead. This can happen with +code that emulates polymorphism with the preprocessor and sizeof. + +GCC will perform semantic analysis after early inlining and dead code +elimination, so it will not warn on invalid code that's dead. Clang +strictly performs optimizations after semantic analysis, so it will warn +for dead code. + +Neither Clang nor GCC like this very much with -m32: + +long long ret; +asm ("movb $5, %0" : "=q" (ret)); + +However, GCC can tolerate this variant: + +long long ret; +switch (sizeof(ret)) { +case 1: + asm ("movb $5, %0" : "=q" (ret)); + break; +case 8:; +} + +Clang, on the other hand, won't accept that because it validates the +inline asm for the '1' case *before* the optimisation phase where it +realises that it wouldn't have to emit it anyway. + +If LLVM (Clang's "back end") fails such as during instruction selection +or register allocation, it cannot provide accurate diagnostics +(warnings/errors) that contain line information, as the AST has been +discarded from memory at that point. + +While there have been early discussions about having C/C++ specific +language optimizations in Clang via the use of MLIR, which would enable +such earlier optimizations, such work is not scoped and likely a +multi-year endeavor. + +We also don't want to swap the use of "=q" with "=r". For 64b, it +doesn't matter. For 32b, it's possible that a 32b register without a 8b +lower alias (i.e. ESI, EDI, EBP) is selected which the assembler will +then reject. + +With this, Clang can finally build an i386 defconfig. + +Reported-by: Arnd Bergmann +Reported-by: David Woodhouse +Reported-by: Dmitry Golovin +Reported-by: Linus Torvalds +Link: https://bugs.llvm.org/show_bug.cgi?id=33587 +Link: https://github.com/ClangBuiltLinux/linux/issues/3 +Link: https://github.com/ClangBuiltLinux/linux/issues/194 +Link: https://github.com/ClangBuiltLinux/linux/issues/781 +Link: https://lore.kernel.org/lkml/20180209161833.4605-1-dwmw2@infradead.org/ +Link: https://lore.kernel.org/lkml/CAK8P3a1EBaWdbAEzirFDSgHVJMtWjuNt2HGG8z+vpXeNHwETFQ@mail.gmail.com/ +Signed-off-by: Nick Desaulniers +--- +Note: this is a resend of: +https://lore.kernel.org/lkml/20180209161833.4605-1-dwmw2@infradead.org/ +rebased on today's Linux next, and with the additional change to +uaccess.h. + +I'm happy to resend with authorship and reported by tags changed to +suggested by's or whatever, just let me know. + +Part of the commit message is stolen from David, and part from Linus. +Shall I resend with David's authorship and +[Nick: reworded] +??? + +I don't really care, I just don't really want to carry this out of tree +for our CI, which is green for i386 otherwise. + + + arch/x86/include/asm/percpu.h | 12 ++++++++---- + arch/x86/include/asm/uaccess.h | 4 +++- + 2 files changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h +index 2278797c769d..826d086f71c9 100644 +--- a/arch/x86/include/asm/percpu.h ++++ b/arch/x86/include/asm/percpu.h +@@ -99,7 +99,7 @@ do { \ + case 1: \ + asm qual (op "b %1,"__percpu_arg(0) \ + : "+m" (var) \ +- : "qi" ((pto_T__)(val))); \ ++ : "qi" ((unsigned char)(unsigned long)(val))); \ + break; \ + case 2: \ + asm qual (op "w %1,"__percpu_arg(0) \ +@@ -144,7 +144,7 @@ do { \ + else \ + asm qual ("addb %1, "__percpu_arg(0) \ + : "+m" (var) \ +- : "qi" ((pao_T__)(val))); \ ++ : "qi" ((unsigned char)(unsigned long)(val))); \ + break; \ + case 2: \ + if (pao_ID__ == 1) \ +@@ -182,12 +182,14 @@ do { \ + + #define percpu_from_op(qual, op, var) \ + ({ \ ++ unsigned char pfo_u8__; \ + typeof(var) pfo_ret__; \ + switch (sizeof(var)) { \ + case 1: \ + asm qual (op "b "__percpu_arg(1)",%0" \ +- : "=q" (pfo_ret__) \ ++ : "=q" (pfo_u8__) \ + : "m" (var)); \ ++ pfo_ret__ = (typeof(var))(unsigned long)pfo_u8__; \ + break; \ + case 2: \ + asm qual (op "w "__percpu_arg(1)",%0" \ +@@ -211,12 +213,14 @@ do { \ + + #define percpu_stable_op(op, var) \ + ({ \ ++ unsigned char pfo_u8__; \ + typeof(var) pfo_ret__; \ + switch (sizeof(var)) { \ + case 1: \ + asm(op "b "__percpu_arg(P1)",%0" \ +- : "=q" (pfo_ret__) \ ++ : "=q" (pfo_u8__) \ + : "p" (&(var))); \ ++ pfo_ret__ = (typeof(var))(unsigned long)pfo_u8__; \ + break; \ + case 2: \ + asm(op "w "__percpu_arg(P1)",%0" \ +diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h +index d8f283b9a569..cf8483cd80e1 100644 +--- a/arch/x86/include/asm/uaccess.h ++++ b/arch/x86/include/asm/uaccess.h +@@ -314,11 +314,13 @@ do { \ + + #define __get_user_size(x, ptr, size, retval) \ + do { \ ++ unsigned char x_u8__; \ + retval = 0; \ + __chk_user_ptr(ptr); \ + switch (size) { \ + case 1: \ +- __get_user_asm(x, ptr, retval, "b", "=q"); \ ++ __get_user_asm(x_u8__, ptr, retval, "b", "=q"); \ ++ (x) = x_u8__; \ + break; \ + case 2: \ + __get_user_asm(x, ptr, retval, "w", "=r"); \ diff --git a/patches/llvm-all/linux/x86/drm-i915-re-disable--Wframe-address.patch b/patches/llvm-all/linux/x86/drm-i915-re-disable--Wframe-address.patch new file mode 100644 index 0000000..332e21a --- /dev/null +++ b/patches/llvm-all/linux/x86/drm-i915-re-disable--Wframe-address.patch @@ -0,0 +1,100 @@ +From patchwork Sun Apr 26 21:42:15 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Nick Desaulniers +X-Patchwork-Id: 1231289 +Return-Path: +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 72157C54FCB + for ; Sun, 26 Apr 2020 21:42:27 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 527FD2070A + for ; Sun, 26 Apr 2020 21:42:27 +0000 (UTC) +Authentication-Results: mail.kernel.org; + dkim=pass (2048-bit key) header.d=google.com header.i=@google.com + header.b="fG5gI4J7" +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1726260AbgDZVm0 (ORCPT + ); + Sun, 26 Apr 2020 17:42:26 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47400 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org + with ESMTP id S1726184AbgDZVmZ (ORCPT + ); + Sun, 26 Apr 2020 17:42:25 -0400 +Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com + [IPv6:2607:f8b0:4864:20::b49]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B94DDC061A0F + for ; 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+ Sun, 26 Apr 2020 14:42:23 -0700 (PDT) +Date: Sun, 26 Apr 2020 14:42:15 -0700 +Message-Id: <20200426214215.139435-1-ndesaulniers@google.com> +Mime-Version: 1.0 +X-Mailer: git-send-email 2.26.2.303.gf8c07b1a785-goog +Subject: [PATCH] drm/i915: re-disable -Wframe-address +From: Nick Desaulniers +To: jani.nikula@linux.intel.com, airlied@linux.ie, daniel@ffwll.ch +Cc: Nick Desaulniers , + Joonas Lahtinen , + Rodrigo Vivi , + intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, + linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +The top level Makefile disables this warning. When building an +i386_defconfig with Clang, this warning is triggered a whole bunch via +includes of headers from perf. + +Link: https://github.com/ClangBuiltLinux/continuous-integration/pull/182 +Signed-off-by: Nick Desaulniers +Reviewed-by: Nathan Chancellor +--- + drivers/gpu/drm/i915/Makefile | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile +index 6f112d8f80ca..8c2257437471 100644 +--- a/drivers/gpu/drm/i915/Makefile ++++ b/drivers/gpu/drm/i915/Makefile +@@ -22,6 +22,7 @@ subdir-ccflags-y += $(call cc-disable-warning, sign-compare) + subdir-ccflags-y += $(call cc-disable-warning, sometimes-uninitialized) + subdir-ccflags-y += $(call cc-disable-warning, initializer-overrides) + subdir-ccflags-y += $(call cc-disable-warning, uninitialized) ++subdir-ccflags-y += $(call cc-disable-warning, frame-address) + subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror + + # Fine grained warnings disable diff --git a/patches/llvm-all/linux/x86/x86-support-i386-with-Clang.patch b/patches/llvm-all/linux/x86/x86-support-i386-with-Clang.patch new file mode 100644 index 0000000..2cf51de --- /dev/null +++ b/patches/llvm-all/linux/x86/x86-support-i386-with-Clang.patch @@ -0,0 +1,237 @@ +From patchwork Mon May 4 23:03:08 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Nick Desaulniers +X-Patchwork-Id: 1236080 +Return-Path: +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 52B86C3A5A9 + for ; Mon, 4 May 2020 23:03:37 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 244512075B + for ; Mon, 4 May 2020 23:03:37 +0000 (UTC) +Authentication-Results: mail.kernel.org; + dkim=pass (2048-bit key) header.d=google.com header.i=@google.com + header.b="nSNYyMa0" +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S1728297AbgEDXDg (ORCPT + ); + Mon, 4 May 2020 19:03:36 -0400 +Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47956 "EHLO + lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) + by vger.kernel.org with ESMTP id S1728182AbgEDXDf (ORCPT + ); + Mon, 4 May 2020 19:03:35 -0400 +Received: from mail-qt1-x849.google.com (mail-qt1-x849.google.com + [IPv6:2607:f8b0:4864:20::849]) + by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 521C0C061A0E + for ; + Mon, 4 May 2020 16:03:34 -0700 (PDT) +Received: by mail-qt1-x849.google.com with SMTP id w12so5566qto.19 + for ; + Mon, 04 May 2020 16:03:34 -0700 (PDT) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=google.com; s=20161025; + h=date:message-id:mime-version:subject:from:to:cc; + bh=riJtF6wnIn/7Sr6BY03T361JLi5EWFboyLscUDM7chc=; + b=nSNYyMa0Ag3IGJnIHcETMoofQRjf/uWCB3a1UEuCsnmr2sovLYdjfRQZ+qj89nWrgg + gpSRpqvvDAhNuzl+vZhHDzNm03hPwFuJTaEl5ewyOEHCnXrRCV4ca9h8GVKRwkc0AhUk + 6saCDJPR7AU2DxvR+RT0mXFsnVLSjh+k1tmdbdVqVHOEF9wpuw7QZJp5rwGQZJcBHaMH + KHYof6HN0q2S/jbiquH6KNObdD3gNh/8bNPvjM6gQFIZT0lZgZ9cDouRVQ7TktyA95kd + tgewVf0TPWAE/KtCrmbUZnVQF0OWf6KTZD5h8jbZwqHpfiOfAejwil16Qt3Kktuf7IFK + f1HQ== +X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; + d=1e100.net; s=20161025; + h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; + bh=riJtF6wnIn/7Sr6BY03T361JLi5EWFboyLscUDM7chc=; + b=gDA3yEPrDlggGZ053aCCSuuQVkgyw+h7zNP6kVcWS6qWM1Pxfj6vwDN1Jse5nXKaTd + MurJhVh/3fFfpo0/yDN4R4KOObsidXYgwYek6HsCMJ05Y0EkA03TPO60An3rEnvzYbu1 + e7A6/dz5DdfdCyay5AZOCsL+ptaxBLqAZKEAKs+2+5m+tsspt7my/UHyECk+eOgawJ/q + S/dBAuqkGdmM5UfCf/SIGPF/6dXhLDQ9aE0Elsgs60POm8e3WrySmaC2gM4Su7sWBrKy + kr4ZDLWuBeigmlHXbW0WcVrlj0DY3zWVld64EUYNTRWtVA6hBGe37LvVZ/ZV/SX7LTQQ + Yk7g== +X-Gm-Message-State: AGi0PuY8zY5fdTfU5SHfROBWXk126w1JV8Yc4wo5tfY45HevM8/VYSv+ + eviYAweYRMneoGWDLrOkGeR8JJgIO4pF+dQyppg= +X-Google-Smtp-Source: + APiQypKKbbGIodBbmoNg+Bd3UCuudEFWI3amAwwTE7q4jyHkz+LOcM90+Fwj4xlOvneGVL1IDm7bbqoA5ZWEY6G3X/w= +X-Received: by 2002:a05:6214:1242:: with SMTP id + q2mr354063qvv.198.1588633412455; + Mon, 04 May 2020 16:03:32 -0700 (PDT) +Date: Mon, 4 May 2020 16:03:08 -0700 +Message-Id: <20200504230309.237398-1-ndesaulniers@google.com> +Mime-Version: 1.0 +X-Mailer: git-send-email 2.26.2.526.g744177e7f7-goog +Subject: [PATCH] x86: support i386 with Clang +From: Nick Desaulniers +To: Thomas Gleixner , + Ingo Molnar , Borislav Petkov +Cc: Nick Desaulniers , + Arnd Bergmann , + David Woodhouse , + Dmitry Golovin , + Linus Torvalds , + Dennis Zhou , Tejun Heo , + Christoph Lameter , x86@kernel.org, + "H. Peter Anvin" , + Al Viro , + Josh Poimboeuf , + Masami Hiramatsu , + Peter Zijlstra , + linux-kernel@vger.kernel.org, clang-built-linux@googlegroups.com +Sender: linux-kernel-owner@vger.kernel.org +Precedence: bulk +List-ID: +X-Mailing-List: linux-kernel@vger.kernel.org + +GCC and Clang are architecturally different, which leads to subtle +issues for code that's invalid but clearly dead. This can happen with +code that emulates polymorphism with the preprocessor and sizeof. + +GCC will perform semantic analysis after early inlining and dead code +elimination, so it will not warn on invalid code that's dead. Clang +strictly performs optimizations after semantic analysis, so it will warn +for dead code. + +Neither Clang nor GCC like this very much with -m32: + +long long ret; +asm ("movb $5, %0" : "=q" (ret)); + +However, GCC can tolerate this variant: + +long long ret; +switch (sizeof(ret)) { +case 1: + asm ("movb $5, %0" : "=q" (ret)); + break; +case 8:; +} + +Clang, on the other hand, won't accept that because it validates the +inline asm for the '1' case *before* the optimisation phase where it +realises that it wouldn't have to emit it anyway. + +If LLVM (Clang's "back end") fails such as during instruction selection +or register allocation, it cannot provide accurate diagnostics +(warnings/errors) that contain line information, as the AST has been +discarded from memory at that point. + +While there have been early discussions about having C/C++ specific +language optimizations in Clang via the use of MLIR, which would enable +such earlier optimizations, such work is not scoped and likely a +multi-year endeavor. + +We also don't want to swap the use of "=q" with "=r". For 64b, it +doesn't matter. For 32b, it's possible that a 32b register without a 8b +lower alias (i.e. ESI, EDI, EBP) is selected which the assembler will +then reject. + +With this, Clang can finally build an i386 defconfig. + +Reported-by: Arnd Bergmann +Reported-by: David Woodhouse +Reported-by: Dmitry Golovin +Reported-by: Linus Torvalds +Link: https://bugs.llvm.org/show_bug.cgi?id=33587 +Link: https://github.com/ClangBuiltLinux/linux/issues/3 +Link: https://github.com/ClangBuiltLinux/linux/issues/194 +Link: https://github.com/ClangBuiltLinux/linux/issues/781 +Link: https://lore.kernel.org/lkml/20180209161833.4605-1-dwmw2@infradead.org/ +Link: https://lore.kernel.org/lkml/CAK8P3a1EBaWdbAEzirFDSgHVJMtWjuNt2HGG8z+vpXeNHwETFQ@mail.gmail.com/ +Signed-off-by: Nick Desaulniers +--- +Note: this is a resend of: +https://lore.kernel.org/lkml/20180209161833.4605-1-dwmw2@infradead.org/ +rebased on today's Linux next, and with the additional change to +uaccess.h. + +I'm happy to resend with authorship and reported by tags changed to +suggested by's or whatever, just let me know. + +Part of the commit message is stolen from David, and part from Linus. +Shall I resend with David's authorship and +[Nick: reworded] +??? + +I don't really care, I just don't really want to carry this out of tree +for our CI, which is green for i386 otherwise. + + + arch/x86/include/asm/percpu.h | 12 ++++++++---- + arch/x86/include/asm/uaccess.h | 4 +++- + 2 files changed, 11 insertions(+), 5 deletions(-) + +diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h +index 2278797c769d..826d086f71c9 100644 +--- a/arch/x86/include/asm/percpu.h ++++ b/arch/x86/include/asm/percpu.h +@@ -99,7 +99,7 @@ do { \ + case 1: \ + asm qual (op "b %1,"__percpu_arg(0) \ + : "+m" (var) \ +- : "qi" ((pto_T__)(val))); \ ++ : "qi" ((unsigned char)(unsigned long)(val))); \ + break; \ + case 2: \ + asm qual (op "w %1,"__percpu_arg(0) \ +@@ -144,7 +144,7 @@ do { \ + else \ + asm qual ("addb %1, "__percpu_arg(0) \ + : "+m" (var) \ +- : "qi" ((pao_T__)(val))); \ ++ : "qi" ((unsigned char)(unsigned long)(val))); \ + break; \ + case 2: \ + if (pao_ID__ == 1) \ +@@ -182,12 +182,14 @@ do { \ + + #define percpu_from_op(qual, op, var) \ + ({ \ ++ unsigned char pfo_u8__; \ + typeof(var) pfo_ret__; \ + switch (sizeof(var)) { \ + case 1: \ + asm qual (op "b "__percpu_arg(1)",%0" \ +- : "=q" (pfo_ret__) \ ++ : "=q" (pfo_u8__) \ + : "m" (var)); \ ++ pfo_ret__ = (typeof(var))(unsigned long)pfo_u8__; \ + break; \ + case 2: \ + asm qual (op "w "__percpu_arg(1)",%0" \ +@@ -211,12 +213,14 @@ do { \ + + #define percpu_stable_op(op, var) \ + ({ \ ++ unsigned char pfo_u8__; \ + typeof(var) pfo_ret__; \ + switch (sizeof(var)) { \ + case 1: \ + asm(op "b "__percpu_arg(P1)",%0" \ +- : "=q" (pfo_ret__) \ ++ : "=q" (pfo_u8__) \ + : "p" (&(var))); \ ++ pfo_ret__ = (typeof(var))(unsigned long)pfo_u8__; \ + break; \ + case 2: \ + asm(op "w "__percpu_arg(P1)",%0" \ +diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h +index d8f283b9a569..cf8483cd80e1 100644 +--- a/arch/x86/include/asm/uaccess.h ++++ b/arch/x86/include/asm/uaccess.h +@@ -314,11 +314,13 @@ do { \ + + #define __get_user_size(x, ptr, size, retval) \ + do { \ ++ unsigned char x_u8__; \ + retval = 0; \ + __chk_user_ptr(ptr); \ + switch (size) { \ + case 1: \ +- __get_user_asm(x, ptr, retval, "b", "=q"); \ ++ __get_user_asm(x_u8__, ptr, retval, "b", "=q"); \ ++ (x) = x_u8__; \ + break; \ + case 2: \ + __get_user_asm(x, ptr, retval, "w", "=r"); \