Name all the generated ClockDomains

jerryz123 · jerryz123 · commit 2d2abed586b2 · 2024-05-30T14:45:24.000-07:00
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -37,7 +37,8 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
 
   // Set up clock domain
   private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
-  val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
+  val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
+    .suggestName("chipyard_prcictrl_domain")
 
   val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
   prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
diff --git a/generators/rocket-chip b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit a2356842423c884863140745f686ec81d3544d07
+Subproject commit 3cec0f0dee432d6bb2da5ce6aa1142474807ff86
diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks
@@ -1 +1 @@
-Subproject commit 2fc961f356b1104a34567adeefa9e3666940643f
+Subproject commit c667be9bb32f25e52516e71cd1ded58290ac5993
diff --git a/generators/testchipip b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 104df6a81fd989cd4cad69b699894664fcf93c05
+Subproject commit 7a30dc737d0d93e1e1926d56f7361d4b70ff5fe7
