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ChrisqcwxChrisqcwx
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fix some bugs in addrTrans & test (#293)
* fix some bugs * remove some comment
1 parent f5a6ab7 commit 08fdbac

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6 files changed

+48
-44
lines changed

6 files changed

+48
-44
lines changed

‎src/src/pipeline/memory/AddrTransStage.scala‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -44,12 +44,16 @@ class AddrTransStage
4444
AddrTransNdPort.default,
4545
Some(new AddrTransPeerPort)
4646
) {
47-
val selectedIn = io.in.bits
48-
val peer = io.peer.get
49-
val out = if (isNoPrivilege) io.out.bits else resultOutReg.bits
47+
val selectedIn = io.in.bits
48+
val selectedInVirtAddr = Cat(selectedIn.memRequest.addr(wordLength - 1, 2), 0.U(2.W))
49+
val peer = io.peer.get
50+
val resultOut = WireDefault(0.U.asTypeOf(Valid(new MemReqNdPort)))
51+
val out = resultOut.bits
52+
resultOutReg := resultOut
5053
if (isNoPrivilege) {
5154
io.in.ready := io.out.ready
5255
io.out.valid := io.in.valid
56+
io.out.bits := resultOut.bits
5357
}
5458

5559
val tlbBlockingReg = RegInit(false.B)

‎src/test/src/ComponentSpec.scala‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
import chisel3._
2-
import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3-
import chiseltest._
4-
import chiseltest.simulator.WriteVcdAnnotation
5-
import pipeline.dispatch.bundles.FetchInstInfoBundle
6-
import pipeline.queue.InstQueue
7-
import utest._
1+
// import chisel3._
2+
// import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3+
// import chiseltest._
4+
// import chiseltest.simulator.WriteVcdAnnotation
5+
// import pipeline.dispatch.bundles.FetchInstInfoBundle
6+
// import pipeline.queue.InstQueue
7+
// import utest._
88

99
// object ComponentSpec extends ChiselUtestTester {
1010
// val tests = Tests {

‎src/test/src/DataForwardSpec.scala‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
import chisel3._
2-
import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3-
import chiseltest._
4-
import chiseltest.simulator.WriteVcdAnnotation
5-
import pipeline.dispatch.bundles.FetchInstInfoBundle
6-
import pipeline.queue.InstQueue
7-
import utest._
1+
// import chisel3._
2+
// import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3+
// import chiseltest._
4+
// import chiseltest.simulator.WriteVcdAnnotation
5+
// import pipeline.dispatch.bundles.FetchInstInfoBundle
6+
// import pipeline.queue.InstQueue
7+
// import utest._
88

99
// import pipeline.dataforward.DataForwardStage
1010

‎src/test/src/ExeStageSpecs/testClz.scala‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
1-
import chisel3._
2-
import chisel3.util._
3-
import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
4-
import chiseltest._
5-
import chiseltest.simulator.WriteVcdAnnotation
6-
import pipeline.dispatch.bundles.FetchInstInfoBundle
7-
import utest._
8-
import pipeline.execution.Clz
9-
import pipeline.queue.InstQueue
10-
import scala.util.Random
1+
// import chisel3._
2+
// import chisel3.util._
3+
// import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
4+
// import chiseltest._
5+
// import chiseltest.simulator.WriteVcdAnnotation
6+
// import pipeline.dispatch.bundles.FetchInstInfoBundle
7+
// import utest._
8+
// import pipeline.execution.Clz
9+
// import pipeline.queue.InstQueue
10+
// import scala.util.Random
1111

1212
// object ComponentSpec extends ChiselUtestTester {
1313
// val tests = Tests {

‎src/test/src/InstQueueSpec.scala‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
1-
import chisel3._
2-
import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3-
import chiseltest._
4-
import chiseltest.simulator.WriteVcdAnnotation
5-
import pipeline.dispatch.bundles.FetchInstInfoBundle
6-
import utest._
7-
import control.bundles.PipelineControlNdPort
8-
import pipeline.queue.InstQueue
9-
import spec.wordLength
10-
import spec.zeroWord
1+
// import chisel3._
2+
// import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3+
// import chiseltest._
4+
// import chiseltest.simulator.WriteVcdAnnotation
5+
// import pipeline.dispatch.bundles.FetchInstInfoBundle
6+
// import utest._
7+
// import control.bundles.PipelineControlNdPort
8+
// import pipeline.queue.InstQueue
9+
// import spec.wordLength
10+
// import spec.zeroWord
1111

1212
// object InstQueueSpec extends ChiselUtestTester {
1313
// val tests = Tests {

‎src/test/src/SimpleCpuSpec.scala‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
1-
import chisel3._
2-
import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3-
import chiseltest._
4-
import chiseltest.simulator.WriteVcdAnnotation
5-
import pipeline.dispatch.bundles.FetchInstInfoBundle
6-
import pipeline.queue.InstQueue
7-
import utest._
1+
// import chisel3._
2+
// import chisel3.experimental.BundleLiterals.AddBundleLiteralConstructor
3+
// import chiseltest._
4+
// import chiseltest.simulator.WriteVcdAnnotation
5+
// import pipeline.dispatch.bundles.FetchInstInfoBundle
6+
// import pipeline.queue.InstQueue
7+
// import utest._
88

99
// object SimpleCpuSpec extends ChiselUtestTester {
1010
// val tests = Tests {

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