refactor: remove inst, pc, vaddr in inst info (#283)

* refactor: remove pc, inst, idxInBlock signal in inst info port

* refactor: remove vaddr from inst info

* fix: excp vaddr assign error in addrTrans

* fix: no initialize error in addr trans

* feat: optimize register usage in DCache

* fix connection error

---------

Co-authored-by: Takehana <cowpowermax@pm.me>

Author: Chrisqcwx

src/src/CoreCpuTop.scala

@@ -16,6 +16,7 @@ import spec.Param.isDiffTest
 import control.Cu
 import pmu.Pmu
 import pmu.bundles.PmuNdPort
+import spec.ExeInst
 
 class CoreCpuTop extends Module {
   val io = IO(new Bundle {
@@ -220,6 +221,7 @@ class CoreCpuTop extends Module {
 
   exePassWbStage_1.io.peer.get.csrReadPort.get           <> csr.io.readPorts(0)
   exePassWbStage_1.io.peer.get.stableCounterReadPort.get <> stableCounter.io
+  exePassWbStage_1.io.peer.get.robQueryPcPort.get        <> rob.io.queryPcPort
   assert(Param.loadStoreIssuePipelineIndex == 0)
   exePassWbStages.zipWithIndex.foreach {
     case (exe, idx) =>
@@ -300,8 +302,10 @@ class CoreCpuTop extends Module {
   cu.io.branchExe          := exePassWbStages(Param.jumpBranchPipelineIndex - 1).io.peer.get.branchSetPort.get
   cu.io.redirectFromDecode := instQueue.io.redirectRequest
 
-  cu.io.csrFlushRequest := csr.io.csrFlushRequest
-  cu.io.csrWriteInfo    := csrScoreBoard.io.csrWritePort
+  cu.io.csrFlushRequest   := csr.io.csrFlushRequest
+  cu.io.csrWriteInfo      := csrScoreBoard.io.csrWritePort
+  cu.io.majorPc           := commitStage.io.majorPc
+  cu.io.exceptionVirtAddr := addrTransStage.io.peer.get.exceptionVirtAddr
 
   // CSR
   csr.io.writePorts.zip(cu.io.csrWritePorts).foreach {
@@ -322,8 +326,8 @@ class CoreCpuTop extends Module {
   csr.io.hardwareInterrupt := io.intrpt
 
   // Debug ports
-  io.debug0_wb.pc   := commitStage.io.ins(0).bits.instInfo.pc
-  io.debug0_wb.inst := commitStage.io.ins(0).bits.instInfo.inst
+  io.debug0_wb.pc   := commitStage.io.ins(0).bits.fetchInfo.pcAddr
+  io.debug0_wb.inst := commitStage.io.ins(0).bits.fetchInfo.inst
   io.debug0_wb.rf.wen := VecInit(
     Seq.fill(4)(
       commitStage.io.gprWritePorts(0).en && commitStage.io.ins(0).bits.instInfo.isValid && commitStage.io

src/src/control/Cu.scala

@@ -10,6 +10,7 @@ import spec.Param.isDiffTest
 import spec.{Csr, ExeInst, Param}
 import frontend.bundles.CuCommitFtqNdPort
 import frontend.bundles.QueryPcBundle
+import spec.Width
 
 // Note. Exception只从第0个提交
 class Cu(
@@ -21,6 +22,7 @@ class Cu(
     // `WbStage` -> `Cu` -> `Regfile`
     val gprWritePassThroughPorts = new PassThroughPort(Vec(commitNum, new RfWriteNdPort))
     val instInfoPorts            = Input(Vec(commitNum, new InstInfoNdPort))
+    val majorPc                  = Input(UInt(Width.Reg.data))
     // `Cu` -> `Csr`, 软件写
     val csrWritePorts = Output(Vec(writeNum, new CsrWriteNdPort))
     // `Cu` -> `Csr`, 硬件写
@@ -49,6 +51,8 @@ class Cu(
     val ftqPort     = Output(new CuCommitFtqNdPort)
     val queryPcPort = Flipped(new QueryPcBundle)
 
+    val exceptionVirtAddr = Input(UInt(Width.Mem.addr))
+
     val isDbarFinish = Output(Bool())
 
     val difftest = if (isDiffTest) {
@@ -65,7 +69,7 @@ class Cu(
   // Values
   val majorInstInfo = io.instInfoPorts.head
   io.queryPcPort.ftqId := majorInstInfo.ftqInfo.ftqId
-  val majorPc: UInt = WireDefault(io.queryPcPort.pc + (majorInstInfo.ftqInfo.idxInBlock << 2))
+  val majorPc     = io.majorPc // : UInt = WireDefault(io.queryPcPort.pc + (majorInstInfo.ftqInfo.idxInBlock << 2))
   val isException = (majorInstInfo.exceptionPos =/= ExceptionPos.none) && majorInstInfo.isValid
 
   // Write GPR
@@ -159,7 +163,7 @@ class Cu(
       io.csrMessage.badVAddrSet.en := true.B
       io.csrMessage.badVAddrSet.addr := Mux(
         majorInstInfo.exceptionPos === ExceptionPos.backend,
-        majorInstInfo.vaddr,
+        io.exceptionVirtAddr,
         majorPc
       )
     }

src/src/frontend/fetch/InstResStage.scala

@@ -41,8 +41,8 @@ class InstResStage
 
   out.enqInfos.zipWithIndex.foreach {
     case (infoBundle, index) =>
-      infoBundle.bits.pcAddr             := selectedIn.ftqBlock.startPc + index.asUInt(Width.Mem.addr) * 4.U
-      infoBundle.bits.ftqInfo.idxInBlock := index.U
+      infoBundle.bits.pcAddr := selectedIn.ftqBlock.startPc + index.asUInt(Width.Mem.addr) * 4.U
+      // infoBundle.bits.ftqInfo.idxInBlock := index.U
       if (Param.fetchInstMaxNum == 1) {
         infoBundle.bits.inst := peer.memRes.read.dataVec(0)
         infoBundle.valid     := true.B

src/src/memory/DCache.scala

@@ -231,7 +231,6 @@ class DCache(
     val writeData      = UInt(Width.Mem.data)
     val writeMask      = UInt(Width.Mem.data)
     val isWrite        = Bool()
-    val writeDataLine  = Vec(Param.Count.DCache.dataPerLine, UInt(Width.Mem.data))
   }))
   lastReg         := lastReg // Fallback: Keep data
   lastReg.isWrite := false.B
@@ -326,7 +325,7 @@ class DCache(
         lastReg.memAddr(Width.Mem._addr - 1, Param.Width.DCache._byteOffset)
       val lastQueryIndex = queryIndexFromMemAddr(lastReg.memAddr)
       when(isLastMatched && lastReg.isWrite) {
-        selectedDataLine := lastReg.writeDataLine
+        selectedDataLine := lastReg.dataLine
       }
       when(lastQueryIndex === queryIndex) {
         statusTagLines.zipWithIndex.foreach {
@@ -341,7 +340,6 @@ class DCache(
       lastReg.memAddr        := reqMemAddr
       lastReg.statusTagLines := statusTagLines
       lastReg.setIndex       := setIndex
-      lastReg.dataLine       := selectedDataLine
       lastReg.writeData      := reqWriteData
       lastReg.writeMask      := reqWriteMask
 
@@ -376,7 +374,7 @@ class DCache(
                 case (data, index) =>
                   Mux(index.U === dataIndex, newData, data)
               }))
-              lastReg.writeDataLine := writeDataLine
+              lastReg.dataLine := writeDataLine
 
               // Set dirty bit
               writeStatusTag.isDirty := true.B
@@ -442,7 +440,7 @@ class DCache(
           lastReg.setIndex := refillSetIndex
           lastReg.dataLine := toDataLine(dataLines(refillSetIndex))
           when(lastReg.isWrite && refillSetIndex === lastReg.setIndex && queryIndex === lastQueryIndex) {
-            lastReg.dataLine := lastReg.writeDataLine
+            lastReg.dataLine := lastReg.dataLine
           }
 
           // Init refill state regs

src/src/pipeline/commit/CommitStage.scala

@@ -10,6 +10,8 @@ import pipeline.dispatch.bundles.ScoreboardChangeNdPort
 import spec.Param.isDiffTest
 import spec._
 import pmu.bundles.PmuBranchPredictNdPort
+import pipeline.dispatch.bundles.FetchInstInfoBundle
+import pipeline.commit.bundles.PcInstBundle
 
 class WbNdPort extends Bundle {
   val gprWrite = new RfWriteNdPort
@@ -20,17 +22,26 @@ object WbNdPort {
   def default = 0.U.asTypeOf(new WbNdPort)
 }
 
+class CommitNdPort extends Bundle {
+  val gprWrite  = new RfWriteNdPort
+  val instInfo  = new InstInfoNdPort
+  val fetchInfo = new PcInstBundle
+}
+
+object CommitNdPort {
+  def default = 0.U.asTypeOf(new CommitNdPort)
+}
+
 class CommitStage(
   commitNum: Int = Param.commitNum)
     extends Module {
   val io = IO(new Bundle {
-    val ins = Vec(commitNum, Flipped(Decoupled(new WbNdPort)))
+    val ins = Vec(commitNum, Flipped(Decoupled(new CommitNdPort)))
 
     // `CommitStage` -> `Cu` NO delay
-    val gprWritePorts = Output(Vec(commitNum, new RfWriteNdPort))
-
-    // `AddrTransStage` -> `CommitStage` -> `Cu` NO delay
+    val gprWritePorts   = Output(Vec(commitNum, new RfWriteNdPort))
     val cuInstInfoPorts = Output(Vec(commitNum, new InstInfoNdPort))
+    val majorPc         = Output(UInt(Width.Reg.data))
 
     val pmu_branchInfo = if (Param.usePmu) Some(Output(new PmuBranchPredictNdPort)) else None
 
@@ -79,6 +90,7 @@ class CommitStage(
       dstGprWrite         := inBit.gprWrite
       dstGprWrite.en      := in.valid && in.ready && inBit.gprWrite.en
   }
+  io.majorPc := inBits.head.fetchInfo.pcAddr
 
   io.pmu_branchInfo match {
     case None =>
@@ -97,14 +109,14 @@ class CommitStage(
   io.difftest match {
     case Some(dt) =>
       dt.valid := RegNext(inBits(0).instInfo.isValid && io.ins(0).valid && io.ins(0).ready, false.B) // && nextCommit)
-      dt.pc    := RegNext(inBits(0).instInfo.pc, 0.U)
-      dt.instr := RegNext(inBits(0).instInfo.inst, 0.U)
+      dt.pc    := RegNext(inBits(0).fetchInfo.pcAddr, 0.U)
+      dt.instr := RegNext(inBits(0).fetchInfo.inst, 0.U)
       dt.wen   := RegNext(inBits(0).gprWrite.en, false.B)
       dt.wdest := RegNext(inBits(0).gprWrite.addr, 0.U)
       dt.wdata := RegNext(inBits(0).gprWrite.data, 0.U)
       dt.csr_rstat := RegNext(
-        inBits(0).instInfo.inst(31, 24) === Inst._2RI14.csr_ &&
-          inBits(0).instInfo.inst(23, 10) === "h5".U,
+        inBits(0).fetchInfo.inst(31, 24) === Inst._2RI14.csr_ &&
+          inBits(0).fetchInfo.inst(23, 10) === "h5".U,
         false.B
       ) && io.ins(0).valid && io.ins(0).ready
       dt.ld_en    := RegNext(inBits(0).instInfo.load.get.en, false.B)
@@ -127,8 +139,8 @@ class CommitStage(
 
       if (commitNum == 2) {
         dt.valid_1 := RegNext(inBits(1).instInfo.isValid && io.ins(1).valid && io.ins(1).ready, false.B)
-        dt.instr_1 := RegNext(inBits(1).instInfo.inst, 0.U)
-        dt.pc_1    := RegNext(inBits(1).instInfo.pc, 0.U)
+        dt.instr_1 := RegNext(inBits(1).fetchInfo.inst, 0.U)
+        dt.pc_1    := RegNext(inBits(1).fetchInfo.pcAddr, 0.U)
         dt.wen_1   := RegNext(inBits(1).gprWrite.en, false.B)
         dt.wdest_1 := RegNext(inBits(1).gprWrite.addr, 0.U)
         dt.wdata_1 := RegNext(inBits(1).gprWrite.data, 0.U)

src/src/pipeline/commit/bundles/InstInfoNdPort.scala

@@ -11,15 +11,11 @@ import pipeline.dispatch.bundles.FtqInfoBundle
 
 class InstInfoNdPort extends Bundle {
   val isValid         = Bool()
-  val pc              = UInt(Width.Reg.data)
-  val inst            = UInt(Width.Reg.data)
   val exceptionPos    = ExceptionPos()
   val exceptionRecord = UInt(Csr.ExceptionIndex.width)
   val isStore         = Bool()
-  val vaddr           = UInt(Width.Mem.addr)
   val needRefetch     = Bool()
   val isCsrWrite      = Bool()
-  val branchSuccess   = Bool()
 
   val exeOp = UInt(Param.Width.exeOp)
   val robId = UInt(Param.Width.Rob.id)
@@ -48,7 +44,6 @@ object InstInfoNdPort {
     instInfo.isTlb                := false.B
     instInfo.isStore              := false.B
     instInfo.forbidParallelCommit := false.B
-    instInfo.branchSuccess        := false.B
 
     if (isDiffTest) {
       instInfo.load.get.en  := false.B

src/src/pipeline/commit/bundles/PcInstBundle.scala

@@ -0,0 +1,8 @@
+package pipeline.commit.bundles
+import chisel3._
+import spec._
+
+class PcInstBundle extends Bundle {
+  val pcAddr = UInt(Width.Reg.data)
+  val inst   = UInt(Width.Reg.data)
+}

src/src/pipeline/dispatch/NewDispatchStage.scala

@@ -95,7 +95,7 @@ class NewDispatchStage(
     }
   }
 
-  // dontcare if input valid
+  // dontcare if input not valid
   val dispatchMap = WireDefault(VecInit(Seq.fill(issueNum)(VecInit(Seq.fill(pipelineNum)(false.B)))))
   val srcEns      = WireDefault(VecInit(dispatchMap.map(_.reduceTree(_ || _))))
   val dstEns = WireDefault(dispatchMap.reduce { (a, b) =>

src/src/pipeline/dispatch/NewRenameStage.scala

@@ -123,6 +123,7 @@ class NewRenameStage(
         case (dst, src) =>
           dst := src
       }
+      req.bits.fetchInfo := in.fetchInfo
   }
 
   // -> reservation station

src/src/pipeline/dispatch/bundles/FtqInfoBundle.scala

@@ -8,7 +8,7 @@ import chisel3.util.log2Ceil
 class FtqInfoBundle extends Bundle {
   val isLastInBlock = Bool()
   val ftqId         = UInt(Param.BPU.Width.id)
-  val idxInBlock    = UInt(log2Ceil(Param.fetchInstMaxNum).W)
+  // val idxInBlock    = UInt(log2Ceil(Param.fetchInstMaxNum).W)
   val predictBranch = Bool()
 }