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refactor & fix pmu (#281)
* refactor pmu * fix: pmu assign error
1 parent b41948b commit bba7e79

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5 files changed

+29
-24
lines changed

5 files changed

+29
-24
lines changed

src/src/CoreCpuTop.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -345,7 +345,7 @@ class CoreCpuTop extends Module {
345345
case (dst, src) =>
346346
dst := src
347347
}
348-
pmu.io.robFull := rob.io.requests.head.ready && !cu.io.backendFlush
348+
pmu.io.robFull := !rob.io.requests.head.ready && !cu.io.backendFlush
349349

350350
}
351351

src/src/pipeline/dispatch/rs/InOrderReservationStation.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ class InOrderReservationStation(
156156
val pmu = io.pmu_dispatchInfo.get
157157
val isFull = !queue.io.enqueuePorts.head.ready
158158
val isEmpty = !queue.io.dequeuePorts.head.valid
159+
pmu.enqueue := io.enqueuePorts.head.valid && io.enqueuePorts.head.ready && !io.isFlush
159160
pmu.isFull := isFull && !io.isFlush
160161
pmu.bubbleFromBackend := io.dequeuePorts.head.valid && !io.dequeuePorts.head.ready && !io.isFlush
161162
pmu.bubbleFromRSEmpty := isEmpty && !io.isFlush

src/src/pipeline/dispatch/rs/SimpleOoOReservationStation.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -215,6 +215,7 @@ class SimpleOoOReservationStation(
215215

216216
if (Param.usePmu) {
217217
val pmu = io.pmu_dispatchInfo.get
218+
pmu.enqueue := io.enqueuePorts.head.valid && io.enqueuePorts.head.ready && !io.isFlush
218219
pmu.isFull := isFull && !io.isFlush
219220
pmu.bubbleFromBackend := io.dequeuePorts.head.valid && !io.dequeuePorts.head.ready && !io.isFlush
220221
pmu.bubbleFromRSEmpty := isEmpty && !io.isFlush

src/src/pmu/Pmu.scala

Lines changed: 25 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ class Pmu extends Module {
5151
val dispatchBubbleFromDataDependences = Seq.fill(Param.pipelineNum)(r)
5252
val dispatchBubbleFromRSEmptys = Seq.fill(Param.pipelineNum)(r)
5353
val dispatchRSFulls = Seq.fill(Param.pipelineNum)(r)
54+
val dispatchRSEnqueueNum = Seq.fill(Param.pipelineNum)(r)
5455

5556
io.dispatchInfos.zipWithIndex.foreach {
5657
case (dispatchInfo, idx) =>
@@ -66,26 +67,27 @@ class Pmu extends Module {
6667
when(dispatchInfo.bubbleFromRSEmpty) {
6768
inc(dispatchBubbleFromRSEmptys(idx))
6869
}
70+
condInc(dispatchRSEnqueueNum(idx), dispatchInfo.enqueue)
6971
}
7072

7173
val robFull = r
7274
when(io.robFull) {
7375
inc(robFull)
7476
}
7577

76-
val branch = r
77-
val branchSuccess = r
78-
val branchFail = r
79-
val unconditionalBranch = r
80-
val unconditionalBranchFail = r
81-
val conditionalBranch = r
82-
val conditionalBranchFail = r
83-
val callBranch = r
84-
val callBranchFail = r
85-
val returnBranch = r
86-
val returnBranchFail = r
87-
val directionMispredict = r
88-
val targetMispredict = r
78+
val branch = r
79+
val branchSuccess = r
80+
val branchFail = r
81+
val branchUnconditional = r
82+
val branchUnconditionalFail = r
83+
val branchConditional = r
84+
val branchConditionalFail = r
85+
val branchCall = r
86+
val branchCallFail = r
87+
val branchReturn = r
88+
val branchReturnFail = r
89+
val branchDirectionMispredict = r
90+
val branchTargetMispredict = r
8991

9092
when(io.branchInfo.isBranch) {
9193
inc(branch)
@@ -95,32 +97,32 @@ class Pmu extends Module {
9597
inc(branchSuccess)
9698
}
9799

98-
condInc(directionMispredict, io.branchInfo.directionMispredict)
99-
condInc(targetMispredict, io.branchInfo.targetMispredict)
100+
condInc(branchDirectionMispredict, io.branchInfo.directionMispredict)
101+
condInc(branchTargetMispredict, io.branchInfo.targetMispredict)
100102

101103
switch(io.branchInfo.branchType) {
102104
is(Param.BPU.BranchType.uncond) {
103-
inc(unconditionalBranch)
105+
inc(branchUnconditional)
104106
when(io.branchInfo.isRedirect) {
105-
inc(unconditionalBranchFail)
107+
inc(branchUnconditionalFail)
106108
}
107109
}
108110
is(Param.BPU.BranchType.cond) {
109-
inc(conditionalBranch)
111+
inc(branchConditional)
110112
when(io.branchInfo.isRedirect) {
111-
inc(conditionalBranchFail)
113+
inc(branchConditionalFail)
112114
}
113115
}
114116
is(Param.BPU.BranchType.call) {
115-
inc(callBranch)
117+
inc(branchCall)
116118
when(io.branchInfo.isRedirect) {
117-
inc(callBranchFail)
119+
inc(branchCallFail)
118120
}
119121
}
120122
is(Param.BPU.BranchType.ret) {
121-
inc(returnBranch)
123+
inc(branchReturn)
122124
when(io.branchInfo.isRedirect) {
123-
inc(returnBranchFail)
125+
inc(branchReturnFail)
124126
}
125127
}
126128
}

src/src/pmu/bundles/PmuDispatchBundle.scala

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,4 +8,5 @@ class PmuDispatchBundle extends Bundle {
88
val bubbleFromDataDependence = Bool()
99
val bubbleFromRSEmpty = Bool()
1010
val isFull = Bool()
11+
val enqueue = Bool()
1112
}

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