diff --git a/src/src/common/Pc.scala b/src/src/common/Pc.scala
index 8c814692..c15f330c 100644
--- a/src/src/common/Pc.scala
+++ b/src/src/common/Pc.scala
@@ -21,10 +21,13 @@ class Pc(
   val pcReg = RegInit(spec.Pc.init)
   io.pc := pcReg
 
+  val canIncReg = RegInit(true.B)
+
   pcReg := pcReg
   when(io.newPc.en) {
-    pcReg := io.newPc.pcAddr
-  }.elsewhen(io.isNext) {
+    pcReg     := io.newPc.pcAddr
+    canIncReg := !io.newPc.isIdle
+  }.elsewhen(io.isNext && canIncReg) {
     // pcReg := pcReg + (4 * issueNum).U
     pcReg := pcReg + 4.U
   }
diff --git a/src/src/common/bundles/PcSetPort.scala b/src/src/common/bundles/PcSetPort.scala
index 7a49dc11..62c384bf 100644
--- a/src/src/common/bundles/PcSetPort.scala
+++ b/src/src/common/bundles/PcSetPort.scala
@@ -6,6 +6,7 @@ import spec._
 import chisel3.experimental.BundleLiterals._
 
 class PcSetPort extends Bundle {
+  val isIdle = Bool()
   val en     = Bool()
   val pcAddr = UInt(Width.Reg.data)
 }
@@ -13,6 +14,7 @@ class PcSetPort extends Bundle {
 object PcSetPort {
   val default = (new PcSetPort).Lit(
     _.en -> false.B,
-    _.pcAddr -> zeroWord
+    _.pcAddr -> zeroWord,
+    _.isIdle -> false.B
   )
 }
diff --git a/src/src/control/Cu.scala b/src/src/control/Cu.scala
index 1ab921a9..f64129a3 100644
--- a/src/src/control/Cu.scala
+++ b/src/src/control/Cu.scala
@@ -229,12 +229,9 @@ class Cu(
   }
 
   // select new pc
-  // when(ertnFlush) {
-  //   io.newPc.en     := true.B
-  //   io.newPc.pcAddr := io.csrValues.era.asUInt
-  // }.else
   when(exceptionFlush) {
-    io.newPc.en := true.B
+    io.newPc.en     := true.B
+    io.newPc.isIdle := false.B
     when(isTlbRefillException) {
       io.newPc.pcAddr := io.csrValues.tlbrentry.asUInt
     }.otherwise {
diff --git a/src/src/frontend/InstFetchStage.scala b/src/src/frontend/InstFetchStage.scala
index 43ef2066..f02304ec 100644
--- a/src/src/frontend/InstFetchStage.scala
+++ b/src/src/frontend/InstFetchStage.scala
@@ -23,6 +23,8 @@ class InstFetchStage extends Module {
     val instEnqueuePort = Decoupled(new InstInfoBundle)
   })
 
+  io.instEnqueuePort.bits := InstInfoBundle.default
+
   io.instEnqueuePort.bits.pcAddr := io.pc
   io.instEnqueuePort.bits.inst   := io.accessPort.res.read.data
 
diff --git a/src/src/pipeline/common/MultiQueue.scala b/src/src/pipeline/common/MultiQueue.scala
index 4752012b..d040e313 100644
--- a/src/src/pipeline/common/MultiQueue.scala
+++ b/src/src/pipeline/common/MultiQueue.scala
@@ -6,12 +6,14 @@ import spec._
 import utils.MultiCounter
 
 class MultiQueue[ElemT <: Data](
-  queueLength:   Int,
-  enqMaxNum:     Int,
-  deqMaxNum:     Int,
-  elemNdFactory: => ElemT,
-  blankElem:     => ElemT,
-  writeFirst:    Boolean = true)
+  queueLength:        Int,
+  enqMaxNum:          Int,
+  deqMaxNum:          Int,
+  elemNdFactory:      => ElemT,
+  blankElem:          => ElemT,
+  needValidPorts:     Boolean = false,
+  isRelativePosition: Boolean = false,
+  writeFirst:         Boolean = true)
     extends Module {
 
   val io = IO(new Bundle {
@@ -19,18 +21,18 @@ class MultiQueue[ElemT <: Data](
     val enqueuePorts = Vec(enqMaxNum, Flipped(Decoupled(elemNdFactory)))
     val dequeuePorts = Vec(deqMaxNum, Decoupled(elemNdFactory))
 
-    val setPorts = Input(Vec(queueLength, ValidIO(elemNdFactory)))
-    val elems    = Output(Vec(queueLength, elemNdFactory))
+    // deq_ptr -> enq_ptr
+    val setPorts   = Input(Vec(queueLength, ValidIO(elemNdFactory)))
+    val elems      = Output(Vec(queueLength, elemNdFactory))
+    val elemValids = if (needValidPorts) Some(Output(Vec(queueLength, Bool()))) else None
   })
 
   require(queueLength > enqMaxNum)
   require(queueLength > deqMaxNum)
 
-  val ram = RegInit(VecInit(Seq.fill(queueLength)(blankElem)))
-  io.elems.zip(ram).foreach {
-    case (dst, src) =>
-      dst := src
-  }
+  val ram       = RegInit(VecInit(Seq.fill(queueLength)(blankElem)))
+  val ramValids = RegInit(VecInit(Seq.fill(queueLength)(false.B)))
+
   val enq_ptr = Module(new MultiCounter(queueLength, enqMaxNum))
   val deq_ptr = Module(new MultiCounter(queueLength, deqMaxNum))
 
@@ -79,10 +81,14 @@ class MultiQueue[ElemT <: Data](
   val dequeueNum = deqEn.map(_.asUInt).reduce(_ +& _)
 
   if (!writeFirst) {
-    ram.zip(io.setPorts).foreach {
-      case (r, s) =>
+    io.setPorts.zipWithIndex.foreach {
+      case (s, idx) =>
         when(s.valid) {
-          r := s.bits
+          if (isRelativePosition) {
+            ram(deq_ptr.io.incResults(idx)) := s.bits
+          } else {
+            ram(idx) := s.bits
+          }
         }
     }
   }
@@ -97,25 +103,54 @@ class MultiQueue[ElemT <: Data](
   io.enqueuePorts.lazyZip(enqEn).zipWithIndex.foreach {
     case ((enqPort, en), idx) =>
       when(idx.U < enqueueNum) {
-        ram(enq_ptr.io.incResults(idx)) := enqPort.bits
+        ram(enq_ptr.io.incResults(idx))       := enqPort.bits
+        ramValids(enq_ptr.io.incResults(idx)) := true.B
       }
   }
 
   deq_ptr.io.inc := dequeueNum
   io.dequeuePorts.zipWithIndex.foreach {
     case (deq, idx) =>
-      deq.bits := ram(deq_ptr.io.incResults(idx))
+      deq.bits                              := ram(deq_ptr.io.incResults(idx))
+      ramValids(deq_ptr.io.incResults(idx)) := false.B
   }
 
   if (writeFirst) {
-    ram.zip(io.setPorts).foreach {
-      case (r, s) =>
+    io.setPorts.zipWithIndex.foreach {
+      case (s, idx) =>
         when(s.valid) {
-          r := s.bits
+          if (isRelativePosition) {
+            ram(deq_ptr.io.incResults(idx)) := s.bits
+          } else {
+            ram(idx) := s.bits
+          }
         }
     }
   }
 
+  io.elems.zipWithIndex.foreach {
+    case (dst, idx) =>
+      if (isRelativePosition) {
+        dst := ram(deq_ptr.io.incResults(idx))
+      } else {
+        dst := ram(idx)
+      }
+
+  }
+
+  io.elemValids match {
+    case Some(elemValids) =>
+      io.elemValids.zipWithIndex.foreach {
+        case (dst, idx) =>
+          if (isRelativePosition) {
+            dst := ramValids(deq_ptr.io.incResults(idx))
+          } else {
+            dst := ramValids(idx)
+          }
+      }
+    case None =>
+  }
+
   when(io.isFlush) {
     ram.foreach(_ := blankElem)
     maybeFull := false.B
diff --git a/src/src/pipeline/dispatch/IssueStage.scala b/src/src/pipeline/dispatch/IssueStage.scala
index 8d438114..38eb7c91 100644
--- a/src/src/pipeline/dispatch/IssueStage.scala
+++ b/src/src/pipeline/dispatch/IssueStage.scala
@@ -15,6 +15,9 @@ import pipeline.common.MultiBaseStage
 import pipeline.execution.ExeNdPort
 import pipeline.dispatch.FetchInstDecodeNdPort
 import pipeline.rob.bundles.InstWbNdPort
+import pipeline.common.MultiQueue
+import pipeline.dispatch.bundles.ReservationStationBundle
+import pipeline.rob.enums.RobDistributeSel
 
 // class FetchInstDecodeNdPort extends Bundle {
 //   val decode   = new DecodeOutNdPort
@@ -29,14 +32,14 @@ import pipeline.rob.bundles.InstWbNdPort
 // }
 
 class IssueStagePeerPort(
-  issueNum:       Int = Param.issueInstInfoMaxNum,
-  pipelineNum:    Int = Param.pipelineNum,
-  scoreChangeNum: Int = Param.regFileWriteNum)
+  issueNum:    Int = Param.issueInstInfoMaxNum,
+  pipelineNum: Int = Param.pipelineNum)
     extends Bundle {
 
   // `IssueStage` <-> `Rob`
-  val requests = Output(Vec(issueNum, new RobReadRequestNdPort))
-  val results  = Input(Vec(issueNum, new RobReadResultNdPort))
+  val robEmptyNum = Input(UInt(Param.Width.Rob.addr))
+  val requests    = Output(Vec(issueNum, new RobReadRequestNdPort))
+  val results     = Input(Vec(issueNum, new RobReadResultNdPort))
 
   // `LSU / ALU` -> `IssueStage
   val writebacks = Input(Vec(pipelineNum, new InstWbNdPort))
@@ -47,12 +50,17 @@ class IssueStagePeerPort(
 }
 
 // dispatch & Reservation Stations
-class IssueStage
+class IssueStage(
+  issueNum:          Int = Param.issueInstInfoMaxNum,
+  pipelineNum:       Int = Param.pipelineNum,
+  reservationLength: Int = spec.Param.reservationStationDeep)
     extends MultiBaseStage(
       new FetchInstDecodeNdPort,
       new ExeNdPort,
       FetchInstDecodeNdPort.default,
-      Some(new IssueStagePeerPort)
+      Some(new IssueStagePeerPort),
+      issueNum,
+      pipelineNum
     ) {
 
   // Fallback
@@ -60,4 +68,132 @@ class IssueStage
   io.peer.get.csrOccupyPort := ScoreboardChangeNdPort.default
   io.peer.get.requests.foreach(_ := RobReadRequestNdPort.default)
 
+  val reservationStations = Seq.fill(pipelineNum)(
+    Module(new MultiQueue(reservationLength, 1, 1, new ReservationStationBundle, ReservationStationBundle.default))
+  )
+
+  // fall back
+  reservationStations.foreach { port =>
+    port.io.enqueuePorts(0).valid := false.B
+    port.io.enqueuePorts(0).bits  := DontCare
+  }
+  reservationStations.foreach(_.io.dequeuePorts(0).ready := false.B)
+  // TODO: BRANCH CONDITION
+  reservationStations.foreach(_.io.isFlush := io.isFlush)
+  reservationStations.foreach(_.io.setPorts.foreach { port =>
+    port.valid := false.B
+    port.bits  := DontCare
+  })
+
+  /** fetch -> reservation stations
+    */
+
+  val readyReservations = WireDefault(VecInit(reservationStations.map(_.io.enqueuePorts(0).ready)))
+
+  val dispatchMap  = WireDefault(VecInit(Seq.fill(issueNum)(VecInit(Seq.fill(pipelineNum)(false.B)))))
+  val canDispatchs = WireDefault(VecInit(dispatchMap.map(_.reduceTree(_ || _))))
+  isComputeds.lazyZip(canDispatchs).lazyZip(selectedIns).foreach {
+    case (isComputed, canDispatch, in) =>
+      isComputed := canDispatch || !in.instInfo.isValid
+  }
+  io.ins.zip(isLastComputeds).foreach {
+    case (in, isLastComputed) =>
+      in.ready := isLastComputed
+  }
+
+  selectedIns.lazyZip(dispatchMap).zipWithIndex.foreach {
+    case ((in, dispatchSel), src_idx) =>
+      when(in.instInfo.isValid) {
+        // select all dsts to dispatch
+        val dstReady = Wire(Vec(pipelineNum, Bool()))
+        dstReady.lazyZip(readyReservations).zipWithIndex.foreach {
+          case ((dispatchEn, ready), dst_idx) =>
+            //  Map condition src -> dst
+            //     1. dst ready
+            //     2. dst isn't occupied by previous srcs
+            //     3. previous srcs dispatch success
+            //     4. rob has empty position
+            //     5. in the right pipeline index
+            dispatchEn := ready &&
+              !dispatchMap.take(src_idx).map(_(dst_idx)).foldLeft(false.B)(_ || _) &&
+              canDispatchs.take(src_idx).foldLeft(true.B)(_ && _) &&
+              src_idx.U < io.peer.get.robEmptyNum
+            if (dst_idx != loadStoreIssuePipelineIndex) {
+              when(in.decode.info.exeSel === ExeInst.Sel.loadStore) {
+                dispatchEn := false.B
+              }
+            }
+            if (dst_idx != csrIssuePipelineIndex) {
+              when(in.instInfo.needCsr) {
+                dispatchEn := false.B
+              }
+            }
+        }
+        // select one
+        dispatchSel.zip(PriorityEncoderOH(dstReady)).foreach {
+          case (dst, src) =>
+            dst := src
+        }
+      }
+  }
+
+  // -> reservation stations
+  for (src_idx <- Seq.range(issueNum - 1, -1, -1)) {
+    for (dst_idx <- 0 to pipelineNum) {
+      when(dispatchMap(src_idx)(dst_idx)) {
+        // decode info
+        reservationStations(dst_idx).io.enqueuePorts(0).valid := true.B
+        reservationStations(dst_idx).io.enqueuePorts(0).bits.regReadPort.preExeInstInfo := selectedIns(
+          src_idx
+        ).decode.info
+        reservationStations(dst_idx).io.enqueuePorts(0).bits.regReadPort.instInfo := selectedIns(src_idx).instInfo
+
+        // rob result
+        io.peer.get.requests(src_idx).readRequests.zip(selectedIns(src_idx).decode.info.gprReadPorts).foreach {
+          case (req, decodeRead) =>
+            req := decodeRead
+        }
+        io.peer.get.requests(src_idx).writeRequest                     := selectedIns(src_idx).decode.info.gprWritePort
+        reservationStations(dst_idx).io.enqueuePorts(0).bits.robResult := io.peer.get.results(src_idx)
+
+        // commit result
+        io.peer.get.writebacks.foreach { writeback =>
+          selectedIns(src_idx).decode.info.gprReadPorts
+            .lazyZip(io.peer.get.results(src_idx).readResults)
+            .lazyZip(reservationStations(dst_idx).io.enqueuePorts(0).bits.robResult.readResults)
+            .foreach {
+              case (readPort, robResult, rs) =>
+                // may be error
+                when(writeback.en && readPort.en && writeback.robId === robResult.result) {
+                  rs.sel    := RobDistributeSel.realData
+                  rs.result := writeback.data
+                }
+            }
+        }
+
+        // imm
+        when(selectedIns(src_idx).decode.info.isHasImm) {
+          reservationStations(dst_idx).io.enqueuePorts(0).bits.robResult.readResults(1).sel := RobDistributeSel.realData
+          reservationStations(dst_idx).io.enqueuePorts(0).bits.robResult.readResults(1).result := selectedIns(
+            src_idx
+          ).decode.info.imm
+        }
+
+        // csr score board
+        io.peer.get.csrOccupyPort.en   := selectedIns(src_idx).decode.info.needCsr
+        io.peer.get.csrOccupyPort.addr := DontCare
+      }
+    }
+  }
+
+  /** commit --fill--> reservation stations
+    */
+
+  reservationStations.foreach { reservationStation =>
+    reservationStation.io.elems.zip(reservationStation.io.elemValids)
+  }
+
+  /** output
+    */
+
 }
diff --git a/src/src/pipeline/dispatch/bundles/InstInfoBundle.scala b/src/src/pipeline/dispatch/bundles/InstInfoBundle.scala
index f7a0b800..ab62b090 100644
--- a/src/src/pipeline/dispatch/bundles/InstInfoBundle.scala
+++ b/src/src/pipeline/dispatch/bundles/InstInfoBundle.scala
@@ -8,11 +8,19 @@ import spec._
 class InstInfoBundle extends Bundle {
   val pcAddr = UInt(Width.Reg.data)
   val inst   = UInt(Width.inst)
+  val isAdef = Bool()
+  val isPpi  = Bool()
+  val isPif  = Bool()
+  val isTlbr = Bool()
 }
 
 object InstInfoBundle {
   val default = (new InstInfoBundle).Lit(
     _.pcAddr -> zeroWord,
-    _.inst -> zeroWord
+    _.inst -> zeroWord,
+    _.isAdef -> false.B,
+    _.isPif -> false.B,
+    _.isPpi -> false.B,
+    _.isTlbr -> false.B
   )
 }
diff --git a/src/src/pipeline/dispatch/bundles/ReservationStationBundle.scala b/src/src/pipeline/dispatch/bundles/ReservationStationBundle.scala
new file mode 100644
index 00000000..15a77d73
--- /dev/null
+++ b/src/src/pipeline/dispatch/bundles/ReservationStationBundle.scala
@@ -0,0 +1,20 @@
+package pipeline.dispatch.bundles
+
+import chisel3._
+import chisel3.experimental.BundleLiterals._
+import chisel3.util._
+import spec._
+import pipeline.dispatch.RegReadNdPort
+import pipeline.rob.bundles.RobReadResultNdPort
+
+class ReservationStationBundle extends Bundle {
+  val regReadPort = new RegReadNdPort
+  val robResult   = new RobReadResultNdPort
+}
+
+object ReservationStationBundle {
+  val default = (new ReservationStationBundle).Lit(
+    _.regReadPort -> RegReadNdPort.default,
+    _.robResult -> RobReadResultNdPort.default
+  )
+}
diff --git a/src/src/pipeline/execution/ExeStage.scala b/src/src/pipeline/execution/ExeStage.scala
index d47dee1c..958d7f17 100644
--- a/src/src/pipeline/execution/ExeStage.scala
+++ b/src/src/pipeline/execution/ExeStage.scala
@@ -266,15 +266,23 @@ class ExeStage
   )
 
   // branch set
-  io.peer.get.branchSetPort                := alu.io.result.jumpBranchInfo
+  io.peer.get.branchSetPort                := PcSetPort.default
+  io.peer.get.branchSetPort.en             := alu.io.result.jumpBranchInfo.en
+  io.peer.get.branchSetPort.pcAddr         := alu.io.result.jumpBranchInfo.pcAddr
   io.peer.get.scoreboardChangePort.en      := selectedIn.gprWritePort.en
   io.peer.get.scoreboardChangePort.addr    := selectedIn.gprWritePort.addr
   io.peer.get.csrScoreboardChangePort.en   := selectedIn.instInfo.needCsr
   io.peer.get.csrScoreboardChangePort.addr := selectedIn.instInfo.csrWritePort.addr
 
   val isErtn = WireDefault(selectedIn.exeOp === ExeInst.Op.ertn)
-  when(isErtn) {
+  val isIdle = WireDefault(selectedIn.exeOp === ExeInst.Op.idle)
+  when(isIdle) {
+    io.peer.get.branchSetPort.isIdle := true.B
+    io.peer.get.branchSetPort.en     := true.B
+    io.peer.get.branchSetPort.pcAddr := selectedIn.instInfo.pc + 4.U
+  }.elsewhen(isErtn) {
     io.peer.get.branchSetPort.en     := true.B
     io.peer.get.branchSetPort.pcAddr := io.peer.get.csr.era.pc
   }
+
 }
diff --git a/src/src/pipeline/queue/MultiInstQueue.scala b/src/src/pipeline/queue/MultiInstQueue.scala
index 3e83c4f5..cba25b85 100644
--- a/src/src/pipeline/queue/MultiInstQueue.scala
+++ b/src/src/pipeline/queue/MultiInstQueue.scala
@@ -97,15 +97,18 @@ class MultiInstQueue(
       dequeuePort.bits.instInfo.pc   := decodeInstInfo.pcAddr
       dequeuePort.bits.instInfo.inst := decodeInstInfo.inst
       val isMatched = WireDefault(decoderWires(index).map(_.isMatched).reduce(_ || _))
-      dequeuePort.bits.instInfo
-        .exceptionRecords(Csr.ExceptionIndex.ine) := !isMatched
-      dequeuePort.bits.instInfo.isExceptionValid  := !isMatched
       dequeuePort.bits.instInfo.isValid := decodeInstInfo.pcAddr.orR // TODO: Check if it can change to isMatched (see whether commit or not)
-      dequeuePort.bits.instInfo.csrWritePort.en   := selectedDecoder.info.csrWriteEn
-      dequeuePort.bits.instInfo.csrWritePort.addr := selectedDecoder.info.csrAddr
-      dequeuePort.bits.instInfo.exeOp             := selectedDecoder.info.exeOp
-      dequeuePort.bits.instInfo.exeSel            := selectedDecoder.info.exeSel
-      dequeuePort.bits.instInfo.tlbInfo           := selectedDecoder.info.tlbInfo
-      dequeuePort.bits.instInfo.needCsr           := selectedDecoder.info.needCsr
+      dequeuePort.bits.instInfo.csrWritePort.en                           := selectedDecoder.info.csrWriteEn
+      dequeuePort.bits.instInfo.csrWritePort.addr                         := selectedDecoder.info.csrAddr
+      dequeuePort.bits.instInfo.exeOp                                     := selectedDecoder.info.exeOp
+      dequeuePort.bits.instInfo.exeSel                                    := selectedDecoder.info.exeSel
+      dequeuePort.bits.instInfo.tlbInfo                                   := selectedDecoder.info.tlbInfo
+      dequeuePort.bits.instInfo.needCsr                                   := selectedDecoder.info.needCsr
+      dequeuePort.bits.instInfo.exceptionRecords(Csr.ExceptionIndex.adef) := decodeInstInfo.isAdef
+      dequeuePort.bits.instInfo.exceptionRecords(Csr.ExceptionIndex.pif)  := decodeInstInfo.isPif
+      dequeuePort.bits.instInfo.exceptionRecords(Csr.ExceptionIndex.ppi)  := decodeInstInfo.isPpi
+      dequeuePort.bits.instInfo.exceptionRecords(Csr.ExceptionIndex.tlbr) := decodeInstInfo.isTlbr
+      dequeuePort.bits.instInfo.exceptionRecords(Csr.ExceptionIndex.ine)  := !isMatched
+      dequeuePort.bits.instInfo.isExceptionValid := !isMatched || decodeInstInfo.isAdef || decodeInstInfo.isPif || decodeInstInfo.isPpi || decodeInstInfo.isTlbr
   }
 }
diff --git a/src/src/pipeline/queue/decode/Decoder_3R.scala b/src/src/pipeline/queue/decode/Decoder_3R.scala
index 08fd990e..19351a67 100644
--- a/src/src/pipeline/queue/decode/Decoder_3R.scala
+++ b/src/src/pipeline/queue/decode/Decoder_3R.scala
@@ -36,6 +36,12 @@ class Decoder_3R extends Decoder {
   io.out.info.jumpBranchAddr := DontCare
 
   switch(opcode) {
+    is(Inst.idle) {
+      io.out.isMatched := true.B
+      outInfo.gprReadPorts.foreach(_.en := false.B)
+      outInfo.gprWritePort.en := false.B
+      outInfo.exeOp           := ExeInst.Op.idle
+    }
     is(Inst.invtlb) {
       io.out.isMatched               := true.B
       outInfo.exeOp                  := ExeInst.Op.invtlb
diff --git a/src/src/pipeline/rob/bundles/InstWbNdPort.scala b/src/src/pipeline/rob/bundles/InstWbNdPort.scala
index 81c473b8..19dcec11 100644
--- a/src/src/pipeline/rob/bundles/InstWbNdPort.scala
+++ b/src/src/pipeline/rob/bundles/InstWbNdPort.scala
@@ -8,7 +8,7 @@ import common.bundles.RfAccessInfoNdPort
 
 class InstWbNdPort extends Bundle {
   val en    = Bool()
-  val robId = UInt(Width.Rob.id)
+  val robId = UInt(Param.Width.Rob.id)
   val data  = UInt(Width.Reg.data)
 }
 
diff --git a/src/src/pipeline/rob/bundles/RobReadRequestNdPort.scala b/src/src/pipeline/rob/bundles/RobReadRequestNdPort.scala
index b7bb2b00..8902cc7f 100644
--- a/src/src/pipeline/rob/bundles/RobReadRequestNdPort.scala
+++ b/src/src/pipeline/rob/bundles/RobReadRequestNdPort.scala
@@ -5,7 +5,6 @@ import chisel3.experimental.BundleLiterals._
 import chisel3.util._
 import spec._
 import common.bundles.RfAccessInfoNdPort
-import pipeline.rob.bundles.RobReadRequestNdPort
 
 class RobReadRequestNdPort extends Bundle {
   val writeRequest = new RfAccessInfoNdPort
diff --git a/src/src/pipeline/rob/bundles/RobReadResultNdPort.scala b/src/src/pipeline/rob/bundles/RobReadResultNdPort.scala
index 83a80096..01ee7f63 100644
--- a/src/src/pipeline/rob/bundles/RobReadResultNdPort.scala
+++ b/src/src/pipeline/rob/bundles/RobReadResultNdPort.scala
@@ -7,7 +7,7 @@ import spec._
 import common.bundles.RfAccessInfoNdPort
 
 class RobReadResultNdPort extends Bundle {
-  val writeResult = UInt(Width.Rob.id)
+  val writeResult = UInt(Param.Width.Rob.id)
   val readResults = Vec(Param.regFileReadNum, new RobDistributeBundle)
 }
 
diff --git a/src/src/spec/ExeInst.scala b/src/src/spec/ExeInst.scala
index c420bb12..257580f1 100644
--- a/src/src/spec/ExeInst.scala
+++ b/src/src/spec/ExeInst.scala
@@ -61,7 +61,7 @@ object ExeInst {
     val ld_b  = next
     val ld_h  = next
     val ld_w  = next
-    val st_b  = next // 2F
+    val st_b  = next // 1F
     val st_h  = next
     val st_w  = next
     val ld_bu = next
@@ -80,7 +80,8 @@ object ExeInst {
     // exception
     val break_  = next
     val syscall = next
-    val ertn    = next // 3E
+    val ertn    = next // 2E
+    val idle    = next
 
     // stable counter
     val rdcntvl_w = next
diff --git a/src/src/spec/Inst.scala b/src/src/spec/Inst.scala
index 779d3912..0d597880 100644
--- a/src/src/spec/Inst.scala
+++ b/src/src/spec/Inst.scala
@@ -43,6 +43,7 @@ object Inst {
     val srai_w  = i("0000_0000_0100_1000_1")
     val break_  = i("0000_0000_0010_1010_0")
     val syscall = i("0000_0000_0010_1011_0")
+    val idle    = i("0000_0110_0100_1000_1")
   }
 
   object _4R {
diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala
index d5e43323..14d1288e 100644
--- a/src/src/spec/Param.scala
+++ b/src/src/spec/Param.scala
@@ -32,6 +32,12 @@ object Param {
     val exeSel = log2Ceil(ExeInst.Sel.count + 1).W
     val exeOp  = log2Ceil(ExeInst.Op.count + 1).W
 
+    object Rob {
+      val id      = 8.W
+      val _length = 15
+      val addr    = log2Ceil(_length).W
+    }
+
     object Axi {
       private val _data = 32
 
diff --git a/src/src/spec/package.scala b/src/src/spec/package.scala
index 16ebf89f..8db219d1 100644
--- a/src/src/spec/package.scala
+++ b/src/src/spec/package.scala
@@ -52,10 +52,6 @@ package object spec {
       val asid           = 10.W
     }
 
-    object Rob {
-      val id = 8.W
-    }
-
     object Op {
       val _2RI12 = 10.W
       val _2RI14 = 8.W
diff --git a/src/src/utils/MultiCounter.scala b/src/src/utils/MultiCounter.scala
index 4c408e0e..80700fee 100644
--- a/src/src/utils/MultiCounter.scala
+++ b/src/src/utils/MultiCounter.scala
@@ -18,11 +18,11 @@ class MultiCounter(
     // one clock delay
     val value = Output(UInt(value_w.W))
     // no delay
-    val incResults = Output(Vec(maxIncNum + 1, UInt(value_w.W)))
+    val incResults = Output(Vec(maxCount + 1, UInt(value_w.W)))
   })
 
   val counter    = RegInit(init.U(value_w.W))
-  val incResults = Wire(Vec(maxIncNum + 1, UInt(value_w.W)))
+  val incResults = Wire(Vec(maxCount + 1, UInt(value_w.W)))
   io.value := counter
   io.incResults.zip(incResults).foreach {
     case (dst, src) =>