diff --git a/src/src/CoreCpuTop.scala b/src/src/CoreCpuTop.scala
index 1167d6e5..4bc759c1 100644
--- a/src/src/CoreCpuTop.scala
+++ b/src/src/CoreCpuTop.scala
@@ -96,12 +96,11 @@ class CoreCpuTop extends Module {
       else None
   })
 
-  val iCache         = Module(new ICache)
-  val frontend       = Module(new Frontend)
-  val instQueue      = Module(new MultiInstQueue)
-  val issueStage     = Module(new IssueStage)
-  val exeForMemStage = Module(new ExeForMemStage)
-  // val exePassWbStages = Seq.fill(Param.exePassWbNum)(Module(new ExePassWbStage))
+  val iCache           = Module(new ICache)
+  val frontend         = Module(new Frontend)
+  val instQueue        = Module(new MultiInstQueue)
+  val issueStage       = Module(new IssueStage)
+  val exeForMemStage   = Module(new ExeForMemStage)
   val exePassWbStage_1 = Module(new ExePassWbStage(supportBranchCsr = true))
   val exePassWbStage_2 = Module(new ExePassWbStage(supportBranchCsr = false))
   val exePassWbStages  = Seq(exePassWbStage_1, exePassWbStage_2)
@@ -116,7 +115,7 @@ class CoreCpuTop extends Module {
   val memReqStage    = Module(new MemReqStage)
   val memResStage    = Module(new MemResStage)
 
-  // pass through
+  // Passthrough
   memReqStage.io.out.ready := true.B
   exePassWbStages.foreach(_.io.out.ready := true.B)
 
@@ -124,8 +123,6 @@ class CoreCpuTop extends Module {
 
   val csrScoreBoard = Module(new CsrScoreboard)
 
-  // val dataforward = Module(new DataForwardStage)
-
   val regFile = Module(new RegFile)
   val pc      = Module(new Pc)
 
@@ -136,7 +133,7 @@ class CoreCpuTop extends Module {
   // AXI top <> AXI crossbar
   crossbar.io.master(0) <> io.axi
 
-  // `ICache` <> AXI crossbar
+  // ICache <> AXI crossbar
   crossbar.io.slave(0) <> iCache.io.axiMasterPort
 
   // Memory related modules
@@ -196,30 +193,11 @@ class CoreCpuTop extends Module {
     case (dst, src) =>
       dst := src
   }
-  // issueStage.io.peer.get.robInstValids.zip(rob.io.robInstValids).foreach {
-  //   case (dst, src) =>
-  //     dst := src
-  // }
-
-  // def connect_wb(dst: InstWbNdPort, src: DecoupledIO[WbNdPort]): Unit = {
-  //   dst.en    := src.valid
-  //   dst.data  := src.bits.gprWrite.data
-  //   dst.robId := src.bits.instInfo.robId
-  // }
-  // issueStage.io.peer.get.writebacks.zipWithIndex.foreach {
-  //   case (dst, idx) =>
-  //     assert(Param.loadStoreIssuePipelineIndex == 0, "if load store no issue in line 0, please change if-else below")
-  //     if (idx == Param.loadStoreIssuePipelineIndex) {
-  //       connect_wb(dst, memResStage.io.out)
-  //     } else {
-  //       connect_wb(dst, exePassWbStages(idx - 1).io.out)
-  //     }
-  // }
   issueStage.io.peer.get.writebacks.zip(rob.io.instWbBroadCasts).foreach {
     case (dst, src) =>
       dst := src
   }
-  issueStage.io.peer.get.csrRegScore := csrScoreBoard.io.regScore
+  issueStage.io.peer.get.csrcore     := csrScoreBoard.io.regScore
   issueStage.io.peer.get.csrReadPort <> csr.io.readPorts(0)
 
   // Scoreboards
@@ -289,9 +267,8 @@ class CoreCpuTop extends Module {
     case (dst, src) =>
       dst <> src
   }
-  commitStage.io.csrValues := csr.io.csrValues
 
-  // regfile
+  // Reg file
   regFile.io.writePorts <> cu.io.gprWritePassThroughPorts.out
   regFile.io.readPorts.zip(rob.io.regReadPortss).foreach {
     case (rfReads, robReads) =>
@@ -301,7 +278,7 @@ class CoreCpuTop extends Module {
       }
   }
 
-  // Ctrl unit
+  // Control unit
   cu.io.instInfoPorts.zip(commitStage.io.cuInstInfoPorts).foreach {
     case (dst, src) => dst := src
   }
@@ -310,10 +287,6 @@ class CoreCpuTop extends Module {
   }
   cu.io.csrValues             := csr.io.csrValues
   cu.io.stableCounterReadPort <> stableCounter.io
-  // cu.io.robInstValids.zip(rob.io.robInstValids).foreach {
-  //   case (dst, src) =>
-  //     dst := src
-  // }
 
   require(Param.jumpBranchPipelineIndex != 0)
   cu.io.branchExe    := exePassWbStages(Param.jumpBranchPipelineIndex - 1).io.peer.get.branchSetPort.get
@@ -322,12 +295,11 @@ class CoreCpuTop extends Module {
   cu.io.hardWareInetrrupt := io.intrpt
 
   // After memory request flush connection
-  // memReqStage.io.peer.get.isAfterMemReqFlush := cu.io.isAfterMemReqFlush
   cu.io.isExceptionValidVec(0) := false.B // memReqStage.io.peer.get.isExceptionValid
   cu.io.isExceptionValidVec(1) := false.B // memResStage.io.peer.get.isExceptionValid
   cu.io.isExceptionValidVec(2) := commitStage.io.isExceptionValid
 
-  // Csr
+  // CSR
   csr.io.writePorts.zip(cu.io.csrWritePorts).foreach {
     case (dst, src) =>
       dst := src
diff --git a/src/src/control/Csr.scala b/src/src/control/Csr.scala
index 6235a5f8..711e268a 100644
--- a/src/src/control/Csr.scala
+++ b/src/src/control/Csr.scala
@@ -3,12 +3,12 @@ package control
 import chisel3._
 import chisel3.util._
 import control.bundles._
-import control.csrRegsBundles._
+import control.csrBundles._
 import spec._
 
 class Csr(
-  writeNum: Int = Param.csrRegsWriteNum,
-  readNum:  Int = Param.csrRegsReadNum)
+  writeNum: Int = Param.csrWriteNum,
+  readNum:  Int = Param.csrReadNum)
     extends Module {
   val io = IO(new Bundle {
     // `Cu` -> `Csr`
@@ -16,7 +16,7 @@ class Csr(
     val csrMessage = Input(new CuToCsrNdPort)
     val csrValues  = Output(new CsrValuePort)
     // `Csr` <-> `RegReadStage`
-    val readPorts = Vec(Param.csrRegsReadNum, new CsrReadPort)
+    val readPorts = Vec(Param.csrReadNum, new CsrReadPort)
     // `Csr` -> `WbStage`
     val hasInterrupt = Output(Bool())
   })
@@ -35,98 +35,98 @@ class Csr(
     passPort
   }
 
-  val csrRegs = RegInit(VecInit(Seq.fill(Count.csrReg)(zeroWord)))
+  val csr = RegInit(VecInit(Seq.fill(Count.csrReg)(zeroWord)))
 
   // CRMD 当前模式信息
 
-  val crmd = viewUInt(csrRegs(spec.Csr.Index.crmd), new CrmdBundle)
+  val crmd = viewUInt(csr(spec.Csr.Index.crmd), new CrmdBundle)
 
   // PRMD 例外前模式信息
-  val prmd = viewUInt(csrRegs(spec.Csr.Index.prmd), new PrmdBundle)
+  val prmd = viewUInt(csr(spec.Csr.Index.prmd), new PrmdBundle)
 
   // EUEN扩展部件使能
-  val euen = viewUInt(csrRegs(spec.Csr.Index.euen), new EuenBundle)
+  val euen = viewUInt(csr(spec.Csr.Index.euen), new EuenBundle)
 
   // ECFG 例外控制
-  val ecfg = viewUInt(csrRegs(spec.Csr.Index.ecfg), new EcfgBundle)
+  val ecfg = viewUInt(csr(spec.Csr.Index.ecfg), new EcfgBundle)
 
   // ESTAT
-  val estat = viewUInt(csrRegs(spec.Csr.Index.estat), new EstatBundle)
+  val estat = viewUInt(csr(spec.Csr.Index.estat), new EstatBundle)
 
   // ERA 例外返回地址: 触发例外指令的pc记录在此
-  val era = viewUInt(csrRegs(spec.Csr.Index.era), new EraBundle)
+  val era = viewUInt(csr(spec.Csr.Index.era), new EraBundle)
 
   // BADV 出错虚地址
-  val badv = viewUInt(csrRegs(spec.Csr.Index.badv), new BadvBundle)
+  val badv = viewUInt(csr(spec.Csr.Index.badv), new BadvBundle)
 
   // EENTRY 例外入口地址
-  val eentry = viewUInt(csrRegs(spec.Csr.Index.eentry), new EentryBundle)
+  val eentry = viewUInt(csr(spec.Csr.Index.eentry), new EentryBundle)
 
   // CPUID 处理器编号
-  val cpuid = viewUInt(csrRegs(spec.Csr.Index.cpuid), new CpuidBundle)
+  val cpuid = viewUInt(csr(spec.Csr.Index.cpuid), new CpuidBundle)
 
   // SAVE0-3 数据保存
   val saves = VecInit(spec.Csr.Index.save0, spec.Csr.Index.save1, spec.Csr.Index.save2, spec.Csr.Index.save3).map {
     idx =>
-      viewUInt(csrRegs(idx), new CsrSaveBundle)
+      viewUInt(csr(idx), new CsrSaveBundle)
   }
 
   // LLBCTL  LLBit控制
-  val llbctl = viewUInt(csrRegs(spec.Csr.Index.llbctl), new LlbctlBundle)
+  val llbctl = viewUInt(csr(spec.Csr.Index.llbctl), new LlbctlBundle)
 
   // TLBIDX  TLB索引
-  val tlbidx = viewUInt(csrRegs(spec.Csr.Index.tlbidx), new TlbidxBundle)
+  val tlbidx = viewUInt(csr(spec.Csr.Index.tlbidx), new TlbidxBundle)
 
   // TLBEHI  TLB表项高位
-  val tlbehi = viewUInt(csrRegs(spec.Csr.Index.tlbehi), new TlbehiBundle)
+  val tlbehi = viewUInt(csr(spec.Csr.Index.tlbehi), new TlbehiBundle)
 
   // TLBELO 0-1  TLB表项低位
-  val tlbelo0 = viewUInt(csrRegs(spec.Csr.Index.tlbelo0), new TlbeloBundle)
+  val tlbelo0 = viewUInt(csr(spec.Csr.Index.tlbelo0), new TlbeloBundle)
 
-  val tlbelo1 = viewUInt(csrRegs(spec.Csr.Index.tlbelo1), new TlbeloBundle)
+  val tlbelo1 = viewUInt(csr(spec.Csr.Index.tlbelo1), new TlbeloBundle)
 
   // ASID 地址空间标识符
-  val asid = viewUInt(csrRegs(spec.Csr.Index.asid), new AsidBundle)
+  val asid = viewUInt(csr(spec.Csr.Index.asid), new AsidBundle)
 
   // PGDL 低半地址空间全局目录基址
-  val pgdl = viewUInt(csrRegs(spec.Csr.Index.pgdl), new PgdlBundle)
+  val pgdl = viewUInt(csr(spec.Csr.Index.pgdl), new PgdlBundle)
 
   // PGDH 高半地址空间全局目录基址
-  val pgdh = viewUInt(csrRegs(spec.Csr.Index.pgdh), new PgdhBundle)
+  val pgdh = viewUInt(csr(spec.Csr.Index.pgdh), new PgdhBundle)
 
   // PGD 全局地址空间全局目录基址
-  val pgd = viewUInt(csrRegs(spec.Csr.Index.pgd), new PgdBundle)
+  val pgd = viewUInt(csr(spec.Csr.Index.pgd), new PgdBundle)
 
   // TLBRENTRY  TLB重填例外入口地址
-  val tlbrentry = viewUInt(csrRegs(spec.Csr.Index.tlbrentry), new TlbrentryBundle)
+  val tlbrentry = viewUInt(csr(spec.Csr.Index.tlbrentry), new TlbrentryBundle)
 
   // DMW 0-1 直接映射配置窗口
-  val dmw0 = viewUInt(csrRegs(spec.Csr.Index.dmw0), new DmwBundle)
+  val dmw0 = viewUInt(csr(spec.Csr.Index.dmw0), new DmwBundle)
 
-  val dmw1 = viewUInt(csrRegs(spec.Csr.Index.dmw1), new DmwBundle)
+  val dmw1 = viewUInt(csr(spec.Csr.Index.dmw1), new DmwBundle)
 
   // TID 定时器编号
-  val tid = viewUInt(csrRegs(spec.Csr.Index.tid), new TidBundle)
+  val tid = viewUInt(csr(spec.Csr.Index.tid), new TidBundle)
 
   // TCFG 定时器配置
-  val tcfg = viewUInt(csrRegs(spec.Csr.Index.tcfg), new TcfgBundle)
+  val tcfg = viewUInt(csr(spec.Csr.Index.tcfg), new TcfgBundle)
 
   // TVAL 定时器数值
-  val tval = viewUInt(csrRegs(spec.Csr.Index.tval), new TvalBundle)
+  val tval = viewUInt(csr(spec.Csr.Index.tval), new TvalBundle)
 
   // TICLR 定时器中断清除
-  val ticlr = viewUInt(csrRegs(spec.Csr.Index.ticlr), new TiclrBundle)
+  val ticlr = viewUInt(csr(spec.Csr.Index.ticlr), new TiclrBundle)
 
   // read
   io.readPorts.foreach { readPort =>
     readPort.data := zeroWord
     when(readPort.en) {
-      readPort.data := csrRegs(readPort.addr)
+      readPort.data := csr(readPort.addr)
       when(readPort.addr === spec.Csr.Index.pgd) {
         readPort.data := Mux(
           badv.out.vaddr(31),
-          csrRegs(spec.Csr.Index.pgdh),
-          csrRegs(spec.Csr.Index.pgdl)
+          csr(spec.Csr.Index.pgdh),
+          csr(spec.Csr.Index.pgdl)
         )
       }
     }
@@ -147,7 +147,7 @@ class Csr(
     }
   }
 
-  // 软件写csrRegs
+  // 软件写csr
   // 保留域断断续续的样子真是可爱捏
   io.writePorts.foreach { writePort =>
     when(writePort.en) {
diff --git a/src/src/control/Cu.scala b/src/src/control/Cu.scala
index ae9d9e56..bf210280 100644
--- a/src/src/control/Cu.scala
+++ b/src/src/control/Cu.scala
@@ -11,9 +11,8 @@ import spec.{Csr, ExeInst, Param}
 
 // Note. Exception只从第0个提交
 class Cu(
-  ctrlControlNum: Int = Param.ctrlControlNum,
-  writeNum:       Int = Param.csrRegsWriteNum,
-  commitNum:      Int = Param.commitNum)
+  writeNum:  Int = Param.csrWriteNum,
+  commitNum: Int = Param.commitNum)
     extends Module {
   val io = IO(new Bundle {
 
@@ -48,9 +47,6 @@ class Cu(
     // -> `MemReqStage`
     val isAfterMemReqFlush = Output(Bool())
 
-    // <- `Rob`
-    // val robInstValids = Input(Vec(Param.Width.Rob._length, Bool()))
-
     // <- Out
     val hardWareInetrrupt = Input(UInt(8.W))
 
@@ -67,10 +63,6 @@ class Cu(
   io.csrMessage := CuToCsrNdPort.default
   io.newPc      := PcSetPort.default
 
-  // val linesHasException = WireDefault(VecInit(io.instInfoPorts.map { instInfo =>
-  //   (instInfo.exceptionPos =/= ExceptionPos.none) && instInfo.isValid
-  // }))
-  // val hasException = WireDefault(linesHasException.reduce(_ || _))
   val hasException = WireDefault(io.instInfoPorts(0).exceptionPos =/= ExceptionPos.none) && io.instInfoPorts(0).isValid
 
   /** stable counter
@@ -109,8 +101,6 @@ class Cu(
   io.csrMessage.exceptionFlush := hasException
   // Attention: 由于encoder在全零的情况下会选择idx最高的那个，
   // 使用时仍需判断是否有exception
-  // val selectLineNum      = PriorityEncoder(linesHasException)
-  // val selectInstInfo     = WireDefault(io.instInfoPorts(selectLineNum))
   val selectInstInfo     = WireDefault(io.instInfoPorts(0))
   val selectException    = WireDefault(selectInstInfo.exceptionRecord)
   val selectExceptionPos = WireDefault(selectInstInfo.exceptionPos)
@@ -212,8 +202,6 @@ class Cu(
   /** Flush & jump
     */
 
-  val exceptionFlush = WireDefault(hasException)
-
   val ertnFlush = WireDefault(
     io.instInfoPorts.map { instInfo => instInfo.exeOp === ExeInst.Op.ertn && instInfo.isValid }.reduce(_ || _)
   )
@@ -221,16 +209,12 @@ class Cu(
   // Handle after memory request exception valid
   io.isAfterMemReqFlush := io.isExceptionValidVec.asUInt.orR
 
-  // io.exceptionFlush := RegNext(exceptionFlush, false.B)
-  // val branchSetEnable = WireDefault(io.jumpPc.en && io.robInstValids(io.jumpPc.robId))
-  // io.branchFlushInfo.en    := RegNext(branchSetEnable)
-  // io.branchFlushInfo.robId := RegNext(io.jumpPc.robId)
   io.csrMessage.ertnFlush := ertnFlush
-  io.frontendFlush        := RegNext(exceptionFlush || io.branchExe.en, false.B)
-  io.backendFlush         := RegNext(exceptionFlush || io.branchCommit, false.B)
+  io.frontendFlush        := RegNext(hasException || io.branchExe.en, false.B)
+  io.backendFlush         := RegNext(hasException || io.branchCommit, false.B)
 
   // select new pc
-  when(exceptionFlush) {
+  when(hasException) {
     io.newPc.en     := true.B
     io.newPc.isIdle := false.B
     when(isTlbRefillException) {
@@ -248,12 +232,9 @@ class Cu(
     io.instInfoPorts(0).csrWritePort.data(1, 0).orR
 
   io.difftest match {
-    case Some(dt) => {
-      dt.cmt_ertn := RegNext(ertnFlush)
-      dt.cmt_excp_flush := RegNext(
-        exceptionFlush
-      )
-    }
+    case Some(dt) =>
+      dt.cmt_ertn       := RegNext(ertnFlush)
+      dt.cmt_excp_flush := RegNext(hasException)
     case _ =>
   }
 }
diff --git a/src/src/control/bundles/CsrValuePort.scala b/src/src/control/bundles/CsrValuePort.scala
index 04c370d2..24fad6fb 100644
--- a/src/src/control/bundles/CsrValuePort.scala
+++ b/src/src/control/bundles/CsrValuePort.scala
@@ -1,7 +1,7 @@
 package control.bundles
 
 import chisel3._
-import control.csrRegsBundles._
+import control.csrBundles._
 
 class CsrValuePort extends Bundle {
   val crmd      = new CrmdBundle
diff --git a/src/src/control/csrRegsBundles/AsidBundle.scala b/src/src/control/csrRegsBundles/AsidBundle.scala
index d406a5ef..c17799e1 100644
--- a/src/src/control/csrRegsBundles/AsidBundle.scala
+++ b/src/src/control/csrRegsBundles/AsidBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/BadvBundle.scala b/src/src/control/csrRegsBundles/BadvBundle.scala
index dc2b26ac..fc17b1ad 100644
--- a/src/src/control/csrRegsBundles/BadvBundle.scala
+++ b/src/src/control/csrRegsBundles/BadvBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/CpuidBundle.scala b/src/src/control/csrRegsBundles/CpuidBundle.scala
index d5532089..acd1d1ac 100644
--- a/src/src/control/csrRegsBundles/CpuidBundle.scala
+++ b/src/src/control/csrRegsBundles/CpuidBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/CrmdBundle.scala b/src/src/control/csrRegsBundles/CrmdBundle.scala
index 45f27791..791235b2 100644
--- a/src/src/control/csrRegsBundles/CrmdBundle.scala
+++ b/src/src/control/csrRegsBundles/CrmdBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import chisel3.experimental.BundleLiterals._
diff --git a/src/src/control/csrRegsBundles/CsrSaveBundle.scala b/src/src/control/csrRegsBundles/CsrSaveBundle.scala
index c5f928f0..7ffb4e67 100644
--- a/src/src/control/csrRegsBundles/CsrSaveBundle.scala
+++ b/src/src/control/csrRegsBundles/CsrSaveBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/DmwBundle.scala b/src/src/control/csrRegsBundles/DmwBundle.scala
index 268d352d..6ba37600 100644
--- a/src/src/control/csrRegsBundles/DmwBundle.scala
+++ b/src/src/control/csrRegsBundles/DmwBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/EcfgBundle.scala b/src/src/control/csrRegsBundles/EcfgBundle.scala
index b4c0a090..3fb0eab4 100644
--- a/src/src/control/csrRegsBundles/EcfgBundle.scala
+++ b/src/src/control/csrRegsBundles/EcfgBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/EentryBundle.scala b/src/src/control/csrRegsBundles/EentryBundle.scala
index 159e503c..51164bda 100644
--- a/src/src/control/csrRegsBundles/EentryBundle.scala
+++ b/src/src/control/csrRegsBundles/EentryBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/EraBundle.scala b/src/src/control/csrRegsBundles/EraBundle.scala
index 4066aaf7..611394ac 100644
--- a/src/src/control/csrRegsBundles/EraBundle.scala
+++ b/src/src/control/csrRegsBundles/EraBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/EstatBundle.scala b/src/src/control/csrRegsBundles/EstatBundle.scala
index c10b3647..abd3524c 100644
--- a/src/src/control/csrRegsBundles/EstatBundle.scala
+++ b/src/src/control/csrRegsBundles/EstatBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/EuenBundle.scala b/src/src/control/csrRegsBundles/EuenBundle.scala
index 815ef7a8..1d039569 100644
--- a/src/src/control/csrRegsBundles/EuenBundle.scala
+++ b/src/src/control/csrRegsBundles/EuenBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/LlbctlBundle.scala b/src/src/control/csrRegsBundles/LlbctlBundle.scala
index 3d5f4830..5807ba20 100644
--- a/src/src/control/csrRegsBundles/LlbctlBundle.scala
+++ b/src/src/control/csrRegsBundles/LlbctlBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/PgdBundle.scala b/src/src/control/csrRegsBundles/PgdBundle.scala
index 2d3953da..f5aae69d 100644
--- a/src/src/control/csrRegsBundles/PgdBundle.scala
+++ b/src/src/control/csrRegsBundles/PgdBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/PgdhBundle.scala b/src/src/control/csrRegsBundles/PgdhBundle.scala
index 6eaa43cd..6a6d9500 100644
--- a/src/src/control/csrRegsBundles/PgdhBundle.scala
+++ b/src/src/control/csrRegsBundles/PgdhBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/PgdlBundle.scala b/src/src/control/csrRegsBundles/PgdlBundle.scala
index cd6556ec..cc3fc47a 100644
--- a/src/src/control/csrRegsBundles/PgdlBundle.scala
+++ b/src/src/control/csrRegsBundles/PgdlBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/PrmdBundle.scala b/src/src/control/csrRegsBundles/PrmdBundle.scala
index 55605862..6f604ec0 100644
--- a/src/src/control/csrRegsBundles/PrmdBundle.scala
+++ b/src/src/control/csrRegsBundles/PrmdBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/TcfgBundle.scala b/src/src/control/csrRegsBundles/TcfgBundle.scala
index 3183eef0..9f8f92ba 100644
--- a/src/src/control/csrRegsBundles/TcfgBundle.scala
+++ b/src/src/control/csrRegsBundles/TcfgBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/TiclrBundle.scala b/src/src/control/csrRegsBundles/TiclrBundle.scala
index 331ae8d7..7aef9821 100644
--- a/src/src/control/csrRegsBundles/TiclrBundle.scala
+++ b/src/src/control/csrRegsBundles/TiclrBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/TidBundle.scala b/src/src/control/csrRegsBundles/TidBundle.scala
index b8512400..52147b0f 100644
--- a/src/src/control/csrRegsBundles/TidBundle.scala
+++ b/src/src/control/csrRegsBundles/TidBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/TlbehiBundle.scala b/src/src/control/csrRegsBundles/TlbehiBundle.scala
index cc3a06f2..2c162f8e 100644
--- a/src/src/control/csrRegsBundles/TlbehiBundle.scala
+++ b/src/src/control/csrRegsBundles/TlbehiBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/TlbeloBundle.scala b/src/src/control/csrRegsBundles/TlbeloBundle.scala
index 4b2a3e6a..854facc4 100644
--- a/src/src/control/csrRegsBundles/TlbeloBundle.scala
+++ b/src/src/control/csrRegsBundles/TlbeloBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/TlbidxBundle.scala b/src/src/control/csrRegsBundles/TlbidxBundle.scala
index 02c0ff0c..1f0a0f12 100644
--- a/src/src/control/csrRegsBundles/TlbidxBundle.scala
+++ b/src/src/control/csrRegsBundles/TlbidxBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/control/csrRegsBundles/TlbrentryBundle.scala b/src/src/control/csrRegsBundles/TlbrentryBundle.scala
index 441d594f..860a09dd 100644
--- a/src/src/control/csrRegsBundles/TlbrentryBundle.scala
+++ b/src/src/control/csrRegsBundles/TlbrentryBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 
diff --git a/src/src/control/csrRegsBundles/TvalBundle.scala b/src/src/control/csrRegsBundles/TvalBundle.scala
index 57b88688..d0239562 100644
--- a/src/src/control/csrRegsBundles/TvalBundle.scala
+++ b/src/src/control/csrRegsBundles/TvalBundle.scala
@@ -1,4 +1,4 @@
-package control.csrRegsBundles
+package control.csrBundles
 
 import chisel3._
 import spec._
diff --git a/src/src/memory/Tlb.scala b/src/src/memory/Tlb.scala
index 1abdefdb..54b3d1a4 100644
--- a/src/src/memory/Tlb.scala
+++ b/src/src/memory/Tlb.scala
@@ -2,7 +2,7 @@ package memory
 
 import chisel3._
 import chisel3.util._
-import control.csrRegsBundles.{AsidBundle, TlbehiBundle, TlbeloBundle, TlbidxBundle}
+import control.csrBundles.{AsidBundle, TlbehiBundle, TlbeloBundle, TlbidxBundle}
 import memory.bundles._
 import memory.enums.TlbMemType
 import spec.ExeInst.Op.Tlb._
diff --git a/src/src/memory/bundles/TlbCsrWriteNdPort.scala b/src/src/memory/bundles/TlbCsrWriteNdPort.scala
index 90d9bafb..d144e6da 100644
--- a/src/src/memory/bundles/TlbCsrWriteNdPort.scala
+++ b/src/src/memory/bundles/TlbCsrWriteNdPort.scala
@@ -2,7 +2,7 @@ package memory.bundles
 
 import chisel3._
 import chisel3.util._
-import control.csrRegsBundles.{AsidBundle, TlbehiBundle, TlbeloBundle, TlbidxBundle}
+import control.csrBundles.{AsidBundle, TlbehiBundle, TlbeloBundle, TlbidxBundle}
 
 class TlbCsrWriteNdPort extends Bundle {
   val tlbidx    = Valid(new TlbidxBundle)
diff --git a/src/src/pipeline/commit/CommitStage.scala b/src/src/pipeline/commit/CommitStage.scala
index 14eab8e4..a8b44494 100644
--- a/src/src/pipeline/commit/CommitStage.scala
+++ b/src/src/pipeline/commit/CommitStage.scala
@@ -40,8 +40,6 @@ class CommitStage(
     // `CommitStage` -> `Cu` NO delay
     val isExceptionValid = Output(Bool())
 
-    val csrValues = Input(new CsrValuePort)
-
     val difftest =
       if (isDiffTest)
         Some(Output(new Bundle {
diff --git a/src/src/pipeline/dispatch/BiIssueStage.scala b/src/src/pipeline/dispatch/BiIssueStage.scala
index 5d274bab..7e60ce8e 100644
--- a/src/src/pipeline/dispatch/BiIssueStage.scala
+++ b/src/src/pipeline/dispatch/BiIssueStage.scala
@@ -41,7 +41,7 @@ class BiIssueStagePeerPort(
 
   // `IssueStage` <-> `Scoreboard(csr)`
   val csrOccupyPort = Output(new ScoreboardChangeNdPort)
-  val csrRegScore   = Input(ScoreboardState())
+  val csrcore       = Input(ScoreboardState())
 }
 
 // TODO: deal WAR / WAW data hazard
@@ -103,7 +103,7 @@ class BiIssueStage(
         !(
           // csr only issue in one pipeline
           if (idx == csrIssuePipelineIndex) {
-            in.instInfo.needCsr && (io.peer.get.csrRegScore =/= ScoreboardState.free)
+            in.instInfo.needCsr && (io.peer.get.csrcore =/= ScoreboardState.free)
           } else {
             in.instInfo.needCsr
           }
diff --git a/src/src/pipeline/dispatch/IssueStage.scala b/src/src/pipeline/dispatch/IssueStage.scala
index 590dd6c8..672f6bec 100644
--- a/src/src/pipeline/dispatch/IssueStage.scala
+++ b/src/src/pipeline/dispatch/IssueStage.scala
@@ -39,7 +39,7 @@ class IssueStagePeerPort(
 
   // `IssueStage` <-> `Scoreboard(csr)`
   val csrOccupyPort = Output(new ScoreboardChangeNdPort)
-  val csrRegScore   = Input(ScoreboardState())
+  val csrcore       = Input(ScoreboardState())
   val csrReadPort   = Flipped(new CsrReadPort)
 
   // branch flush
@@ -138,7 +138,7 @@ class IssueStage(
               }
             }
             if (dst_idx == csrIssuePipelineIndex) {
-              when(in.instInfo.needCsr && (io.peer.get.csrRegScore =/= ScoreboardState.free)) {
+              when(in.instInfo.needCsr && (io.peer.get.csrcore =/= ScoreboardState.free)) {
                 dispatchEn := false.B
               }
             } else {
diff --git a/src/src/pipeline/dispatch/RegReadStage.scala b/src/src/pipeline/dispatch/RegReadStage.scala
index ada3381b..e0d0174e 100644
--- a/src/src/pipeline/dispatch/RegReadStage.scala
+++ b/src/src/pipeline/dispatch/RegReadStage.scala
@@ -22,24 +22,24 @@ object RegReadNdPort {
   )
 }
 
-class RegReadPeerPort(readNum: Int, csrRegsReadNum: Int) extends Bundle {
+class RegReadPeerPort(readNum: Int, csrReadNum: Int) extends Bundle {
   // `RegReadStage` <-> `Regfile`
   val gprReadPorts = Vec(readNum, Flipped(new RfReadPort))
 
   // `RegReadStage <-> `Csr`
-  val csrReadPorts = Vec(csrRegsReadNum, Flipped(new CsrReadPort))
+  val csrReadPorts = Vec(csrReadNum, Flipped(new CsrReadPort))
 
 }
 
-class RegReadStage(readNum: Int = Param.instRegReadNum, csrRegsReadNum: Int = Param.csrRegsReadNum)
+class RegReadStage(readNum: Int = Param.instRegReadNum, csrReadNum: Int = Param.csrReadNum)
     extends BaseStage(
       new RegReadNdPort,
       new ExeNdPort,
       RegReadNdPort.default,
-      Some(new RegReadPeerPort(readNum, csrRegsReadNum))
+      Some(new RegReadPeerPort(readNum, csrReadNum))
     ) {
 
-  require(csrRegsReadNum == 1)
+  require(csrReadNum == 1)
 
   // Read from GPR
   selectedIn.preExeInstInfo.gprReadPorts.zip(io.peer.get.gprReadPorts).foreach {
diff --git a/src/src/pipeline/execution/ExeForMemStage.scala b/src/src/pipeline/execution/ExeForMemStage.scala
index 4d55e070..89faeabc 100644
--- a/src/src/pipeline/execution/ExeForMemStage.scala
+++ b/src/src/pipeline/execution/ExeForMemStage.scala
@@ -3,7 +3,7 @@ package pipeline.execution
 import chisel3._
 import chisel3.util._
 import common.enums.ReadWriteSel
-import control.csrRegsBundles.{EraBundle, LlbctlBundle}
+import control.csrBundles.{EraBundle, LlbctlBundle}
 import control.enums.ExceptionPos
 import pipeline.common.BaseStage
 import pipeline.dispatch.bundles.ScoreboardChangeNdPort
@@ -34,15 +34,8 @@ class ExeForMemStage
   resultOutReg.bits.instInfo := selectedIn.instInfo
 
   // write-back information fallback
-  // resultOutReg.bits.gprWrite.en   := false.B
-  // resultOutReg.bits.gprWrite.addr := zeroWord
-  // resultOutReg.bits.gprWrite.data := zeroWord
   resultOutReg.bits.gprAddr := selectedIn.gprWritePort.addr
 
-  // // write-back information selection
-  // resultOutReg.bits.gprWrite.en   := selectedIn.gprWritePort.en
-  // resultOutReg.bits.gprWrite.addr := selectedIn.gprWritePort.addr
-
   // 指令未对齐
   val isAle = WireDefault(false.B)
   resultOutReg.bits.instInfo.exceptionPos := selectedIn.instInfo.exceptionPos
@@ -63,11 +56,6 @@ class ExeForMemStage
     }
   }
 
-  // when(selectedIn.instInfo.pc(1, 0).orR) {
-  //   resultOutReg.bits.instInfo.isExceptionValid                          := true.B
-  //   resultOutReg.bits.instInfo.exceptionRecords(Csr.ExceptionIndex.adef) := true.B
-  // }
-
   /** MemAccess
     */
 
@@ -167,5 +155,4 @@ class ExeForMemStage
 
   io.peer.get.csrScoreboardChangePort.en   := selectedIn.instInfo.needCsr
   io.peer.get.csrScoreboardChangePort.addr := selectedIn.instInfo.csrWritePort.addr
-
 }
diff --git a/src/src/pipeline/execution/ExePassWbStage.scala b/src/src/pipeline/execution/ExePassWbStage.scala
index c8b8eb77..eb8250b8 100644
--- a/src/src/pipeline/execution/ExePassWbStage.scala
+++ b/src/src/pipeline/execution/ExePassWbStage.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.BundleLiterals._
 import chisel3.util._
 import common.bundles.{PcSetPort, RfAccessInfoNdPort}
-import control.csrRegsBundles.{EraBundle, LlbctlBundle}
+import control.csrBundles.{EraBundle, LlbctlBundle}
 import control.enums.ExceptionPos
 import pipeline.commit.WbNdPort
 import pipeline.commit.bundles.InstInfoNdPort
diff --git a/src/src/pipeline/mem/bundles/MemCsrNdPort.scala b/src/src/pipeline/mem/bundles/MemCsrNdPort.scala
index e4f10c84..47800b29 100644
--- a/src/src/pipeline/mem/bundles/MemCsrNdPort.scala
+++ b/src/src/pipeline/mem/bundles/MemCsrNdPort.scala
@@ -1,7 +1,7 @@
 package pipeline.mem.bundles
 
 import chisel3._
-import control.csrRegsBundles.{CrmdBundle, DmwBundle}
+import control.csrBundles.{CrmdBundle, DmwBundle}
 
 class MemCsrNdPort extends Bundle {
   val crmd = new CrmdBundle
diff --git a/src/src/pipeline/rob/Rob.scala b/src/src/pipeline/rob/Rob.scala
index 09216808..72969f65 100644
--- a/src/src/pipeline/rob/Rob.scala
+++ b/src/src/pipeline/rob/Rob.scala
@@ -80,10 +80,6 @@ class Rob(
   queue.io.dequeuePorts.foreach(_.ready := false.B)
   queue.io.isFlush := io.isFlush
   io.emptyNum      := queue.io.emptyNum
-  // io.robInstValids.lazyZip(queue.io.elems).lazyZip(queue.io.elemValids).lazyZip(queue.io.setPorts).foreach {
-  //   case (dst, elem, elemValid, set) =>
-  //     dst := elemValid && elem.isValid && (!set.valid || set.bits.isValid)
-  // }
   io.instWbBroadCasts.zip(io.finishInsts).foreach {
     case (dst, src) =>
       dst.en    := src.valid // && io.robInstValids(src.bits.instInfo.robId)
@@ -163,15 +159,13 @@ class Rob(
 
   when(io.hasInterrupt) {
     when(io.commits(0).valid && io.commits(0).ready) {
-      // io.commits(0).bits.instInfo.exceptionRecords(Csr.ExceptionIndex.int) := true.B
       io.commits(0).bits.instInfo.exceptionRecord := Csr.ExceptionIndex.int
       io.commits(0).bits.instInfo.exceptionPos    := ExceptionPos.backend
     }.otherwise {
       hasInterruptReg := true.B
     }
   }.elsewhen(hasInterruptReg && io.commits(0).valid && io.commits(0).ready) {
-    hasInterruptReg := false.B
-    // io.commits(0).bits.instInfo.exceptionRecords(Csr.ExceptionIndex.int) := true.B
+    hasInterruptReg                             := false.B
     io.commits(0).bits.instInfo.exceptionRecord := Csr.ExceptionIndex.int
     io.commits(0).bits.instInfo.exceptionPos    := ExceptionPos.backend
   }
@@ -243,39 +237,6 @@ class Rob(
 
     }
 
-  // /** branch
-  //   *
-  //   * insts between branch inst and enq
-  //   *
-  //   * TODO: clean csr score board
-  //   */
-  // when(io.branchFlushInfo.en) {
-  //   queue.io.enqueuePorts.foreach(_.bits.isValid := false.B)
-  //   when(io.branchFlushInfo.robId >= queue.io.deq_ptr) {
-  //     // ----- deq_ptr --*(stay)*-- branch_ptr(robId) -----
-  //     branchSetQueuePorts.lazyZip(queue.io.elems).zipWithIndex.foreach {
-  //       case ((set, elem), id) =>
-  //         when(id.U < queue.io.deq_ptr || io.branchFlushInfo.robId < id.U) {
-  //           set.valid        := true.B
-  //           set.bits.state   := State.ready // elem.state
-  //           set.bits.wbPort  := elem.wbPort
-  //           set.bits.isValid := false.B
-  //         }
-  //     }
-  //   }.otherwise {
-  //     // --*(stay)*-- branch_ptr(robId) ----- deq_ptr --*(stay)*--
-  //     branchSetQueuePorts.lazyZip(queue.io.elems).zipWithIndex.foreach {
-  //       case ((set, elem), id) =>
-  //         when(io.branchFlushInfo.robId < id.U && id.U < queue.io.deq_ptr) {
-  //           set.valid        := true.B
-  //           set.bits.state   := State.ready // elem.state
-  //           set.bits.wbPort  := elem.wbPort
-  //           set.bits.isValid := false.B
-  //         }
-  //     }
-  //   }
-  // }
-
   /** flush
     */
 
diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala
index 5f7c061b..39539ee0 100644
--- a/src/src/spec/Param.scala
+++ b/src/src/spec/Param.scala
@@ -15,14 +15,13 @@ object Param {
   val scoreboardChangeNum    = 1 // 3
   val csrScoreBoardChangeNum = 1
   val instRegReadNum         = 2
-  val ctrlControlNum         = PipelineStageIndex.count + 1
   val fetchInstMaxNum        = 2 // 单次取指
   val issueInstInfoMaxNum    = 2 // 发射数量
   val commitNum              = 2 // 单次提交数量
   val pipelineNum            = 3 // number of pipeline
   val reservationStationDeep = 4 // 保留站深度
-  val csrRegsReadNum         = 1
-  val csrRegsWriteNum        = 1
+  val csrReadNum             = 1
+  val csrWriteNum            = 1
 
   val csrIssuePipelineIndex       = 1 // csr 相关指令在第1条流水线
   val loadStoreIssuePipelineIndex = 0 // load & store相关指令在第0条流水线