diff --git a/src/src/pipeline/memory/MemReqStage.scala b/src/src/pipeline/memory/MemReqStage.scala
index e0bcc8db..1af291e2 100644
--- a/src/src/pipeline/memory/MemReqStage.scala
+++ b/src/src/pipeline/memory/MemReqStage.scala
@@ -50,7 +50,9 @@ class MemReqStage
       "h_1faf".U(16.W),
       "h_bfaf".U(16.W),
       "h_1fd0".U(16.W), // Chiplab only
-      "h_1fe0".U(16.W) // Chiplab only
+      "h_1fe0".U(16.W), // Chiplab only; serial port
+      "h_1fe7".U(16.W), // FPGA: NAND flash
+      "h_1ff0".U(16.W) // FPGA: Xilinx DMFE
     ).contains(selectedIn.translatedMemReq.addr(Width.Mem._addr - 1, Width.Mem._addr - 16))
   } else if (isPartialUncachedPatch) {
     VecInit(