From 4263a8b9f3f4f7daf88e48a1aed900369ea21309 Mon Sep 17 00:00:00 2001 From: Takehana Date: Wed, 19 Jul 2023 20:30:06 +0800 Subject: [PATCH] feat: add uncached address ranges --- src/src/pipeline/memory/MemReqStage.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/src/pipeline/memory/MemReqStage.scala b/src/src/pipeline/memory/MemReqStage.scala index e0bcc8db..1af291e2 100644 --- a/src/src/pipeline/memory/MemReqStage.scala +++ b/src/src/pipeline/memory/MemReqStage.scala @@ -50,7 +50,9 @@ class MemReqStage "h_1faf".U(16.W), "h_bfaf".U(16.W), "h_1fd0".U(16.W), // Chiplab only - "h_1fe0".U(16.W) // Chiplab only + "h_1fe0".U(16.W), // Chiplab only; serial port + "h_1fe7".U(16.W), // FPGA: NAND flash + "h_1ff0".U(16.W) // FPGA: Xilinx DMFE ).contains(selectedIn.translatedMemReq.addr(Width.Mem._addr - 1, Width.Mem._addr - 16)) } else if (isPartialUncachedPatch) { VecInit(