diff --git a/src/src/frontend/bpu/TagePredictor.scala b/src/src/frontend/bpu/TagePredictor.scala index 66f5888d..6c3c3090 100644 --- a/src/src/frontend/bpu/TagePredictor.scala +++ b/src/src/frontend/bpu/TagePredictor.scala @@ -12,16 +12,16 @@ import frontend.bpu.utils.Lfsr // TAGE predictor // This is the main predictor class TagePredictor( - tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum, - tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth, - ghrDepth: Int = Param.BPU.TagePredictor.ghrLength, - historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength, - phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth, - componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth, - componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth, - entryNum: Int = Param.BPU.RAS.entryNum, - addr: Int = spec.Width.Mem._addr) - extends Module { + tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum, + tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth, + ghrDepth: Int = Param.BPU.TagePredictor.ghrLength, + historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength, + phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth, + componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth, + componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth, + entryNum: Int = Param.BPU.RAS.entryNum, + addr: Int = spec.Width.Mem._addr) + extends Module { val addrWidth = log2Ceil(addr) val pointerWidth = log2Ceil(entryNum) val tagComPtrWidth = log2Ceil(tagComponentNum + 1) @@ -135,45 +135,44 @@ class TagePredictor( basePredictor.io.updatePc := updatePc basePredictor.io.isCtrInc := updateBranchTaken basePredictor.io.updateCtr := updateMetaBundle.providerCtrBits(0) - // basePredictor.io.updateCtr <> io.updateInfoPort.bpuMeta.providerCtrBits(0) // Tagged Predictor Generate val taggedPreditors = Seq.range(0, tagComponentNum).map { providerId => - { - val taggedPreditor = Module( - new TaggedPreditor( - ghrLength = historyLengths(providerId + 1), - phtDepth = phtDepths(providerId + 1), - phtUsefulWidth = componentUsefulWidth(providerId + 1), - phtCtrWidth = componentCtrWidth(providerId + 1) + { + val taggedPreditor = Module( + new TaggedPreditor( + ghrLength = historyLengths(providerId + 1), + phtDepth = phtDepths(providerId + 1), + phtUsefulWidth = componentUsefulWidth(providerId + 1), + phtCtrWidth = componentCtrWidth(providerId + 1) + ) ) - ) - // Query - taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid - taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0) - taggedPreditor.io.pc := io.pc - tagUsefuls(providerId) := taggedPreditor.io.usefulBits - tagCtrs(providerId) := taggedPreditor.io.ctrBits - tagQueryTags(providerId) := taggedPreditor.io.queryTag - tagOriginTags(providerId) := taggedPreditor.io.hitIndex - tagTaken(providerId) := taggedPreditor.io.taken - tagHit(providerId) := taggedPreditor.io.tagHit - - // update - taggedPreditor.io.updatePc := io.updatePc - taggedPreditor.io.updateValid := isUpdateValid && updateIsConditional - taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId) - taggedPreditor.io.updateUseful := tagUpdateUseful(providerId) - taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId) - taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId) - taggedPreditor.io.incCtr := updateBranchTaken - taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId) - taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId) - taggedPreditor.io.updateTag := tagUpdateNewTags(providerId) - taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId) - - taggedPreditor - } + // Query + taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid + taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0) + taggedPreditor.io.pc := io.pc + tagUsefuls(providerId) := taggedPreditor.io.usefulBits + tagCtrs(providerId) := taggedPreditor.io.ctrBits + tagQueryTags(providerId) := taggedPreditor.io.queryTag + tagOriginTags(providerId) := taggedPreditor.io.hitIndex + tagTaken(providerId) := taggedPreditor.io.taken + tagHit(providerId) := taggedPreditor.io.tagHit + + // update + taggedPreditor.io.updatePc := io.updatePc + taggedPreditor.io.updateValid := isUpdateValid && updateIsConditional + taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId) + taggedPreditor.io.updateUseful := tagUpdateUseful(providerId) + taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId) + taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId) + taggedPreditor.io.incCtr := updateBranchTaken + taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId) + taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId) + taggedPreditor.io.updateTag := tagUpdateNewTags(providerId) + taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId) + + taggedPreditor + } } queryIsUseful := (takens(predPredictionId) =/= takens(altPredPredctionId)) @@ -253,7 +252,7 @@ class TagePredictor( // USE_ALT_ON_NA updateNewEntryFlag := (updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 3.U(3.W) || updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 4.U(3.W) && - updateProviderId =/= 0.U) + updateProviderId =/= 0.U) when( isUpdateValid && updateNewEntryFlag && updateMetaBundle.useful && !io.updateInfoPort.predictCorrect @@ -302,16 +301,14 @@ class TagePredictor( // Shorter history component has a higher chance of chosen // foreach from high index to low index - tagUpdateUsefulZeroId := 0.U(log2Ceil(tagComponentNum + 1).W) + tagUpdateUsefulZeroId := 0.U(tagComPtrWidth.W) tagUpdateQueryUsefulsMatch.zipWithIndex.reverse.foreach { case (isMatch, index) => when( - isMatch && (index.asUInt(log2Ceil(tagComponentTagWidth)) + 1.U( - log2Ceil(tagComponentTagWidth).W - ) > updateProviderId) + isMatch && (index.asUInt(log2Ceil(tagComponentTagWidth)) + 1.U > updateProviderId) ) { when(tagUpdateUsefulPingpongCounter(index)) { - tagUpdateUsefulZeroId := index.U((log2Ceil(tagComponentNum + 1).W)) + tagUpdateUsefulZeroId := index.U(tagComPtrWidth.W) } } } diff --git a/src/src/frontend/bpu/components/BasePredictor.scala b/src/src/frontend/bpu/components/BasePredictor.scala index a61a2ea2..f7819a8d 100644 --- a/src/src/frontend/bpu/components/BasePredictor.scala +++ b/src/src/frontend/bpu/components/BasePredictor.scala @@ -60,7 +60,7 @@ class BasePredictor( val ctrRam = Module( new VSimpleDualBRam( - tableDepthLog, // size + tableDepth, // size ctrWidth // dataWidth ) ) diff --git a/src/src/memory/VBRam.scala b/src/src/memory/VBRam.scala index 96f5d131..aebca5fd 100644 --- a/src/src/memory/VBRam.scala +++ b/src/src/memory/VBRam.scala @@ -25,28 +25,44 @@ class VSingleBRam(size: Int, dataWidth: Int) extends Module { io.dataOut := blackBox.io.douta } -//class VTrueDualBRam(size: Int, dataWidth: Int) extends Module { -// // TODO: customize it as you want -// val io = IO(new Bundle {}) -// -// val blackBox = Module(new truedual_readfirst_bram(size, dataWidth)) -// -// blackBox.io.addra := DontCare -// blackBox.io.addrb := DontCare -// blackBox.io.dina := DontCare -// blackBox.io.dinb := DontCare -// blackBox.io.clka := DontCare -// blackBox.io.wea := DontCare -// blackBox.io.web := DontCare -// blackBox.io.ena := DontCare -// blackBox.io.enb := DontCare -// blackBox.io.rsta := DontCare -// blackBox.io.rstb := DontCare -// blackBox.io.regcea := DontCare -// blackBox.io.regceb := DontCare -// DontCare <> blackBox.io.douta -// DontCare <> blackBox.io.doutb -//} +class VTrueDualBRam(size: Int, dataWidth: Int) extends Module { + // TODO: customize it as you want + val addrWidth = log2Ceil(size) + val io = IO(new Bundle { + val port0 = new Bundle() { + val isWrite = Input(Bool()) + val isRead = Input(Bool()) + val addr = Input(UInt(addrWidth.W)) + val dataIn = Input(UInt(dataWidth.W)) + val dataOut = Output(UInt(dataWidth.W)) + } + val port1 = new Bundle() { + val isWrite = Input(Bool()) + val isRead = Input(Bool()) + val addr = Input(UInt(addrWidth.W)) + val dataIn = Input(UInt(dataWidth.W)) + val dataOut = Output(UInt(dataWidth.W)) + } + }) + + val blackBox = Module(new truedual_readfirst_bram(size, dataWidth)) + + blackBox.io.addra := io.port0.addr + blackBox.io.addrb := io.port1.addr + blackBox.io.dina := io.port0.dataIn + blackBox.io.dinb := io.port1.dataIn + blackBox.io.clka := clock + blackBox.io.wea := io.port0.isWrite + blackBox.io.web := io.port1.isWrite + blackBox.io.ena := io.port0.isWrite || io.port0.isRead + blackBox.io.enb := io.port1.isWrite || io.port1.isRead + blackBox.io.rsta := reset + blackBox.io.rstb := reset + blackBox.io.regcea := false.B + blackBox.io.regceb := false.B + io.port0.dataOut <> blackBox.io.douta + io.port1.dataOut <> blackBox.io.doutb +} class VSimpleDualBRam(size: Int, dataWidth: Int) extends Module { val addrWidth = log2Ceil(size)