From 25f2ab8e3ad165ca698a2cffc99c9e205e8f34b6 Mon Sep 17 00:00:00 2001 From: zhengyujie <3257144507@qq.com> Date: Tue, 18 Jul 2023 23:28:56 +0800 Subject: [PATCH 1/4] fix:bug --- src/src/frontend/bpu/TagePredictor.scala | 138 +++++++++++------------ src/src/spec/Param.scala | 48 +------- 2 files changed, 71 insertions(+), 115 deletions(-) diff --git a/src/src/frontend/bpu/TagePredictor.scala b/src/src/frontend/bpu/TagePredictor.scala index a5258f89..66f5888d 100644 --- a/src/src/frontend/bpu/TagePredictor.scala +++ b/src/src/frontend/bpu/TagePredictor.scala @@ -12,16 +12,16 @@ import frontend.bpu.utils.Lfsr // TAGE predictor // This is the main predictor class TagePredictor( - tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum, - tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth, - ghrDepth: Int = Param.BPU.TagePredictor.ghrLength, - historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength, - phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth, - componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth, - componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth, - entryNum: Int = Param.BPU.RAS.entryNum, - addr: Int = spec.Width.Mem._addr) - extends Module { + tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum, + tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth, + ghrDepth: Int = Param.BPU.TagePredictor.ghrLength, + historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength, + phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth, + componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth, + componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth, + entryNum: Int = Param.BPU.RAS.entryNum, + addr: Int = spec.Width.Mem._addr) + extends Module { val addrWidth = log2Ceil(addr) val pointerWidth = log2Ceil(entryNum) val tagComPtrWidth = log2Ceil(tagComponentNum + 1) @@ -37,7 +37,7 @@ class TagePredictor( val updateInfoPort = Input(new TagePredictorUpdateInfoPort) // TODO PMU -// val perfTagHitCounters = Output(Vec(32, UInt((tagComponentNum + 1).W))) + // val perfTagHitCounters = Output(Vec(32, UInt((tagComponentNum + 1).W))) }) @@ -82,9 +82,9 @@ class TagePredictor( val isBaseUpdateCtr = WireDefault(false.B) val isUpdateValid = WireDefault(false.B) val globalHistoryUpdateReg = RegInit(false.B) - val updatePredictCorrect = WireDefault(0.U(tagComponentNum.W)) - val updateBranchTaken = WireDefault(0.U(tagComponentNum.W)) - val updateIsConditional = WireDefault(0.U(tagComponentNum.W)) + val updatePredictCorrect = WireDefault(false.B) + val updateBranchTaken = WireDefault(false.B) + val updateIsConditional = WireDefault(false.B) val updateNewEntryFlag = WireDefault(false.B) // Indicates the provider is new val updateProviderId = WireDefault(0.U(tagComPtrWidth.W)) val updateALtProviderId = WireDefault(0.U(tagComPtrWidth.W)) @@ -139,41 +139,41 @@ class TagePredictor( // Tagged Predictor Generate val taggedPreditors = Seq.range(0, tagComponentNum).map { providerId => - { - val taggedPreditor = Module( - new TaggedPreditor( - ghrLength = historyLengths(providerId + 1), - phtDepth = phtDepths(providerId + 1), - phtUsefulWidth = componentUsefulWidth(providerId + 1), - phtCtrWidth = componentCtrWidth(providerId + 1) - ) + { + val taggedPreditor = Module( + new TaggedPreditor( + ghrLength = historyLengths(providerId + 1), + phtDepth = phtDepths(providerId + 1), + phtUsefulWidth = componentUsefulWidth(providerId + 1), + phtCtrWidth = componentCtrWidth(providerId + 1) ) - // Query - taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid - taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0) - taggedPreditor.io.pc := io.pc - tagUsefuls(providerId) := taggedPreditor.io.usefulBits - tagCtrs(providerId) := taggedPreditor.io.ctrBits - tagQueryTags(providerId) := taggedPreditor.io.queryTag - tagOriginTags(providerId) := taggedPreditor.io.hitIndex - tagTaken(providerId) := taggedPreditor.io.taken - tagHit(providerId) := taggedPreditor.io.tagHit - - // update - taggedPreditor.io.updatePc := io.updatePc - taggedPreditor.io.updateValid := (isUpdateValid & updateIsConditional) - taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId) - taggedPreditor.io.updateUseful := tagUpdateUseful(providerId) - taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId) - taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId) - taggedPreditor.io.incCtr := updateBranchTaken.asBools(providerId) - taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId) - taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId) - taggedPreditor.io.updateTag := tagUpdateNewTags(providerId) - taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId) - - taggedPreditor - } + ) + // Query + taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid + taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0) + taggedPreditor.io.pc := io.pc + tagUsefuls(providerId) := taggedPreditor.io.usefulBits + tagCtrs(providerId) := taggedPreditor.io.ctrBits + tagQueryTags(providerId) := taggedPreditor.io.queryTag + tagOriginTags(providerId) := taggedPreditor.io.hitIndex + tagTaken(providerId) := taggedPreditor.io.taken + tagHit(providerId) := taggedPreditor.io.tagHit + + // update + taggedPreditor.io.updatePc := io.updatePc + taggedPreditor.io.updateValid := isUpdateValid && updateIsConditional + taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId) + taggedPreditor.io.updateUseful := tagUpdateUseful(providerId) + taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId) + taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId) + taggedPreditor.io.incCtr := updateBranchTaken + taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId) + taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId) + taggedPreditor.io.updateTag := tagUpdateNewTags(providerId) + taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId) + + taggedPreditor + } } queryIsUseful := (takens(predPredictionId) =/= takens(altPredPredctionId)) @@ -208,7 +208,7 @@ class TagePredictor( // Output logic io.predictValid := true.B -// takens := Cat(tagTaken, baseTaken) + // takens := Cat(tagTaken, baseTaken) Seq.range(1, tagComponentNum + 1).foreach { i => takens(i) := tagTaken(i - 1) } @@ -239,10 +239,10 @@ class TagePredictor( // skip ctrBitsVec(0) queryMetaBundle.providerCtrBits(i + 1) := tagCtrs(i) ) -// queryMetaPort.providerCtrBits.drop(1).zip(tagCtrs).foreach { -// case (dst, src) => -// dst := src -// } + // queryMetaPort.providerCtrBits.drop(1).zip(tagCtrs).foreach { + // case (dst, src) => + // dst := src + // } io.bpuMetaPort := BpuFtqMetaNdPort.default io.bpuMetaPort.bpuMeta := queryMetaBundle @@ -253,10 +253,10 @@ class TagePredictor( // USE_ALT_ON_NA updateNewEntryFlag := (updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 3.U(3.W) || updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 4.U(3.W) && - updateProviderId =/= 0.U) + updateProviderId =/= 0.U) when( - isUpdateValid & updateNewEntryFlag & - updateMetaBundle.useful & ~io.updateInfoPort.predictCorrect + isUpdateValid && updateNewEntryFlag && + updateMetaBundle.useful && !io.updateInfoPort.predictCorrect ) { useAltOnNaCounterTablesReg(updatePc(4, 2)) := Mux( useALtOnNaCounter === 15.U(4.W), @@ -264,8 +264,8 @@ class TagePredictor( useALtOnNaCounter + 1.U ) }.elsewhen( - isUpdateValid & updateNewEntryFlag & - updateMetaBundle.useful & io.updateInfoPort.predictCorrect + isUpdateValid && updateNewEntryFlag && + updateMetaBundle.useful && io.updateInfoPort.predictCorrect ) { useAltOnNaCounterTablesReg(updatePc(4, 2)) := Mux(useALtOnNaCounter === 0.U(4.W), 0.U(4.W), useALtOnNaCounter - 1.U) } @@ -323,13 +323,13 @@ class TagePredictor( // Fill update structs // update ctr Policy // update provider - when(updateIsConditional.orR & isUpdateValid) { + when(updateIsConditional && isUpdateValid) { updateCtr(updateProviderId) := true.B } // update altProvider if new entry when( - updateNewEntryFlag && updateIsConditional.orR && + updateNewEntryFlag && updateIsConditional && !io.updateInfoPort.predictCorrect && isUpdateValid ) { updateCtr(updateALtProviderId) := true.B @@ -338,13 +338,13 @@ class TagePredictor( // tag update policy // Default 0 -// val tagUpdateUseful = WireDefault(0.U((tagComponentNum + 1).W)) -// val tagUpdateIncUseful = WireDefault(0.U((tagComponentNum + 1).W)) -// val tagUpdateReallocEntry = WireDefault(0.U((tagComponentNum + 1).W)) + // val tagUpdateUseful = WireDefault(0.U((tagComponentNum + 1).W)) + // val tagUpdateIncUseful = WireDefault(0.U((tagComponentNum + 1).W)) + // val tagUpdateReallocEntry = WireDefault(0.U((tagComponentNum + 1).W)) // Only update on conditional branches - when(updateIsConditional.xorR & isUpdateValid) { - when(updatePredictCorrect.xorR) { + when(updateIsConditional & isUpdateValid) { + when(updatePredictCorrect) { // if useful,update useful bits tagUpdateUseful(updateProviderId - 1.U) := updateMetaBundle.useful // Increase if correct, else decrease @@ -377,10 +377,10 @@ class TagePredictor( ) } -// // counter -// Seq.range(0, tagComponentNum + 1).foreach { i => -// io.perfTagHitCounters(i) := io.perfTagHitCounters(i) + Cat(0.U(31.W), (i.U === predPredictionId)) -// } + // // counter + // Seq.range(0, tagComponentNum + 1).foreach { i => + // io.perfTagHitCounters(i) := io.perfTagHitCounters(i) + Cat(0.U(31.W), (i.U === predPredictionId)) + // } // todo debug diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala index a02905f3..7bb84a31 100644 --- a/src/src/spec/Param.scala +++ b/src/src/spec/Param.scala @@ -10,11 +10,11 @@ object Param { val isReleasePackage = false val isDiffTest = false || isChiplab - val isOutOfOrderIssue = false + val isOutOfOrderIssue = true val isFullUncachedPatch = false || isChiplab val isPartialUncachedPatch = false || isReleasePackage val isNoPrivilege = false || isReleasePackage - val isCacheOnPg = false + val isCacheOnPg = true val isForcedCache = false || isReleasePackage val isBranchPredict = true @@ -186,8 +186,6 @@ object Param { val entryNum = 32 } - val decodeWidth = 1 // 2 to do - val commitWidth = 1 // 2 to do object BranchType { var count = 0 private def next = { @@ -203,48 +201,6 @@ object Param { } } - // object BPU { - // val fetchWidth = 4 - // val ftqSize = 8 - - // object TagePredictor { - // val ghrLength = 1400 - // val tagComponentNum = 15 - // val tagComponentTagWidth = 12 - // // ComponentTableDepth - // // length = tagComponentNum +1 - // val componentTableDepth = - // Seq(16384, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024) - // val componentCtrWidth = Seq(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) - // val componentUsefulWidth = Seq(0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) - // val componentHistoryLength = Seq(0, 6, 10, 18, 25, 35, 55, 69, 105, 155, 230, 354, 479, 642, 1012, 1347) - - // } - - // object FTB { - // val nset = 1024 - // val nway = 4 - // } - - // object RAS { - // val entryNum = 32 - // } - - // val decodeWidth = 1 // 2 to do - // val commitWidth = 1 // 2 to do - // object BranchType { - // var count = 0 - // private def next = { - // count += 1 - // count.U - // } - // val cond = 0.U - // val call = next - // val ret = next - // val uncond = next - // } - // } - object SimpleFetchStageState extends ChiselEnum { val idle, requestInst, waitInst = Value } From 0a86ca1c8c6425f94c59bed5542496b0af0e3e7f Mon Sep 17 00:00:00 2001 From: zhengyujie <3257144507@qq.com> Date: Tue, 18 Jul 2023 23:34:04 +0800 Subject: [PATCH 2/4] change param --- src/src/spec/Param.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala index 7bb84a31..01be6d4d 100644 --- a/src/src/spec/Param.scala +++ b/src/src/spec/Param.scala @@ -10,11 +10,11 @@ object Param { val isReleasePackage = false val isDiffTest = false || isChiplab - val isOutOfOrderIssue = true + val isOutOfOrderIssue = false val isFullUncachedPatch = false || isChiplab val isPartialUncachedPatch = false || isReleasePackage val isNoPrivilege = false || isReleasePackage - val isCacheOnPg = true + val isCacheOnPg = false val isForcedCache = false || isReleasePackage val isBranchPredict = true From c149f8b62396013e5ec612aadfe12380b442cc20 Mon Sep 17 00:00:00 2001 From: zhengyujie <3257144507@qq.com> Date: Thu, 20 Jul 2023 19:37:18 +0800 Subject: [PATCH 3/4] feat:change tage param --- src/src/frontend/bpu/TagePredictor.scala | 99 ++++++++++++------------ 1 file changed, 48 insertions(+), 51 deletions(-) diff --git a/src/src/frontend/bpu/TagePredictor.scala b/src/src/frontend/bpu/TagePredictor.scala index 66f5888d..6c3c3090 100644 --- a/src/src/frontend/bpu/TagePredictor.scala +++ b/src/src/frontend/bpu/TagePredictor.scala @@ -12,16 +12,16 @@ import frontend.bpu.utils.Lfsr // TAGE predictor // This is the main predictor class TagePredictor( - tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum, - tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth, - ghrDepth: Int = Param.BPU.TagePredictor.ghrLength, - historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength, - phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth, - componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth, - componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth, - entryNum: Int = Param.BPU.RAS.entryNum, - addr: Int = spec.Width.Mem._addr) - extends Module { + tagComponentNum: Int = Param.BPU.TagePredictor.tagComponentNum, + tagComponentTagWidth: Int = Param.BPU.TagePredictor.tagComponentTagWidth, + ghrDepth: Int = Param.BPU.TagePredictor.ghrLength, + historyLengths: Seq[Int] = Param.BPU.TagePredictor.componentHistoryLength, + phtDepths: Seq[Int] = Param.BPU.TagePredictor.componentTableDepth, + componentCtrWidth: Seq[Int] = Param.BPU.TagePredictor.componentCtrWidth, + componentUsefulWidth: Seq[Int] = Param.BPU.TagePredictor.componentUsefulWidth, + entryNum: Int = Param.BPU.RAS.entryNum, + addr: Int = spec.Width.Mem._addr) + extends Module { val addrWidth = log2Ceil(addr) val pointerWidth = log2Ceil(entryNum) val tagComPtrWidth = log2Ceil(tagComponentNum + 1) @@ -135,45 +135,44 @@ class TagePredictor( basePredictor.io.updatePc := updatePc basePredictor.io.isCtrInc := updateBranchTaken basePredictor.io.updateCtr := updateMetaBundle.providerCtrBits(0) - // basePredictor.io.updateCtr <> io.updateInfoPort.bpuMeta.providerCtrBits(0) // Tagged Predictor Generate val taggedPreditors = Seq.range(0, tagComponentNum).map { providerId => - { - val taggedPreditor = Module( - new TaggedPreditor( - ghrLength = historyLengths(providerId + 1), - phtDepth = phtDepths(providerId + 1), - phtUsefulWidth = componentUsefulWidth(providerId + 1), - phtCtrWidth = componentCtrWidth(providerId + 1) + { + val taggedPreditor = Module( + new TaggedPreditor( + ghrLength = historyLengths(providerId + 1), + phtDepth = phtDepths(providerId + 1), + phtUsefulWidth = componentUsefulWidth(providerId + 1), + phtCtrWidth = componentCtrWidth(providerId + 1) + ) ) - ) - // Query - taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid - taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0) - taggedPreditor.io.pc := io.pc - tagUsefuls(providerId) := taggedPreditor.io.usefulBits - tagCtrs(providerId) := taggedPreditor.io.ctrBits - tagQueryTags(providerId) := taggedPreditor.io.queryTag - tagOriginTags(providerId) := taggedPreditor.io.hitIndex - tagTaken(providerId) := taggedPreditor.io.taken - tagHit(providerId) := taggedPreditor.io.tagHit - - // update - taggedPreditor.io.updatePc := io.updatePc - taggedPreditor.io.updateValid := isUpdateValid && updateIsConditional - taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId) - taggedPreditor.io.updateUseful := tagUpdateUseful(providerId) - taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId) - taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId) - taggedPreditor.io.incCtr := updateBranchTaken - taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId) - taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId) - taggedPreditor.io.updateTag := tagUpdateNewTags(providerId) - taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId) - - taggedPreditor - } + // Query + taggedPreditor.io.isGlobalHistoryUpdate := isUpdateValid + taggedPreditor.io.globalHistory := ghr(historyLengths(providerId + 1), 0) + taggedPreditor.io.pc := io.pc + tagUsefuls(providerId) := taggedPreditor.io.usefulBits + tagCtrs(providerId) := taggedPreditor.io.ctrBits + tagQueryTags(providerId) := taggedPreditor.io.queryTag + tagOriginTags(providerId) := taggedPreditor.io.hitIndex + tagTaken(providerId) := taggedPreditor.io.taken + tagHit(providerId) := taggedPreditor.io.tagHit + + // update + taggedPreditor.io.updatePc := io.updatePc + taggedPreditor.io.updateValid := isUpdateValid && updateIsConditional + taggedPreditor.io.incUseful := tagUpdateIncUseful(providerId) + taggedPreditor.io.updateUseful := tagUpdateUseful(providerId) + taggedPreditor.io.updateUsefulBits := updateMetaBundle.tagPredictorUsefulBits(providerId) + taggedPreditor.io.updateCtr := tagUpdateCtr.asBools(providerId) + taggedPreditor.io.incCtr := updateBranchTaken + taggedPreditor.io.updateCtrBits := updateMetaBundle.providerCtrBits(providerId) + taggedPreditor.io.reallocEntry := tagUpdateReallocEntry(providerId) + taggedPreditor.io.updateTag := tagUpdateNewTags(providerId) + taggedPreditor.io.updateIndex := updateMetaBundle.tagPredictorHitIndex(providerId) + + taggedPreditor + } } queryIsUseful := (takens(predPredictionId) =/= takens(altPredPredctionId)) @@ -253,7 +252,7 @@ class TagePredictor( // USE_ALT_ON_NA updateNewEntryFlag := (updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 3.U(3.W) || updateMetaBundle.providerCtrBits(updateProviderId - 1.U) === 4.U(3.W) && - updateProviderId =/= 0.U) + updateProviderId =/= 0.U) when( isUpdateValid && updateNewEntryFlag && updateMetaBundle.useful && !io.updateInfoPort.predictCorrect @@ -302,16 +301,14 @@ class TagePredictor( // Shorter history component has a higher chance of chosen // foreach from high index to low index - tagUpdateUsefulZeroId := 0.U(log2Ceil(tagComponentNum + 1).W) + tagUpdateUsefulZeroId := 0.U(tagComPtrWidth.W) tagUpdateQueryUsefulsMatch.zipWithIndex.reverse.foreach { case (isMatch, index) => when( - isMatch && (index.asUInt(log2Ceil(tagComponentTagWidth)) + 1.U( - log2Ceil(tagComponentTagWidth).W - ) > updateProviderId) + isMatch && (index.asUInt(log2Ceil(tagComponentTagWidth)) + 1.U > updateProviderId) ) { when(tagUpdateUsefulPingpongCounter(index)) { - tagUpdateUsefulZeroId := index.U((log2Ceil(tagComponentNum + 1).W)) + tagUpdateUsefulZeroId := index.U(tagComPtrWidth.W) } } } From a7ccbf48a7fbb659fff1a707d2e6db8716b8dbae Mon Sep 17 00:00:00 2001 From: zhengyujie <3257144507@qq.com> Date: Thu, 20 Jul 2023 20:43:18 +0800 Subject: [PATCH 4/4] feat:change tage param --- .../bpu/components/BasePredictor.scala | 2 +- src/src/memory/VBRam.scala | 48 ++++++++++++------- 2 files changed, 33 insertions(+), 17 deletions(-) diff --git a/src/src/frontend/bpu/components/BasePredictor.scala b/src/src/frontend/bpu/components/BasePredictor.scala index a8d275c0..a1a47e54 100644 --- a/src/src/frontend/bpu/components/BasePredictor.scala +++ b/src/src/frontend/bpu/components/BasePredictor.scala @@ -60,7 +60,7 @@ class BasePredictor( val ctrRam = Module( new VSimpleDualBRam( - tableDepthLog, // size + tableDepth, // size ctrWidth // dataWidth ) ) diff --git a/src/src/memory/VBRam.scala b/src/src/memory/VBRam.scala index 31a18abe..be6957ec 100644 --- a/src/src/memory/VBRam.scala +++ b/src/src/memory/VBRam.scala @@ -27,25 +27,41 @@ class VSingleBRam(size: Int, dataWidth: Int) extends Module { class VTrueDualBRam(size: Int, dataWidth: Int) extends Module { // TODO: customize it as you want - val io = IO(new Bundle {}) + val addrWidth = log2Ceil(size) + val io = IO(new Bundle { + val port0 = new Bundle() { + val isWrite = Input(Bool()) + val isRead = Input(Bool()) + val addr = Input(UInt(addrWidth.W)) + val dataIn = Input(UInt(dataWidth.W)) + val dataOut = Output(UInt(dataWidth.W)) + } + val port1 = new Bundle() { + val isWrite = Input(Bool()) + val isRead = Input(Bool()) + val addr = Input(UInt(addrWidth.W)) + val dataIn = Input(UInt(dataWidth.W)) + val dataOut = Output(UInt(dataWidth.W)) + } + }) val blackBox = Module(new truedual_readfirst_bram(size, dataWidth)) - blackBox.io.addra := DontCare - blackBox.io.addrb := DontCare - blackBox.io.dina := DontCare - blackBox.io.dinb := DontCare - blackBox.io.clka := DontCare - blackBox.io.wea := DontCare - blackBox.io.web := DontCare - blackBox.io.ena := DontCare - blackBox.io.enb := DontCare - blackBox.io.rsta := DontCare - blackBox.io.rstb := DontCare - blackBox.io.regcea := DontCare - blackBox.io.regceb := DontCare - DontCare <> blackBox.io.douta - DontCare <> blackBox.io.doutb + blackBox.io.addra := io.port0.addr + blackBox.io.addrb := io.port1.addr + blackBox.io.dina := io.port0.dataIn + blackBox.io.dinb := io.port1.dataIn + blackBox.io.clka := clock + blackBox.io.wea := io.port0.isWrite + blackBox.io.web := io.port1.isWrite + blackBox.io.ena := io.port0.isWrite||io.port0.isRead + blackBox.io.enb := io.port1.isWrite||io.port1.isRead + blackBox.io.rsta := reset + blackBox.io.rstb := reset + blackBox.io.regcea := false.B + blackBox.io.regceb := false.B + io.port0.dataOut <> blackBox.io.douta + io.port1.dataOut <> blackBox.io.doutb } class VSimpleDualBRam(size: Int, dataWidth: Int) extends Module {