From 6b3488f2714797bbd977dc06e2f31e48bf2daa53 Mon Sep 17 00:00:00 2001 From: Takehana Date: Mon, 24 Jul 2023 15:46:54 +0800 Subject: [PATCH 1/3] feat: increase cache size --- src/src/pipeline/execution/ExePassWbStage.scala | 4 ---- src/src/spec/Param.scala | 4 ++-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/src/src/pipeline/execution/ExePassWbStage.scala b/src/src/pipeline/execution/ExePassWbStage.scala index b2949de3..ba95532d 100644 --- a/src/src/pipeline/execution/ExePassWbStage.scala +++ b/src/src/pipeline/execution/ExePassWbStage.scala @@ -115,7 +115,6 @@ class ExePassWbStage(supportBranchCsr: Boolean = true) val isSyscall = selectedIn.exeOp === ExeInst.Op.syscall val isBreak = selectedIn.exeOp === ExeInst.Op.break_ - resultOutReg.bits.instInfo.exceptionPos := selectedIn.instInfo.exceptionPos when(selectedIn.instInfo.exceptionPos === ExceptionPos.none) { when(isSyscall) { resultOutReg.bits.instInfo.exceptionPos := ExceptionPos.backend @@ -127,7 +126,6 @@ class ExePassWbStage(supportBranchCsr: Boolean = true) } if (supportBranchCsr) { - if (isDiffTest) { resultOutReg.bits.instInfo.timerInfo.get.isCnt := VecInit(ExeInst.Op.rdcntvl_w, ExeInst.Op.rdcntvh_w) .contains(selectedIn.exeOp) @@ -135,7 +133,6 @@ class ExePassWbStage(supportBranchCsr: Boolean = true) } switch(selectedIn.exeOp) { - is(ExeInst.Op.rdcntvl_w) { resultOutReg.bits.gprWrite.data := io.peer.get.stableCounterReadPort.get.output(wordLength - 1, 0) } @@ -250,6 +247,5 @@ class ExePassWbStage(supportBranchCsr: Boolean = true) when(io.isFlush) { branchEnableFlag := true.B } - } } diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala index 9c104a44..94d30ec6 100644 --- a/src/src/spec/Param.scala +++ b/src/src/spec/Param.scala @@ -79,7 +79,7 @@ object Param { } object DCache { - val _addr = 8 // TODO: Choose an optimal value (small value is suitible for difftest) + val _addr = 10 // TODO: Choose an optimal value (small value is suitible for difftest) val _byteOffset = log2Ceil(Count.DCache.dataPerLine) + log2Ceil(wordLength / byteLength) val _dataLine = Count.DCache.dataPerLine * spec.Width.Mem._data val _tag = spec.Width.Mem._addr - _addr - _byteOffset @@ -92,7 +92,7 @@ object Param { } object ICache { - val _addr = 8 // TODO: Choose an optimal value (small value is suitible for difftest) + val _addr = 10 // TODO: Choose an optimal value (small value is suitible for difftest) val _instOffset = log2Ceil(wordLength / byteLength) val _fetchOffset = log2Ceil(fetchInstMaxNum) + log2Ceil(wordLength / byteLength) val _byteOffset = log2Ceil(Count.ICache.dataPerLine) + log2Ceil(wordLength / byteLength) From 2f9b11d77334e5770041c50979cf256c2099fc4c Mon Sep 17 00:00:00 2001 From: Takehana Date: Mon, 24 Jul 2023 17:06:47 +0800 Subject: [PATCH 2/3] feat: skip a stage when no TLB --- src/src/frontend/fetch/InstAddrTransStage.scala | 6 +++++- src/src/pipeline/memory/AddrTransStage.scala | 7 +++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/src/frontend/fetch/InstAddrTransStage.scala b/src/src/frontend/fetch/InstAddrTransStage.scala index 9e332260..74c7c5bb 100644 --- a/src/src/frontend/fetch/InstAddrTransStage.scala +++ b/src/src/frontend/fetch/InstAddrTransStage.scala @@ -38,7 +38,11 @@ class InstAddrTransStage val selectedIn = io.in.bits val peer = io.peer.get - val out = resultOutReg.bits + val out = if (isNoPrivilege) io.out.bits else resultOutReg.bits + if (isNoPrivilege) { + io.in.ready := io.out.ready + io.out.valid := io.in.valid + } val pc = WireDefault(0.U(Width.inst)) pc := selectedIn.ftqBlockBundle.startPc diff --git a/src/src/pipeline/memory/AddrTransStage.scala b/src/src/pipeline/memory/AddrTransStage.scala index de996281..8d0ebf1b 100644 --- a/src/src/pipeline/memory/AddrTransStage.scala +++ b/src/src/pipeline/memory/AddrTransStage.scala @@ -45,7 +45,11 @@ class AddrTransStage ) { val selectedIn = io.in.bits val peer = io.peer.get - val out = resultOutReg.bits + val out = if (isNoPrivilege) io.out.bits else resultOutReg.bits + if (isNoPrivilege) { + io.in.ready := io.out.ready + io.out.valid := io.in.valid + } val tlbBlockingReg = RegInit(false.B) tlbBlockingReg := tlbBlockingReg @@ -181,7 +185,6 @@ class AddrTransStage } if (isNoPrivilege) { peer.tlbMaintenance := DontCare - io.in.ready := inReady } // Handle flush (actually is TLB maintenance done) From dd7de5fe436ab724fe456d1982f8278a68a04302 Mon Sep 17 00:00:00 2001 From: Takehana Date: Mon, 24 Jul 2023 22:14:21 +0800 Subject: [PATCH 3/3] feat: skip a stage when no TLB --- src/src/pipeline/memory/AddrTransStage.scala | 4 ++++ src/src/pipeline/memory/MemReqStage.scala | 21 +++++++++++++++++--- src/src/spec/Param.scala | 8 ++++++-- 3 files changed, 28 insertions(+), 5 deletions(-) diff --git a/src/src/pipeline/memory/AddrTransStage.scala b/src/src/pipeline/memory/AddrTransStage.scala index 8d0ebf1b..bd6ad273 100644 --- a/src/src/pipeline/memory/AddrTransStage.scala +++ b/src/src/pipeline/memory/AddrTransStage.scala @@ -192,6 +192,10 @@ class AddrTransStage tlbBlockingReg := false.B } + if (isNoPrivilege) { + tlbBlockingReg := true.B + } + // Submit result when(selectedIn.instInfo.isValid && !tlbBlockingReg && io.in.ready && io.in.valid) { resultOutReg.valid := true.B diff --git a/src/src/pipeline/memory/MemReqStage.scala b/src/src/pipeline/memory/MemReqStage.scala index 1af291e2..1525e294 100644 --- a/src/src/pipeline/memory/MemReqStage.scala +++ b/src/src/pipeline/memory/MemReqStage.scala @@ -10,7 +10,7 @@ import pipeline.common.{BaseStage, LookupQueue} import pipeline.memory.bundles.{CacheMaintenanceInstNdPort, MemRequestNdPort, StoreInfoBundle} import pipeline.memory.enums.CacheMaintenanceTargetType import spec._ -import spec.Param.{isFullUncachedPatch, isPartialUncachedPatch} +import spec.Param.{isFullUncachedPatch, isMmioDelay, isPartialUncachedPatch} class MemReqNdPort extends Bundle { val isAtomicStore = new Bool() @@ -50,7 +50,7 @@ class MemReqStage "h_1faf".U(16.W), "h_bfaf".U(16.W), "h_1fd0".U(16.W), // Chiplab only - "h_1fe0".U(16.W), // Chiplab only; serial port + "h_1fe0".U(16.W), // Serial port "h_1fe7".U(16.W), // FPGA: NAND flash "h_1ff0".U(16.W) // FPGA: Xilinx DMFE ).contains(selectedIn.translatedMemReq.addr(Width.Mem._addr - 1, Width.Mem._addr - 16)) @@ -63,6 +63,21 @@ class MemReqStage false.B } + // Delay load for MMIO + val isAdditionalLoadReady = Wire(Bool()) + if (isMmioDelay) { + val isMmioAddressMatched = + selectedIn.translatedMemReq.addr(Width.Mem._addr - 1, Width.Mem._addr - 16) === "h_1fe0".U(16.W) + val MmioCountDownReg = RegInit(Param.Count.Mem.MmioDelayMax.U) + MmioCountDownReg := MmioCountDownReg - 1.U + when(isLastComputed || io.isFlush) { + MmioCountDownReg := Param.Count.Mem.MmioDelayMax.U + } + isAdditionalLoadReady := !isMmioAddressMatched || (!MmioCountDownReg.orR && !isLastComputed) + } else { + isAdditionalLoadReady := true.B + } + val isTrueCached = selectedIn.isCached && !isUncachedAddressRange val isInstantReq = WireDefault(selectedIn.translatedMemReq.isValid) @@ -132,7 +147,7 @@ class MemReqStage switch(selectedIn.translatedMemReq.rw) { is(ReadWriteSel.read) { // Whether last memory request is submitted and no stores in queue and not committing store - when(io.out.ready && !storeQueue.io.lookup.out) { // TODO: Might optimize + when(io.out.ready && !storeQueue.io.lookup.out && isAdditionalLoadReady) { // TODO: Might optimize when(isTrueCached) { peer.dCacheReq.client.isValid := true.B isComputed := peer.dCacheReq.isReady diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala index 94d30ec6..5852059c 100644 --- a/src/src/spec/Param.scala +++ b/src/src/spec/Param.scala @@ -6,19 +6,22 @@ import chisel3.{ChiselEnum, _} object Param { // Configurable self-defined parameters go here + // These options are one-hot val isChiplab = true val isReleasePackage = false + val isFullFpga = false val isDiffTest = false || isChiplab val isOutOfOrderIssue = true - val isFullUncachedPatch = false || isChiplab + val isFullUncachedPatch = false || isChiplab || isFullFpga val isPartialUncachedPatch = false || isReleasePackage + val isMmioDelay = false || isChiplab || isFullFpga val isNoPrivilege = false || isReleasePackage val isCacheOnPg = false val isForcedCache = false || isReleasePackage val isForcedUncached = false val isBranchPredict = true - val isTagePredictorTagCompare = false || isChiplab + val isTagePredictorTagCompare = true val isWritebackPassThroughWakeUp = true val canIssueSameWbRegInsts = true @@ -131,6 +134,7 @@ object Param { object Mem { val storeQueueLen = 8 + val MmioDelayMax = 5 } }