From 6aafe76c24414da7866f22b5c65b7feef446cf17 Mon Sep 17 00:00:00 2001 From: Chrisqcwx <3075401625@qq.com> Date: Wed, 26 Jul 2023 19:32:16 +0800 Subject: [PATCH 1/2] refactor pmu --- .../rs/InOrderReservationStation.scala | 1 + .../rs/SimpleOoOReservationStation.scala | 1 + src/src/pmu/Pmu.scala | 48 ++++++++++--------- src/src/pmu/bundles/PmuDispatchBundle.scala | 1 + 4 files changed, 28 insertions(+), 23 deletions(-) diff --git a/src/src/pipeline/dispatch/rs/InOrderReservationStation.scala b/src/src/pipeline/dispatch/rs/InOrderReservationStation.scala index 742471c0..c6fd21ac 100644 --- a/src/src/pipeline/dispatch/rs/InOrderReservationStation.scala +++ b/src/src/pipeline/dispatch/rs/InOrderReservationStation.scala @@ -156,6 +156,7 @@ class InOrderReservationStation( val pmu = io.pmu_dispatchInfo.get val isFull = !queue.io.enqueuePorts.head.ready val isEmpty = !queue.io.dequeuePorts.head.valid + pmu.enqueue := io.enqueuePorts.head.valid && io.enqueuePorts.head.ready && !io.isFlush pmu.isFull := isFull && !io.isFlush pmu.bubbleFromBackend := io.dequeuePorts.head.valid && !io.dequeuePorts.head.ready && !io.isFlush pmu.bubbleFromRSEmpty := isEmpty && !io.isFlush diff --git a/src/src/pipeline/dispatch/rs/SimpleOoOReservationStation.scala b/src/src/pipeline/dispatch/rs/SimpleOoOReservationStation.scala index 65d2145f..dae8245d 100644 --- a/src/src/pipeline/dispatch/rs/SimpleOoOReservationStation.scala +++ b/src/src/pipeline/dispatch/rs/SimpleOoOReservationStation.scala @@ -215,6 +215,7 @@ class SimpleOoOReservationStation( if (Param.usePmu) { val pmu = io.pmu_dispatchInfo.get + pmu.enqueue := io.enqueuePorts.head.valid && io.enqueuePorts.head.ready && !io.isFlush pmu.isFull := isFull && !io.isFlush pmu.bubbleFromBackend := io.dequeuePorts.head.valid && !io.dequeuePorts.head.ready && !io.isFlush pmu.bubbleFromRSEmpty := isEmpty && !io.isFlush diff --git a/src/src/pmu/Pmu.scala b/src/src/pmu/Pmu.scala index a2517d37..56fb3012 100644 --- a/src/src/pmu/Pmu.scala +++ b/src/src/pmu/Pmu.scala @@ -51,6 +51,7 @@ class Pmu extends Module { val dispatchBubbleFromDataDependences = Seq.fill(Param.pipelineNum)(r) val dispatchBubbleFromRSEmptys = Seq.fill(Param.pipelineNum)(r) val dispatchRSFulls = Seq.fill(Param.pipelineNum)(r) + val dispatchRSEnqueueNum = Seq.fill(Param.pipelineNum)(r) io.dispatchInfos.zipWithIndex.foreach { case (dispatchInfo, idx) => @@ -66,6 +67,7 @@ class Pmu extends Module { when(dispatchInfo.bubbleFromRSEmpty) { inc(dispatchBubbleFromRSEmptys(idx)) } + condInc(dispatchRSEnqueueNum(idx), dispatchInfo.enqueue) } val robFull = r @@ -73,19 +75,19 @@ class Pmu extends Module { inc(robFull) } - val branch = r - val branchSuccess = r - val branchFail = r - val unconditionalBranch = r - val unconditionalBranchFail = r - val conditionalBranch = r - val conditionalBranchFail = r - val callBranch = r - val callBranchFail = r - val returnBranch = r - val returnBranchFail = r - val directionMispredict = r - val targetMispredict = r + val branch = r + val branchSuccess = r + val branchFail = r + val branchUnconditional = r + val branchUnconditionalFail = r + val branchConditional = r + val branchConditionalFail = r + val branchCall = r + val branchCallFail = r + val branchReturn = r + val branchReturnFail = r + val branchDirectionMispredict = r + val branchTargetMispredict = r when(io.branchInfo.isBranch) { inc(branch) @@ -95,32 +97,32 @@ class Pmu extends Module { inc(branchSuccess) } - condInc(directionMispredict, io.branchInfo.directionMispredict) - condInc(targetMispredict, io.branchInfo.targetMispredict) + condInc(branchDirectionMispredict, io.branchInfo.directionMispredict) + condInc(branchTargetMispredict, io.branchInfo.targetMispredict) switch(io.branchInfo.branchType) { is(Param.BPU.BranchType.uncond) { - inc(unconditionalBranch) + inc(branchUnconditional) when(io.branchInfo.isRedirect) { - inc(unconditionalBranchFail) + inc(branchUnconditionalFail) } } is(Param.BPU.BranchType.cond) { - inc(conditionalBranch) + inc(branchConditional) when(io.branchInfo.isRedirect) { - inc(conditionalBranchFail) + inc(branchConditionalFail) } } is(Param.BPU.BranchType.call) { - inc(callBranch) + inc(branchCall) when(io.branchInfo.isRedirect) { - inc(callBranchFail) + inc(branchCallFail) } } is(Param.BPU.BranchType.ret) { - inc(returnBranch) + inc(branchReturn) when(io.branchInfo.isRedirect) { - inc(returnBranchFail) + inc(branchReturnFail) } } } diff --git a/src/src/pmu/bundles/PmuDispatchBundle.scala b/src/src/pmu/bundles/PmuDispatchBundle.scala index a9202cf6..3bee665e 100644 --- a/src/src/pmu/bundles/PmuDispatchBundle.scala +++ b/src/src/pmu/bundles/PmuDispatchBundle.scala @@ -8,4 +8,5 @@ class PmuDispatchBundle extends Bundle { val bubbleFromDataDependence = Bool() val bubbleFromRSEmpty = Bool() val isFull = Bool() + val enqueue = Bool() } From c0f7bbf56fbc3829967d488466fd66b39cf5b85f Mon Sep 17 00:00:00 2001 From: Chrisqcwx <3075401625@qq.com> Date: Wed, 26 Jul 2023 20:36:53 +0800 Subject: [PATCH 2/2] fix: pmu assign error --- src/src/CoreCpuTop.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/src/CoreCpuTop.scala b/src/src/CoreCpuTop.scala index 26cacc80..de3e13da 100644 --- a/src/src/CoreCpuTop.scala +++ b/src/src/CoreCpuTop.scala @@ -345,7 +345,7 @@ class CoreCpuTop extends Module { case (dst, src) => dst := src } - pmu.io.robFull := rob.io.requests.head.ready && !cu.io.backendFlush + pmu.io.robFull := !rob.io.requests.head.ready && !cu.io.backendFlush }