diff --git a/src/src/memory/ICache.scala b/src/src/memory/ICache.scala
index e1d4b2ff..1b0c60f3 100644
--- a/src/src/memory/ICache.scala
+++ b/src/src/memory/ICache.scala
@@ -304,8 +304,8 @@ class ICache(
 
         axiMaster.io.read.req.isValid := true.B
         axiMaster.io.read.req.addr := Cat(
-          lastReg.memAddr(Width.Mem._addr - 1, Param.Width.DCache._byteOffset),
-          0.U(Param.Width.DCache.byteOffset)
+          lastReg.memAddr(Width.Mem._addr - 1, Param.Width.ICache._byteOffset),
+          0.U(Param.Width.ICache.byteOffset)
         )
 
         when(axiMaster.io.read.req.isReady) {
diff --git a/src/src/spec/Param.scala b/src/src/spec/Param.scala
index c8960f33..814b5f9c 100644
--- a/src/src/spec/Param.scala
+++ b/src/src/spec/Param.scala
@@ -90,7 +90,8 @@ object Param {
     }
 
     object DCache {
-      val _addr           = 8 // TODO: Choose an optimal value (small value is suitible for difftest)
+      val _addr =
+        if (isReleasePackage) 8 else 10 // TODO: Choose an optimal value (small value is suitible for difftest)
       val _byteOffset     = log2Ceil(Count.DCache.dataPerLine) + log2Ceil(wordLength / byteLength)
       val _dataLine       = Count.DCache.dataPerLine * spec.Width.Mem._data
       val _tag            = spec.Width.Mem._addr - _addr - _byteOffset
@@ -103,7 +104,8 @@ object Param {
     }
 
     object ICache {
-      val _addr           = 8 // TODO: Choose an optimal value (small value is suitible for difftest)
+      val _addr =
+        if (isReleasePackage) 8 else 10 // TODO: Choose an optimal value (small value is suitible for difftest)
       val _instOffset     = log2Ceil(wordLength / byteLength)
       val _fetchOffset    = log2Ceil(fetchInstMaxNum) + log2Ceil(wordLength / byteLength)
       val _byteOffset     = log2Ceil(Count.ICache.dataPerLine) + log2Ceil(wordLength / byteLength)
@@ -125,7 +127,7 @@ object Param {
 
     object DCache {
       val setLen      = 2 // Also the number of RAMs for data; TODO: Choose an optimal value
-      val dataPerLine = 16 // TODO: One data line is 64 bytes
+      val dataPerLine = if (isReleasePackage) 8 else 16
       val sizePerRam  = math.pow(2, Width.DCache._addr).toInt
     }