diff --git a/src/src/frontend/FetchTargetQueue.scala b/src/src/frontend/FetchTargetQueue.scala
index 1d4bcdb7..5e742ed5 100644
--- a/src/src/frontend/FetchTargetQueue.scala
+++ b/src/src/frontend/FetchTargetQueue.scala
@@ -242,13 +242,16 @@ class FetchTargetQueue(
   io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.fallThroughAddr := ftqBranchMetaRegs(commitFtqId).fallThroughAddr
 
   // commit to ras
-  io.ftqRasPort.valid         := io.commitFtqTrainPort.isTrainValid
-  io.ftqRasPort.bits.isPush   := io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.call
-  io.ftqRasPort.bits.isPop    := io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.ret
-  io.ftqRasPort.bits.callAddr := ftqBranchMetaRegs(commitFtqId).fallThroughAddr
-  io.ftqRasPort.bits.predictError := ftqBranchMetaRegs(
-    commitFtqId
-  ).ftbDirty || (io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken)
+  io.ftqRasPort.valid         := RegNext(io.commitFtqTrainPort.isTrainValid, false.B)
+  io.ftqRasPort.bits.isPush   := RegNext(io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.call, false.B)
+  io.ftqRasPort.bits.isPop    := RegNext(io.commitFtqTrainPort.branchTakenMeta.branchType === BranchType.ret, false.B)
+  io.ftqRasPort.bits.callAddr := RegNext(ftqBranchMetaRegs(commitFtqId).fallThroughAddr, 0.U)
+  io.ftqRasPort.bits.predictError := RegNext(
+    ftqBranchMetaRegs(
+      commitFtqId
+    ).ftbDirty || (io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken),
+    false.B
+  )
 //  }
 
   // Bpu meta ram
@@ -314,9 +317,12 @@ class FetchTargetQueue(
     io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.jumpTargetAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateJumpTarget
     io.bpuFtqPort.ftqBpuTrainMeta.branchAddrBundle.fallThroughAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough
 
-    io.ftqRasPort.bits.callAddr := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough
-    io.ftqRasPort.bits.predictError := io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFtbDirty ||
-      (io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken)
+    io.ftqRasPort.bits.callAddr := RegNext(io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFallThrough, 0.U)
+    io.ftqRasPort.bits.predictError := RegNext(
+      io.exeFtqPort.feedBack.commitBundle.ftqMetaUpdateFtbDirty ||
+        (io.commitFtqTrainPort.branchTakenMeta.predictedTaken ^ io.commitFtqTrainPort.branchTakenMeta.isTaken),
+      false.B
+    )
   }
 
 }
diff --git a/src/src/frontend/bpu/RAS.scala b/src/src/frontend/bpu/RAS.scala
index 95fab0c9..aba4d3df 100644
--- a/src/src/frontend/bpu/RAS.scala
+++ b/src/src/frontend/bpu/RAS.scala
@@ -67,8 +67,10 @@ class RAS(
   }
   // Output
   if (Param.isOverideRas) {
-    io.topAddr := Mux(io.predictError, lutram(readIndex), predictLutram(predictReadIndex))
+//    io.topAddr := Mux(io.predictError, lutram(readIndex), predictLutram(predictReadIndex))
+    io.topAddr := predictLutram(predictReadIndex)
   } else {
     io.topAddr := lutram(predictReadIndex)
   }
+
 }