From cadce39ddad68c080c064c96aa443cdea1d1e919 Mon Sep 17 00:00:00 2001 From: Daniel Black Date: Thu, 21 May 2026 11:54:35 +1000 Subject: [PATCH] MDEV-39692 innodb intrinsics fail to compile on ARMv8.3-A and later (but not ARMv9.x) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Assembler messages: {standard input}:169: Error: selected processor does not support `retaa' {standard input}:271: Error: selected processor does not support `retaa' It happens because the pmem_cvap() funciton manually inserts the `.arch armv8-2.a` clause, making GAS believe that retaa instruction (inserted by GCC) is invalid. Replaced compiler dependent version by using the generic sys instruction: __asm__ __volatile__(/* dc cvap, %0 */ "sys #3, c7, c12, 1, %0" :: "r"(u) : "memory"); Co-authored-by: gemini-code-assist Reported-by: Dmitry Baryshkov Reviewed-by: Marko Mäkelä Original solution: https://lore.kernel.org/openembedded-devel/20260520113418.2523208-1-dmitry.baryshkov@oss.qualcomm.com/ --- storage/innobase/sync/cache.cc | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/storage/innobase/sync/cache.cc b/storage/innobase/sync/cache.cc index c5e67709e22b2..064c29d6f0205 100644 --- a/storage/innobase/sync/cache.cc +++ b/storage/innobase/sync/cache.cc @@ -82,11 +82,8 @@ static void pmem_cvap(const void* buf, size_t size) for (uintptr_t u= uintptr_t(buf) & ~(CPU_LEVEL1_DCACHE_LINESIZE), end= uintptr_t(buf) + size; u < end; u+= CPU_LEVEL1_DCACHE_LINESIZE) -#if defined __ARM_ARCH && __ARM_ARCH == 9 - __asm__ __volatile__(".arch armv9.4-a\n dc cvap, %0" :: "r"(u) : "memory"); -#else - __asm__ __volatile__(".arch armv8.2-a\n dc cvap, %0" :: "r"(u) : "memory"); -#endif + __asm__ __volatile__(/* dc cvap, %0 */ "sys #3, c7, c12, 1, %0" :: + "r"(u) : "memory"); __asm__ __volatile__("dmb ishst" ::: "memory"); }