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4805 lines (4167 loc) · 195 KB
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/*
* mips_start_of_header
*
* Copyright (c) [Year(s)] MIPS Technologies, Inc. All rights reserved.
*
* Unpublished rights reserved under U.S. copyright law.
*
* PROPRIETARY/SECRET CONFIDENTIAL INFORMATION OF MIPS TECHNOLOGIES,
* INC. FOR INTERNAL USE ONLY.
*
* Under no circumstances (contract or otherwise) may this information be
* disclosed to, or copied, modified or used by anyone other than employees
* or contractors of MIPS Technologies having a need to know.
*
*
* mips_end_of_header
*
*++
* File: ArchDefs.h
*
* Description:
* Architecture definitions
*
* Compile Options:
* MIPSAVPENV selects the special MIPS AVP environment
*
* Notes:
*
* ArchDefs.h: 1.261
*/
#ifndef _ArchDefs_h_
#define _ArchDefs_h_
/*
* Define __ASSEMBLER__ if a different tool specific define indicating
* the an assembly language file is being processed is set. This allows
* support for new tools to be added in one place (here). The remainder
* of ArchDefs.h simply uses __ASSEMBLER__ to separate assembly specific
* code from C or C++ code.
*/
#if defined(MIPSAVPENV) || defined(__LANGUAGE_ASM__) || defined(__assembler)
#undef __ASSEMBLER__
#define __ASSEMBLER__
#endif
/*
* Utility defines for cross platform handling of 64bit constants.
*/
#if defined(__ASSEMBLER__) && !defined(KEEPINT64)
#undef UINT64_C
#undef INT64_C
#define UINT64_C(c) c
#define INT64_C(c) c
#endif /* defined(__ASSEMBLER__) */
/*
************************************************************************
* I N S T R U C T I O N F O R M A T S *
************************************************************************
*
* The following definitions describe each field in an instruction. There
* is one diagram for each type of instruction, with field definitions
* following the diagram for that instruction. Note that if a field of
* the same name and position is defined in an earlier diagram, it is
* not defined again in the subsequent diagram. Only new fields are
* defined for each diagram.
*
* R-Type (operate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | rs | rt | rd | sa | |
* | Opcode | | | Tcode | func |
* | | Bcode | |
* | | |s| |h| |s| |
* | | |r| |b| hint |c| | sel |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnOpcode 26
#define M_InstnOpcode (0x3f << S_InstnOpcode)
#define S_InstnRS 21
#define M_InstnRS (0x1f << S_InstnRS)
#define S_InstnRT 16
#define M_InstnRT (0x1f << S_InstnRT)
#define S_InstnRD 11
#define M_InstnRD (0x1f << S_InstnRD)
#define S_InstnSA 6
#define M_InstnSA (0x1f << S_InstnSA)
#define S_InstnTcode 6
#define M_InstnTcode (0x3ff << S_InstnTcode)
#define S_InstnBcode 6
#define M_InstnBcode (0xfffff << S_InstnBcode)
#define S_InstnFunc 0
#define M_InstnFunc (0x3f << S_InstnFunc)
#define S_InstnSel 0
#define M_InstnSel (0x7 << S_InstnSel)
/* to distinguish release2 DI/EI */
#define S_InstnSC 5
#define M_InstnSC (0x1 << S_InstnSC)
/* to distinguish release2 shift/rotate */
#define S_InstnSR 21
#define M_InstnSR (0x1 << S_InstnSR)
/* to distinguish release2 jump with hazard barrier */
#define S_InstnHB 10
#define M_InstnHB (0x1 << S_InstnHB)
/*
* I-Type (load, store, branch, immediate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | rt | Offset |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnOffset 0
#define M_InstnOffset (0xffff << S_InstnOffset)
/*
* I12-Type (aclr, aset)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | RIFunc |S|ABit | Offset12 |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnABit 12
#define M_InstnABit (0x7 << S_InstnABit)
#define S_InstnOffset12 0
#define M_InstnOffset12 (0xfff << S_InstnOffset12)
/*
* I-Type (pref)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | hint | Offset |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnHint S_InstnRT
#define M_InstnHint M_InstnRT
/*
* J-Type (jump)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | JIndex |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnJIndex 0
#define M_InstnJIndex (0x03ffffff << S_InstnJIndex)
/*
* FP R-Type (operate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmt | ft | fs | fd | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnFmt S_InstnRS
#define M_InstnFmt M_InstnRS
#define S_InstnFT S_InstnRT
#define M_InstnFT M_InstnRT
#define S_InstnFS S_InstnRD
#define M_InstnFS M_InstnRD
#define S_InstnFD S_InstnSA
#define M_InstnFD M_InstnSA
/*
* FP R-Type (cpu <-> cpu data movement))
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | sub | rt | fs | 0 |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnSub S_InstnRS
#define M_InstnSub M_InstnRS
/*
* FP R-Type (compare)
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | | | | | |C| |
* | Opcode | fmt | ft | fs | cc |0|A| func |
* | | | | | | |B| |
* | | | | | | |S| |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnCCcmp 8
#define M_InstnCCcmp (0x7 << S_InstnCCcmp)
#define S_InstnCABS 6
#define M_InstnCABS (0x1 << S_InstnCABS)
/*
* FP R-Type (FPR conditional move on FP cc)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmt | cc |n|t| fs | fd | func |
* | | | |d|f| | | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnCC 18
#define M_InstnCC (0x7 << S_InstnCC)
#define S_InstnND 17
#define M_InstnND (0x1 << S_InstnND)
#define S_InstnTF 16
#define M_InstnTF (0x1 << S_InstnTF)
/*
* FP R-Type (3-operand operate)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fr | ft | fs | fd | op4 | fmt3|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnFR S_InstnRS
#define M_InstnFR M_InstnRS
#define S_InstnOp4 3
#define M_InstnOp4 (0x7 << S_InstnOp4)
#define S_InstnFmt3 0
#define M_InstnFmt3 (0x7 << S_InstnFmt3)
/*
* FP R-Type (Indexed load, store)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | rt | 0 | fd | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* FP R-Type (prefx)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | rt | hint | 0 | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnHintX S_InstnRD
#define M_InstnHintX M_InstnRD
/*
* FP R-Type (GPR conditional move on FP cc)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | cc |n|t| rd | 0 | func |
* | | | |d|f| | | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* FP I-Type (load, store)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rs | ft | Offset |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* FP I-Type (branch)
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmt | cc |n|t| Offset |
* | | | |d|f| |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* Vector Type
*
* bit[25:21] This field is mostly format select (fmtsel), or combind
* with operation select for shuffle, read/write accumulator,
* or fourth register (rs) for variable alignment, or
* immediate for constant alignment.
* bit[10] L bit is only used for VMac instructions.
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | fmtsel | vt | vs | vd | func |
* | | fmt/op | | | | |
* | | rs | | | | |
* | | 0 | imm | | |L| | |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_InstnVT S_InstnRT
#define M_InstnVT M_InstnRT
#define S_InstnVS S_InstnRD
#define M_InstnVS M_InstnRD
#define S_InstnVD S_InstnSA
#define M_InstnVD M_InstnSA
#define S_InstnFmtsel S_InstnFmt
#define M_InstnFmtsel (0x1 << S_InstnFmtsel)
#define S_InstnVImm S_InstnFmt
#define M_InstnVImm (0x7 << S_InstnVImm)
#define S_InstnL 10
#define M_InstnL (0x1 << S_InstnL)
/*
************************************************************************
* M I P S 1 6 I N S T R U C T I O N F O R M A T S *
************************************************************************
*/
/*
* MIPS16 I Type (operate)
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | Immediate |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnOpcode 11
#define M_M16_InstnOpcode (0x1f << S_M16_InstnOpcode)
#define S_M16_InstnOffset 0
#define M_M16_InstnOffset (0x7ff << S_M16_InstnOffset)
/*
* MIPS16 RI Type
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rx | Immediate |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnRX 8
#define M_M16_InstnRX (0x7 << S_M16_InstnRX)
#define S_M16_InstnOffset7 0
#define M_M16_InstnOffset7 (0xff << S_M16_InstnOffset7)
/*
* MIPS16 Breakpoint Type
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | code | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnBPcode 5
#define M_M16_InstnBPcode (0x3f << S_M16_InstnBPcode)
/*
* MIPS16 RR Type
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rx | ry | func |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* MIPS16 RRI Type
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rx | ry |Immediate|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnRY 5
#define M_M16_InstnRY (0x7 << S_M16_InstnRY)
#define S_M16_InstnFunc 0
#define M_M16_InstnFunc (0x1f << S_M16_InstnFunc)
/*
* MIPS16 RRR Type
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode | rx | ry | rz | f |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
/*
* MIPS16 Shift1 Type
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Extend | sa[4:0] |5| 0 | Opcode | rx | ry | sa | f |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnExtendSA4 22
#define M_M16_InstnExtendSA4 (0x1f << S_M16_InstnExtendSA4)
#define S_M16_InstnExtendSA5 21
#define M_M16_InstnExtendSA5 (0x1 << S_M16_InstnExtendSA5)
#define S_M16_InstnShiftF 0
#define M_M16_InstnShiftF (0x3 << S_M16_InstnShiftF)
#define S_M16_InstnRZ 2
#define M_M16_InstnRZ (0x7 << S_M16_InstnRZ)
#define S_M16_InstnSA 2
#define M_M16_InstnSA (0x7 << S_M16_InstnSA)
/*
* MIPS16 EXTEND
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Extend | [10:5] | [15:11] |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnExtendOffset15 16
#define M_M16_InstnExtendOffset15 (0x1f << S_M16_InstnExtendOffset15)
#define S_M16_InstnExtendOffset10 21
#define M_M16_InstnExtendOffset10 (0x3f << S_M16_InstnExtendOffset10)
/*
* MIPS16 RRI-A Type
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Extend | [10:4] |[14:11]| Opcode | rx | ry |f| immed |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnF 4
#define M_M16_InstnF (0x1 << S_M16_InstnF)
#define S_M16_InstnOffset3 0
#define M_M16_InstnOffset3 (0xf << S_M16_InstnOffset3)
#define S_M16_InstnExtendOffset14 16
#define M_M16_InstnExtendOffset14 (0xf << S_M16_InstnExtendOffset14)
#define S_M16_InstnExtendOffset10_4 20
#define M_M16_InstnExtendOffset10_4 (0x7f << S_M16_InstnExtendOffset10_4)
/*
* MIPS16 JALX
*
* 3 3 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Opcode |x| [20:16] | [25:21] | target[15:0] |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnX 26
#define M_M16_InstnX (0x1 << S_M16_InstnX)
#define S_M16_InstnTarget2 21
#define M_M16_InstnTarget2 (0x1f << S_M16_InstnTarget2)
#define S_M16_InstnTarget1 16
#define M_M16_InstnTarget1 (0x1f << S_M16_InstnTarget1)
#define S_M16_InstnTarget0 0
#define M_M16_InstnTarget0 (0xffff << S_M16_InstnTarget0)
/*
* MIPS16 MOVE32R
*
* 1 1 1 1 1 1
* 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | I8 |mv32r| 2:0 |4:3| rz |
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnRZ0 0
#define M_M16_InstnRZ0 (0x7 << S_M16_InstnRZ0)
#define S_M16_InstnR32u 3
#define M_M16_InstnR32u (0x3 << S_M16_InstnR32u)
#define S_M16_InstnR32l 5
#define M_M16_InstnR32l (0x7 << S_M16_InstnR32l)
/*
* MIPS16 save/restore
*
* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | Extend |xsreg|f[7:4] | aregs | I8 |svrs |S|a|0|1|frmsize|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*/
#define S_M16_InstnXsregs 24
#define M_M16_InstnXsregs (0x7 << S_M16_InstnXsregs)
#define S_M16_InstnFrameSize7 20
#define M_M16_InstnFrameSize7 (0xf << S_M16_InstnFrameSize7)
#define S_M16_InstnAregs 16
#define M_M16_InstnAregs (0xf << S_M16_InstnAregs)
#define S_M16_InstnS 7
#define M_M16_InstnS (0x1 << S_M16_InstnS)
#define S_M16_InstnRa 6
#define M_M16_InstnRa (0x1 << S_M16_InstnRa)
#define S_M16_InstnS0 5
#define M_M16_InstnS0 (0x1 << S_M16_InstnS0)
#define S_M16_InstnS1 4
#define M_M16_InstnS1 (0x1 << S_M16_InstnS1)
#define S_M16_InstnFrameSize 0
#define M_M16_InstnFrameSize (0xf << S_M16_InstnFrameSize)
/*
*************************************************************************
* V I R T U A L A D D R E S S D E F I N I T I O N S *
*************************************************************************
*/
#ifdef MIPSADDR64
#define A_K0BASE UINT64_C(0xffffffff80000000)
#define A_K1BASE UINT64_C(0xffffffffa0000000)
#define A_K2BASE UINT64_C(0xffffffffc0000000)
#define A_K3BASE UINT64_C(0xffffffffe0000000)
#define A_REGION UINT64_C(0xc000000000000000)
#define A_XKPHYS_ATTR UINT64_C(0x3800000000000000)
#else
#define A_K0BASE 0x80000000
#define A_K1BASE 0xa0000000
#define A_K2BASE 0xc0000000
#define A_K3BASE 0xe0000000
#endif
#define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */
#define M_KUNCACHED 0x20000000 /* K[01]SEG address is uncached if bit is one */
#ifdef MIPS_Model64
#define S_VMAP64 62
#define M_VMAP64 UINT64_C(0xc000000000000000)
#define K_VMode11 3
#define K_VMode10 2
#define K_VMode01 1
#define K_VMode00 0
#define S_KSEG3 29
#define M_KSEG3 (0x7 << S_KSEG3)
#define K_KSEG3 7
#define S_SSEG 29
#define M_SSEG (0x7 << S_KSEG3)
#define K_SSEG 6
#define S_KSSEG 29
#define M_KSSEG (0x7 << S_KSEG3)
#define K_KSSEG 6
#define S_KSEG1 29
#define M_KSEG1 (0x7 << S_KSEG3)
#define K_KSEG1 5
#define S_KSEG0 29
#define M_KSEG0 (0x7 << S_KSEG3)
#define K_KSEG0 4
#define S_XKSEG 29
#define M_XKSEG (0x7 << S_KSEG3)
#define K_XKSEG 3
#define S_USEG 31
#define M_USEG (0x1 << S_USEG)
#define K_USEG 0
#define S_EjtagProbeMem 20
#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem)
#define K_EjtagProbeMem 0
#else
#define S_KSEG3 29
#define M_KSEG3 (0x7 << S_KSEG3)
#define K_KSEG3 7
#define S_KSSEG 29
#define M_KSSEG (0x7 << S_KSSEG)
#define K_KSSEG 6
#define S_SSEG 29
#define M_SSEG (0x7 << S_SSEG)
#define K_SSEG 6
#define S_KSEG1 29
#define M_KSEG1 (0x7 << S_KSEG1)
#define K_KSEG1 5
#define S_KSEG0 29
#define M_KSEG0 (0x7 << S_KSEG0)
#define K_KSEG0 4
#define S_KUSEG 31
#define M_KUSEG (0x1 << S_KUSEG)
#define K_KUSEG 0
#define S_SUSEG 31
#define M_SUSEG (0x1 << S_SUSEG)
#define K_SUSEG 0
#define S_USEG 31
#define M_USEG (0x1 << S_USEG)
#define K_USEG 0
#define K_EjtagLower 0xff200000
#define K_EjtagUpper 0xff3fffff
#define S_EjtagProbeMem 20
#define M_EjtagProbeMem (0x1 << S_EjtagProbeMem)
#define K_EjtagProbeMem 0
#endif
/*
*************************************************************************
* C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S *
*************************************************************************
*/
/*
* Cache encodings
*/
#define K_CachePriI 0 /* Primary Icache */
#define K_CachePriD 1 /* Primary Dcache */
#define K_CachePriU 1 /* Unified primary */
#define K_CacheTerU 2 /* Unified Tertiary */
#define K_CacheSecU 3 /* Unified secondary */
/*
* Function encodings
*/
#define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */
#define K_CacheIndexInv 0 /* Index invalidate */
#define K_CacheIndexWBInv 0 /* Index writeback invalidate */
#define K_CacheIndexLdTag 1 /* Index load tag */
#define K_CacheIndexStTag 2 /* Index store tag */
#define K_CacheHitInv 4 /* Hit Invalidate */
#define K_CacheFill 5 /* Fill (Icache only) */
#define K_CacheHitWBInv 5 /* Hit writeback invalidate */
#define K_CacheHitWB 6 /* Hit writeback */
#define K_CacheFetchLock 7 /* Fetch and lock */
#define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
#define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
#define DCIndexInv DCIndexWBInv
#define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
#define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
#define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
#define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
#define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
#define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
#define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI)
#define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
#define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
#define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
#define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
#define SCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CacheSecU)
#define SCIndexInv SCIndexWBInv
#define SCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CacheSecU)
#define SCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CacheSecU)
#define SCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CacheSecU)
#define SCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CacheSecU)
#define SCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CacheSecU)
#define TCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CacheTerU)
#define TCIndexInv TCIndexWBInv
#define TCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CacheTerU)
#define TCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CacheTerU)
#define TCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CacheTerU)
#define TCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CacheTerU)
#define TCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CacheTerU)
/*
*************************************************************************
* P R E F E T C H I N S T R U C T I O N H I N T S *
*************************************************************************
*/
#define PrefLoad 0
#define PrefStore 1
#define PrefLoadStreamed 4
#define PrefStoreStreamed 5
#define PrefLoadRetained 6
#define PrefStoreRetained 7
#define PrefWBInval 25
#define PrefNudge 25
#define PrefPrepareForStore 30
/*
*************************************************************************
* C P U R E G I S T E R D E F I N I T I O N S *
*************************************************************************
*/
/*
*************************************************************************
* S O F T W A R E G P R N A M E S *
*************************************************************************
*/
#if defined(__ASSEMBLER__)
#define zero $0
#define AT $1
#define v0 $2
#define v1 $3
#define a0 $4
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24
#define t9 $25
#define k0 $26
#define k1 $27
#define gp $28
#define sp $29
#define fp $30
#define ra $31
#endif
/*
* The following registers are used by the AVP environment and
* are not part of the normal software definitions.
*/
#ifdef MIPSAVPENV
#define repc $25 /* Expected exception PC */
#define tid $30 /* Current test case address */
#endif
/*
*************************************************************************
* H A R D W A R E G P R N A M E S *
*************************************************************************
*
* In the AVP environment, several of the `r' names are removed from the
* name space because they are used by the kernel for special purposes.
* Removing them causes assembly rather than runtime errors for tests that
* use the `r' names.
*
* - r25 (repc) is used as the expected PC on an exception
* - r26-r27 (k0, k1) are used in the exception handler
* - r30 (tid) is used as the current test address
*/
#if defined(__ASSEMBLER__)
#define r0 $0
#define r1 $1
#define r2 $2
#define r3 $3
#define r4 $4
#define r5 $5
#define r6 $6
#define r7 $7
#define r8 $8
#define r9 $9
#define r10 $10
#define r11 $11
#define r12 $12
#define r13 $13
#define r14 $14
#define r15 $15
#define r16 $16
#define r17 $17
#define r18 $18
#define r19 $19
#define r20 $20
#define r21 $21
#define r22 $22
#define r23 $23
#define r24 $24
#ifdef MIPSAVPENV
#define r25 r25_unknown
#define r26 r26_unknown
#define r27 r27_unknown
#else
#define r25 $25
#define r26 $26
#define r27 $27
#endif
#define r28 $28
#define r29 $29
#ifdef MIPSAVPENV
#define r30 r30_unknown
#else
#define r30 $30
#endif
#define r31 $31
#endif /* defined(__ASSEMBLER__) */
/*
*************************************************************************
* H A R D W A R E G P R I N D I C E S *
*************************************************************************
*
* These definitions provide the index (number) of the GPR, as opposed
* to the assembler register name ($n).
*/
#define R_r0 0
#define R_r1 1
#define R_r2 2
#define R_r3 3
#define R_r4 4
#define R_r5 5
#define R_r6 6
#define R_r7 7
#define R_r8 8
#define R_r9 9
#define R_r10 10
#define R_r11 11
#define R_r12 12
#define R_r13 13
#define R_r14 14
#define R_r15 15
#define R_r16 16
#define R_r17 17
#define R_r18 18
#define R_r19 19
#define R_r20 20
#define R_r21 21
#define R_r22 22
#define R_r23 23
#define R_r24 24
#define R_r25 25
#define R_r26 26
#define R_r27 27
#define R_r28 28
#define R_r29 29
#define R_r30 30
#define R_r31 31
/*
*************************************************************************
* S O F T W A R E G P R I N D I C E S *
*************************************************************************
*
* These definitions provide the index (number) of the GPR, as opposed
* to the assembler register name ($n).
*/
#define R_zero 0
#define R_AT 1
#define R_v0 2
#define R_v1 3
#define R_a0 4
#define R_a1 5
#define R_a2 6
#define R_a3 7
#define R_t0 8
#define R_t1 9
#define R_t2 10
#define R_t3 11
#define R_t4 12
#define R_t5 13
#define R_t6 14
#define R_t7 15
#define R_s0 16
#define R_s1 17
#define R_s2 18
#define R_s3 19
#define R_s4 20
#define R_s5 21
#define R_s6 22
#define R_s7 23
#define R_t8 24
#define R_t9 25
#define R_repc 25
#define R_k0 26
#define R_k1 27
#define R_gp 28
#define R_sp 29
#define R_fp 30
#define R_s8 30
#define R_tid 30
#define R_ra 31
#define R_hi 32 /* Hi register */
#define R_lo 33 /* Lo register */
/*
*************************************************************************
* S O F T W A R E G P R M A S K S *
*************************************************************************
*
* These definitions provide the bit mask corresponding to the GPR number
*/
#define M_AT (1<<1)
#define M_v0 (1<<2)
#define M_v1 (1<<3)
#define M_a0 (1<<4)
#define M_a1 (1<<5)
#define M_a2 (1<<6)
#define M_a3 (1<<7)
#define M_t0 (1<<8)
#define M_t1 (1<<9)
#define M_t2 (1<<10)
#define M_t3 (1<<11)
#define M_t4 (1<<12)
#define M_t5 (1<<13)
#define M_t6 (1<<14)
#define M_t7 (1<<15)
#define M_s0 (1<<16)
#define M_s1 (1<<17)
#define M_s2 (1<<18)
#define M_s3 (1<<19)
#define M_s4 (1<<20)
#define M_s5 (1<<21)
#define M_s6 (1<<22)
#define M_s7 (1<<23)
#define M_t8 (1<<24)
#define M_t9 (1<<25)
#define M_k0 (1<<26)
#define M_k1 (1<<27)
#define M_gp (1<<28)
#define M_sp (1<<29)
#define M_fp (1<<30)
#define M_ra (1<<31)
/*
*************************************************************************
* H A R D W A R E A C C I N D I C E S *
*************************************************************************
*/
#define A_ac0 0
#define A_ac1 1
#define A_ac2 2
#define A_ac3 3