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Initial Commit of XiangShan CPU
Use fake Icache to fetch 8 instructions per cycle.
1 parent 6a54961 commit 1e3fad1

23 files changed

+737
-60
lines changed

‎Makefile‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ build/top.zip: $(TOP_V)
3737

3838
verilog: $(TOP_V)
3939

40-
SIM_TOP = NOOPSimTop
40+
SIM_TOP = XSSimTop
4141
SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
4242
$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
4343
mkdir -p $(@D)

‎build.sbt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
2626
}
2727
}
2828

29-
name := "noop"
29+
name := "xiangshan"
3030

3131
version := "3.1.1"
3232

‎src/main/scala/system/SoC.scala‎

Lines changed: 15 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1,49 +1,42 @@
11
package system
22

3-
import noop._
3+
import noop.{Cache,CacheConfig}
44
import bus.axi4.{AXI4, AXI4Lite}
55
import bus.simplebus._
66
import device.AXI4Timer
7-
87
import chisel3._
98
import chisel3.util._
109
import chisel3.util.experimental.BoringUtils
10+
import xiangshan.{XSConfig, XSCore}
1111

1212
trait HasSoCParameter {
1313
val EnableILA = true
1414
val HasL2cache = true
1515
val HasPrefetch = true
1616
}
1717

18-
class ILABundle extends Bundle {
19-
val WBUpc = UInt(32.W)
20-
val WBUvalid = UInt(1.W)
21-
val WBUrfWen = UInt(1.W)
22-
val WBUrfDest = UInt(5.W)
23-
val WBUrfData = UInt(64.W)
24-
val InstrCnt = UInt(64.W)
25-
}
18+
class ILABundle extends Bundle {}
2619

27-
class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
20+
class XSSoc(implicit val p: XSConfig) extends Module with HasSoCParameter {
2821
val io = IO(new Bundle{
2922
val mem = new AXI4
30-
val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
23+
val mmio = if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC }
3124
val frontend = Flipped(new AXI4)
3225
val meip = Input(Bool())
3326
val ila = if (p.FPGAPlatform && EnableILA) Some(Output(new ILABundle)) else None
3427
})
3528

36-
val noop = Module(new NOOP)
29+
val xsCore = Module(new XSCore)
3730
val cohMg = Module(new CoherenceManager)
3831
val xbar = Module(new SimpleBusCrossbarNto1(2))
39-
cohMg.io.in <> noop.io.imem.mem
40-
noop.io.dmem.coh <> cohMg.io.out.coh
32+
cohMg.io.in <> xsCore.io.imem.mem
33+
xsCore.io.dmem.coh <> cohMg.io.out.coh
4134
xbar.io.in(0) <> cohMg.io.out.mem
42-
xbar.io.in(1) <> noop.io.dmem.mem
35+
xbar.io.in(1) <> xsCore.io.dmem.mem
4336

4437
val axi2sb = Module(new AXI42SimpleBusConverter())
4538
axi2sb.io.in <> io.frontend
46-
noop.io.frontend <> axi2sb.io.out
39+
xsCore.io.frontend <> axi2sb.io.out
4740

4841
if (HasL2cache) {
4942
val l2cacheOut = Wire(new SimpleBusC)
@@ -65,17 +58,16 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
6558
} else {
6659
io.mem <> xbar.io.out.toAXI4()
6760
}
68-
69-
noop.io.imem.coh.resp.ready := true.B
70-
noop.io.imem.coh.req.valid := false.B
71-
noop.io.imem.coh.req.bits := DontCare
61+
xsCore.io.imem.coh.resp.ready := true.B
62+
xsCore.io.imem.coh.req.valid := false.B
63+
xsCore.io.imem.coh.req.bits := DontCare
7264

7365
val addrSpace = List(
7466
(0x40000000L, 0x08000000L), // external devices
7567
(0x48000000L, 0x00010000L) // CLINT
7668
)
7769
val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))
78-
mmioXbar.io.in <> noop.io.mmio
70+
mmioXbar.io.in <> xsCore.io.mmio
7971

8072
val extDev = mmioXbar.io.out(0)
8173
val clint = Module(new AXI4Timer(sim = !p.FPGAPlatform))
@@ -87,22 +79,4 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
8779
val meipSync = RegNext(RegNext(io.meip))
8880
BoringUtils.addSource(mtipSync, "mtip")
8981
BoringUtils.addSource(meipSync, "meip")
90-
91-
// ILA
92-
if (p.FPGAPlatform) {
93-
def BoringUtilsConnect(sink: UInt, id: String) {
94-
val temp = WireInit(0.U(64.W))
95-
BoringUtils.addSink(temp, id)
96-
sink := temp
97-
}
98-
99-
val dummy = WireInit(0.U.asTypeOf(new ILABundle))
100-
val ila = io.ila.getOrElse(dummy)
101-
BoringUtilsConnect(ila.WBUpc ,"ilaWBUpc")
102-
BoringUtilsConnect(ila.WBUvalid ,"ilaWBUvalid")
103-
BoringUtilsConnect(ila.WBUrfWen ,"ilaWBUrfWen")
104-
BoringUtilsConnect(ila.WBUrfDest ,"ilaWBUrfDest")
105-
BoringUtilsConnect(ila.WBUrfData ,"ilaWBUrfData")
106-
BoringUtilsConnect(ila.InstrCnt ,"ilaInstrCnt")
107-
}
108-
}
82+
}

‎src/main/scala/top/TopMain.scala‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,25 @@
11
package top
22

3-
import noop.NOOPConfig
4-
import system.NOOPSoC
5-
import device.{AXI4Timer, AXI4VGA, AXI4Flash}
3+
import system.XSSoc
4+
import device.{AXI4Flash, AXI4Timer, AXI4VGA}
65
import gpu._
7-
86
import chisel3._
7+
import xiangshan.XSConfig
98

109
class Top extends Module {
1110
val io = IO(new Bundle{})
12-
val noop = Module(new NOOPSoC()(NOOPConfig()))
11+
val xsSoc = Module(new XSSoc()(XSConfig()))
1312
val timer = Module(new AXI4Timer)
1413
val vga = Module(new AXI4VGA)
1514
val flash = Module(new AXI4Flash)
1615
// val gpu = Module(new AXI4GPU)
1716

18-
noop.io := DontCare
17+
xsSoc.io := DontCare
1918
timer.io := DontCare
2019
vga.io := DontCare
2120
flash.io := DontCare
2221
// gpu.io := DontCare
23-
dontTouch(noop.io)
22+
dontTouch(xsSoc.io)
2423
dontTouch(timer.io)
2524
dontTouch(vga.io)
2625
dontTouch(flash.io)

‎src/main/scala/xiangshan/Bundle.scala‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
package xiangshan
2+
3+
import chisel3._
4+
5+
class FetchPacket extends XSBundle {
6+
val instrs = Vec(FetchWidth, UInt(32.W))
7+
val mask = UInt(FetchWidth.W)
8+
val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
9+
}
10+
11+
class Redirect extends XSBundle {
12+
val target = UInt(VAddrBits.W)
13+
}

‎src/main/scala/xiangshan/XSCore.scala‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
package xiangshan
2+
3+
import chisel3._
4+
import chisel3.util._
5+
import bus.simplebus._
6+
import noop.{Cache, CacheConfig, HasExceptionNO, TLB, TLBConfig}
7+
import utils.PipelineConnect
8+
import xiangshan.backend._
9+
import xiangshan.ifu.FakeIFU
10+
11+
trait HasXSParameter {
12+
val XLEN = 64
13+
val HasMExtension = true
14+
val HasCExtension = true
15+
val HasDiv = true
16+
val HasIcache = true
17+
val HasDcache = true
18+
val EnableStoreQueue = false
19+
val AddrBits = 64 // AddrBits is used in some cases
20+
val VAddrBits = 39 // VAddrBits is Virtual Memory addr bits
21+
val PAddrBits = 32 // PAddrBits is Phyical Memory addr bits
22+
val AddrBytes = AddrBits / 8 // unused
23+
val DataBits = XLEN
24+
val DataBytes = DataBits / 8
25+
val HasFPU = true
26+
val FetchWidth = 8
27+
val CommitWidth = 6
28+
}
29+
30+
abstract class XSModule extends Module
31+
with HasXSParameter
32+
with HasExceptionNO
33+
34+
abstract class XSBundle extends Bundle
35+
with HasXSParameter
36+
37+
case class XSConfig
38+
(
39+
FPGAPlatform: Boolean = true,
40+
EnableDebug: Boolean = false
41+
)
42+
43+
class XSCore(implicit val p: XSConfig) extends XSModule {
44+
val io = IO(new Bundle {
45+
val imem = new SimpleBusC
46+
val dmem = new SimpleBusC
47+
val mmio = new SimpleBusUC
48+
val frontend = Flipped(new SimpleBusUC())
49+
})
50+
51+
io.imem <> DontCare
52+
53+
val dmemXbar = Module(new SimpleBusCrossbarNto1(3))
54+
55+
val ifu = Module(new FakeIFU)
56+
val backend = Module(new Backend)
57+
58+
ifu.io.redirect := backend.io.redirect
59+
PipelineConnect(ifu.io.fetchPacket, backend.io.fetchPacket, true.B, false.B)
60+
61+
backend.io.memMMU.imem <> DontCare
62+
63+
val dtlb = TLB(
64+
in = backend.io.dmem,
65+
mem = dmemXbar.io.in(1),
66+
flush = false.B,
67+
csrMMU = backend.io.memMMU.dmem
68+
)(TLBConfig(name = "dtlb", totalEntry = 64))
69+
dmemXbar.io.in(0) <> dtlb.io.out
70+
dmemXbar.io.in(2) <> io.frontend
71+
72+
io.dmem <> Cache(
73+
in = dmemXbar.io.out,
74+
mmio = Seq(io.mmio),
75+
flush = "b00".U,
76+
empty = dtlb.io.cacheEmpty,
77+
enable = HasDcache
78+
)(CacheConfig(name = "dcache"))
79+
}

‎src/main/scala/xiangshan/backend/Backend.scala‎

Lines changed: 70 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,70 @@
1+
package xiangshan.backend
2+
3+
import bus.simplebus.SimpleBusUC
4+
import chisel3._
5+
import chisel3.util._
6+
import chisel3.util.experimental.BoringUtils
7+
import noop.MemMMUIO
8+
import xiangshan.{FetchPacket, Redirect, XSConfig, XSModule}
9+
10+
11+
class Backend(implicit val p: XSConfig) extends XSModule {
12+
val io = IO(new Bundle {
13+
val dmem = new SimpleBusUC(addrBits = VAddrBits)
14+
val memMMU = Flipped(new MemMMUIO)
15+
16+
val fetchPacket = Flipped(DecoupledIO(new FetchPacket)) // from frontend
17+
val redirect = ValidIO(new Redirect)
18+
})
19+
20+
io.dmem <> DontCare
21+
io.memMMU <> DontCare
22+
io.redirect.valid := false.B
23+
io.redirect.bits <> DontCare
24+
25+
io.fetchPacket.ready := true.B
26+
27+
28+
29+
// TODO: Remove sink and source
30+
val tmp = WireInit(0.U)
31+
val sinks = Array[String](
32+
"DTLBFINISH",
33+
"DTLBPF",
34+
"DTLBENABLE",
35+
"perfCntCondMdcacheLoss",
36+
"perfCntCondMl2cacheLoss",
37+
"perfCntCondMdcacheHit",
38+
"lsuMMIO",
39+
"perfCntCondMl2cacheHit",
40+
"perfCntCondMl2cacheReq",
41+
"mtip",
42+
"perfCntCondMdcacheReq",
43+
"meip"
44+
)
45+
for (s <- sinks){ BoringUtils.addSink(tmp, s) }
46+
47+
// A fake commit
48+
// TODO: difftest 6 insts per cycle
49+
val commit = io.fetchPacket.fire()
50+
val pc = io.fetchPacket.bits.pc
51+
val inst = io.fetchPacket.bits.instrs(0)
52+
53+
if(!p.FPGAPlatform){
54+
BoringUtils.addSource(commit, "difftestCommit")
55+
BoringUtils.addSource(pc, "difftestThisPC")
56+
BoringUtils.addSource(inst, "difftestThisINST")
57+
BoringUtils.addSource(tmp, "difftestIsMMIO")
58+
BoringUtils.addSource(tmp, "difftestIsRVC")
59+
BoringUtils.addSource(tmp, "difftestIntrNO")
60+
BoringUtils.addSource(VecInit(Seq.fill(64)(tmp)), "difftestRegs")
61+
BoringUtils.addSource(tmp, "difftestMode")
62+
BoringUtils.addSource(tmp, "difftestMstatus")
63+
BoringUtils.addSource(tmp, "difftestSstatus")
64+
BoringUtils.addSource(tmp, "difftestMepc")
65+
BoringUtils.addSource(tmp, "difftestSepc")
66+
BoringUtils.addSource(tmp, "difftestMcause")
67+
BoringUtils.addSource(tmp, "difftestScause")
68+
}
69+
70+
}

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