fix for chipsalliance/rocket-chip#2967 (#1562)

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic

Co-authored-by: Yinan Xu <xuyinan@ict.ac.cn>

Author: sequencer

rocket-chip

@@ -25,13 +25,11 @@ import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.apb._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree
 import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
 import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.debug.{DebugCustomXbar, DebugIO, DebugTransportModuleJTAG, JtagDTMConfig, PSDIO, ResetCtrlIO, SystemJTAGIO, TLDebugModule}
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
 import freechips.rocketchip.devices.debug._
 
 // this file uses code from rocketchip Periphery.scala
@@ -50,8 +48,6 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
 //  debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
 //    l2xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
 //  }
-  val fakeTreeNode = new GenericLogicalTreeNode
-  LogicalModuleTree.add(fakeTreeNode, debug.logicalTreeNode)
 
   lazy val module = new LazyRawModuleImp(this) {
     val io = IO(new Bundle{

src/main/scala/device/RocketDebugWrapper.scala

@@ -4,7 +4,6 @@ import chisel3._
 import chipsalliance.rocketchip.config.{Config, Parameters}
 import chisel3.util.{Valid, ValidIO}
 import freechips.rocketchip.diplomacy.{BundleBridgeSink, LazyModule, LazyModuleImp, LazyModuleImpLike}
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortParameters, IntSinkPortSimple}
 import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
 import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLIdentityNode, TLNode, TLTempNode, TLXbar}
@@ -43,7 +42,7 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule
   val mmio_port = TLIdentityNode() // to L3
   val memory_port = TLIdentityNode()
   val beu = LazyModule(new BusErrorUnit(
-    new XSL1BusErrors(), BusErrorUnitParams(0x38010000), new GenericLogicalTreeNode
+    new XSL1BusErrors(), BusErrorUnitParams(0x38010000)
   ))
   val busPMU = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
   val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform)

src/main/scala/xiangshan/XSTile.scala

@@ -20,7 +20,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.rocket.DecodeLogic
-import xiangshan.backend.decode.Instructions._
+import freechips.rocketchip.rocket.Instructions._
 import xiangshan.backend.fu.fpu.FPU
 import xiangshan.{FPUCtrlSignals, XSModule}
 

src/main/scala/xiangshan/backend/decode/DecodeUnit.scala

@@ -18,10 +18,10 @@ package xiangshan.backend.decode
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
-import chisel3.util.BitPat.bitPatToUInt
 import chisel3.util._
-import xiangshan._
+import freechips.rocketchip.rocket.Instructions
 import utils._
+import xiangshan._
 
 abstract class BaseFusionCase(pair: Seq[Valid[UInt]])(implicit p: Parameters)
   extends DecodeUnitConstants {
@@ -67,7 +67,7 @@ class FusedAdduw(pair: Seq[Valid[UInt]])(implicit p: Parameters) extends BaseFus
 
   def isValid: Bool = inst1Cond && inst2Cond && withSameDest && destToRs1
   def target: CtrlSignals = {
-    val cs = getBaseCS(Instructions.ADDU_W)
+    val cs = getBaseCS(Instructions.ADD_UW)
     cs.lsrc(0) := instr1Rs1
     cs.lsrc(1) := 0.U
     cs

src/main/scala/xiangshan/backend/decode/FPDecoder.scala

@@ -118,6 +118,7 @@ package object xiangshan {
 
   object FuOpType {
     def apply() = UInt(7.W)
+    def X = BitPat("b???????")
   }
 
   object CommitType {