slides

Internals

1. Software Modeling

   • History of software modeling
   • Computer Science Stack: HW & SW layouts, ISA
   • CISC vs RISC
   • RISC-V RV32I Introduction & Overview
   • QEMU usage

2. Simple Interpreter

   • Interpretation insights
   • Basic CPU Architectural state
   • Simple interpreters and its optimizations
   • Semihosting
   • TOY ISA Introduction & Overview

3. Decoder

   • Introduction into Ruby Language
   • Metaprogramming and DSL Intro

4. ELF

   • Virtual Memory
   • Executable and Linkable Format
   • Review Linux address space
   • elfio usage example

5. Advanced Simulation Techniques

   • Introduction into binary translation techniques
   • Static binary translation and its optimizations
   • Dynamic binary translation, its application and optimizations
   • SMC Problem
   • Commit & Patch (Template Translation)
   • Direct Execution

6. Architecture Description Language

   • Automated Machine Readable specification and its application
   • Automatically Generated Simulators
   • Automatization of Decoder Implementation
   • Decoders in real simulators

7. Memory Management Unit

   • Motivation
   • RISC-V example (Sv32)
   • TLB
   • Exception Levels
   • RISC-V System Registers
   • Exceptions Handling

8. Trace Driven Simulation

   • Introduction into trace technology and its application
   • Definition of trace-driver simulation
   • ChampSim Introduction & Overview

9. Full-System Simulation

   • SE vs FS simulation mode
   • Introduction into DES (Discrete Event Model)
   • Full-System Simulation and Event-driven model

10. Parallel Simulation

    • Multicore CPU simulation with PDES (Parallel Discrete Event Model)
    • Distributed Shared Memory
    • Event queue in Parallel Simulation
    • Optimistic Models

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11. Classification

    • Simulation Classification Survey
    • Introduction into Protea Framework
    • Cooperation Project Rules

12. Testing

    • Unit Testing
    • Automated Testing and its application
    • Fuzzing
    • Co-simulation

13. Caches

    • CPU Test Generation
    • Static Symbolic Execution
    • Coverage

14. Caches

    • Introduction into the concept and structure of caches
    • Cache memory modeling and its corner cases
    • Cache Coherence Protocols
    • Prefetching (HW/SW)

15. Digital Logic (based Digital Design and Computer Architecture)

    • Digital Logic Level
    • Introduction into Analogue electronics
    • Introduction into Digital Logic
    • Sequential & Combination Logic
    • Functional Units
    • Memory

16. Pipeline (based Digital Design and Computer Architecture)

    • uArch Level
    • Single Cycle RISC-V processor
    • Multi Cycle RISC-V processor
    • Pipeline RISC-V processor
    • O3 RISC-V processor

17. Cycle-Accurate Models

    • Introduction into Cycle-Accurate models
    • CA models software implementation details
    • gem5 Introduction & Overview

18. System Description Overview

    • Introduction into System Description Languages (SDL)
    • SystemC
    • DML
    • Current State
    • Introduction into Hardware Description Languages
    • Verilog
    • Simulating HDL with Verilator
    • Introduction into Protea Language of Devices (PLoD)

19. FP & SIMD Introduction

    • History
    • AArch64 FP & SIMD
    • RVV
    • Vectorization and its application