merge from refactor-core

Author: albertlee

.gitignore

@@ -195,3 +195,11 @@ cython_debug/
 .cursorindexingignore
 uv.lock
 local_docs/
+
+.DS_Store
+
+#pytorch minst dataset
+examples/data
+
+examples/circuit.json
+examples/qml_param_v2.npy

README.md

@@ -0,0 +1,31 @@
+TyxonQ Next Documentation (WIP)
+================================
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Getting Started
+
+   quickstart
+   tutorials
+
+.. toctree::
+   :maxdepth: 2
+   :caption: User Guide
+
+   user/core_ir
+   user/compiler
+   user/devices
+   user/postprocessing
+   user/numerics
+
+.. toctree::
+   :maxdepth: 2
+   :caption: API Reference
+
+   api/core
+   api/compiler
+   api/devices
+   api/postprocessing
+   api/numerics
+
+

TECHNICAL_ARCHITECTURE_REPORT.md

@@ -0,0 +1,12 @@
+Quickstart
+==========
+
+This is a work-in-progress quickstart for the refactored TyxonQ.
+
+Contents to be added:
+- Installation and environment
+- First circuit with core IR and builder
+- Compile → Schedule → Execute workflow
+- Postprocessing basics
+
+

docs-ng/source/next/index.rst

@@ -0,0 +1,6 @@
+Compiler
+========
+
+Unified compile API, pipeline stages, and providers.
+
+

docs-ng/source/next/quickstart.rst

@@ -0,0 +1,6 @@
+Core IR
+=======
+
+Overview of Circuit/Hamiltonian/Pulse IR and metadata conventions.
+
+

docs-ng/source/next/user/compiler.rst

@@ -0,0 +1,6 @@
+Devices
+=======
+
+Device protocol, simulators (wavefunction/density-matrix/compressed), hardware adapters, and session execution plans.
+
+

docs-ng/source/next/user/core_ir.rst

@@ -0,0 +1,6 @@
+Numerics
+========
+
+ArrayBackend protocol, backends (numpy/pytorch/cupynumeric), vectorize_or_fallback, and diagnostics plan.
+
+

docs-ng/source/next/user/devices.rst

@@ -0,0 +1,6 @@
+Postprocessing
+==============
+
+Readout mitigation, metrics, IO helpers.
+
+