diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc
index 05f966e5e6..3bf7f2f029 100644
--- a/flow/designs/asap7/aes-block/constraint.sdc
+++ b/flow/designs/asap7/aes-block/constraint.sdc
@@ -1,13 +1,12 @@
 set clk_name clk
 set clk_port_name clk
 set clk_period 450
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input/output_delay = 0.2 * clk_period budget, as
+# optimization targets only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.8 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.6 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json
index f727c2d2bf..7de3cf60f4 100644
--- a/flow/designs/asap7/aes-block/rules-base.json
+++ b/flow/designs/asap7/aes-block/rules-base.json
@@ -28,19 +28,19 @@
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -78.0,
+        "value": -113.0,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -4840.0,
+        "value": -7390.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
-        "value": -52.3,
+        "value": -22.5,
         "compare": ">="
     },
     "cts__timing__hold__tns": {
-        "value": -6310.0,
+        "value": -90.0,
         "compare": ">="
     },
     "globalroute__antenna_diodes_count": {
@@ -52,19 +52,19 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -3660.0,
+        "value": -6000.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
-        "value": -25.9,
+        "value": -22.5,
         "compare": ">="
     },
     "globalroute__timing__hold__tns": {
-        "value": -1080.0,
+        "value": -90.0,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 51873,
+        "value": 49870,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -80,11 +80,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -94.0,
+        "value": -91.5,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -1470.0,
+        "value": -2720.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc
index fd7d806652..09b55083d9 100644
--- a/flow/designs/asap7/aes-mbff/constraint.sdc
+++ b/flow/designs/asap7/aes-mbff/constraint.sdc
@@ -1,13 +1,12 @@
 set clk_name clk
 set clk_port_name clk
 set clk_period 380
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input/output_delay = 0.2 * clk_period budget, as
+# optimization targets only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.8 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.6 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json
index 08c173c711..ecf9d33269 100644
--- a/flow/designs/asap7/aes-mbff/rules-base.json
+++ b/flow/designs/asap7/aes-mbff/rules-base.json
@@ -8,7 +8,7 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 2103,
+        "value": 2087,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -28,11 +28,11 @@
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -28.8,
+        "value": -26.6,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -164.0,
+        "value": -146.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -48,11 +48,11 @@
         "compare": "<="
     },
     "globalroute__timing__setup__ws": {
-        "value": -41.3,
+        "value": -37.1,
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -1010.0,
+        "value": -622.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -84,7 +84,7 @@
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -235.0,
+        "value": -185.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
@@ -96,7 +96,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 2206,
+        "value": 2180,
         "compare": "<="
     }
 }
\ No newline at end of file
diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc
index c55ecb8cf6..68227cb969 100644
--- a/flow/designs/asap7/aes_lvt/constraint.sdc
+++ b/flow/designs/asap7/aes_lvt/constraint.sdc
@@ -1,13 +1,12 @@
 set clk_name clk
 set clk_port_name clk
 set clk_period 360
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input/output_delay = 0.2 * clk_period budget, as
+# optimization targets only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.8 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.6 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json
index 2fb6b362f8..d1bbe54595 100644
--- a/flow/designs/asap7/aes_lvt/rules-base.json
+++ b/flow/designs/asap7/aes_lvt/rules-base.json
@@ -1,6 +1,6 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 1910.0,
+        "value": 1780.0,
         "compare": "<="
     },
     "constraints__clocks__count": {
@@ -8,11 +8,11 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 1954,
+        "value": 1818,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 17740,
+        "value": 17450,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -20,11 +20,11 @@
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 1543,
+        "value": 1517,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1543,
+        "value": 1517,
         "compare": "<="
     },
     "cts__timing__setup__ws": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 68956,
+        "value": 65052,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -80,11 +80,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -18.0,
+        "value": -46.8,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -72.0,
+        "value": -219.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
@@ -96,7 +96,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 1992,
+        "value": 1846,
         "compare": "<="
     }
 }
\ No newline at end of file
diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
index 063b06987a..59a02fa15c 100644
--- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
+++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc
@@ -3,15 +3,14 @@ current_design jpeg_encoder
 set clk_name clk
 set clk_port_name clk
 set clk_period 680
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input/output_delay = 0.2 * clk_period budget, as
+# optimization targets only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.8 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.6 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
 
 set_max_fanout 10 [current_design]
diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
index aea1920f55..3fef65b618 100644
--- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
+++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc
@@ -3,13 +3,12 @@ current_design jpeg_encoder
 set clk_name clk
 set clk_port_name clk
 set clk_period 600
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input/output_delay = 0.2 * clk_period budget, as
+# optimization targets only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.8 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.6 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc
index f5a7e5d92d..f0cd3bd6ef 100644
--- a/flow/designs/asap7/mock-alu/constraints.sdc
+++ b/flow/designs/asap7/mock-alu/constraints.sdc
@@ -1,16 +1,16 @@
 set clk_name clock
 set clk_port_name clock
 set clk_period 300
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input_delay = 0.7 * clk_period (tight, stress-test)
+# and set_output_delay = 0.2 * clk_period budgets, as optimization targets
+# only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.3 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.1 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
 
 set output_regs [get_cells *io_out_REG*]
 if { [llength $output_regs] == 0 } {
diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json
index fa18407f83..47563e2724 100644
--- a/flow/designs/asap7/mock-alu/rules-base.json
+++ b/flow/designs/asap7/mock-alu/rules-base.json
@@ -28,11 +28,11 @@
         "compare": "<="
     },
     "cts__timing__setup__ws": {
-        "value": -308.0,
+        "value": -289.0,
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -14100.0,
+        "value": -18200.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -48,11 +48,11 @@
         "compare": "<="
     },
     "globalroute__timing__setup__ws": {
-        "value": -321.0,
+        "value": -309.0,
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -18100.0,
+        "value": -20700.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -80,11 +80,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -303.0,
+        "value": -292.0,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -15700.0,
+        "value": -18500.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc
index 99e95e8e24..a3eb1dd11a 100644
--- a/flow/designs/asap7/swerv_wrapper/constraint.sdc
+++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc
@@ -3,13 +3,12 @@ current_design swerv_wrapper
 set clk_name core_clock
 set clk_port_name clk
 set clk_period 1600
-set clk_io_pct 0.2
 
-set clk_port [get_ports $clk_port_name]
+# Match the old set_input/output_delay = 0.2 * clk_period budget, as
+# optimization targets only (no set_input/output_delay — see rationale in
+# $PLATFORM_DIR/constraints.sdc).
+set in2reg_max [expr { $clk_period * 0.8 }]
+set reg2out_max [expr { $clk_period * 0.8 }]
+set in2out_max [expr { $clk_period * 0.6 }]
 
-create_clock -name $clk_name -period $clk_period $clk_port
-
-set non_clock_inputs [all_inputs -no_clocks]
-
-set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
-set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+source $::env(PLATFORM_DIR)/constraints.sdc
diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json
index 037a9c707e..f1bb7eda4a 100644
--- a/flow/designs/asap7/swerv_wrapper/rules-base.json
+++ b/flow/designs/asap7/swerv_wrapper/rules-base.json
@@ -8,11 +8,11 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 54990,
+        "value": 54984,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 155444,
+        "value": 155394,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -20,11 +20,11 @@
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 13517,
+        "value": 13512,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 13517,
+        "value": 13512,
         "compare": "<="
     },
     "cts__timing__setup__ws": {
@@ -64,7 +64,7 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 1288494,
+        "value": 1287970,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -80,19 +80,19 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -142.0,
+        "value": -80.0,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -2390.0,
+        "value": -320.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {
-        "value": -134.0,
+        "value": -89.0,
         "compare": ">="
     },
     "finish__timing__hold__tns": {
-        "value": -17100.0,
+        "value": -338.0,
         "compare": ">="
     },
     "finish__design__instance__area": {