From 0dfc20b5defcb0969dd0a80c9b8dae4765814ea8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Tue, 21 Apr 2026 10:32:05 +0200 Subject: [PATCH 1/4] asap7: drop fictitious set_input/output_delay from single-clock macro SDCs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These designs are macros — blocks instantiated inside a larger SoC, not chips with real IO pads. set_input_delay / set_output_delay at a macro boundary picks a fraction of the clock period as a "budget" against the clock insertion point, but macro insertion latency is not known until SoC integration. The budget is fabricated. repair_timing -hold interprets the fabricated budget as a real hold requirement and inserts hold buffers to fix phantom violations. From PR 4159 CI (metric cts__design__instance__count__hold_buffer): aes-block 723 hold buffers + 3 unfixed hold violations (7.4% of the design is hold buffers and it still does not close: finish hold TNS = -1.53 ns) swerv_wrapper 0 hold buffers, but 102 unfixed hold violations, finish hold TNS = -337 ns — repair gave up entirely jpeg_lvt 96 aes-mbff 94 aes_lvt 89 jpeg 80 mock-alu 0 (clean, but the anti-pattern is still present) The asap7 platform already ships the correct macro template in flow/platforms/asap7/constraints.sdc (rationale at lines 45-56): set_max_delay -ignore_clock_latency as an optimization target, no IO delay, and by construction no hold path at the macro boundary. The SoC integrator owns the boundary. Switch these single-clock designs to source that template — the same idiom already used by riscv32i-mock-sram/fakeram7_256x32/constraints.sdc. Pass explicit in2reg_max / reg2out_max / in2out_max to preserve the old implicit setup budget (0.8 * clk_period for in2reg and reg2out, 0.6 * clk_period for in2out), rather than the template's 80 ps default which is too aggressive for the 360–1600 ps clock periods used here. Results (cts__design__instance__count__hold_buffer → 0 unless noted; finish__timing__drv__hold_violation_count): aes-block 723 → 0 3 → 0 hold violations finish setup WS -71 ps → -27 ps (better) finish setup TNS -1384 ps → -711 ps (better) swerv_wrapper 0 → 0 102 → 5 hold violations finish hold TNS -337 ns → -18 ps (18000x better) finish setup closes (WS +37 ps, TNS 0) jpeg 80 → 0 setup closes (WS +22 ps, TNS 0) jpeg_lvt 96 → 0 setup WS +15 → +23 ps (better) aes_lvt 89 → 0 hold WS 13 → 27 ps aes-mbff 94 → 152 (internal reg-reg, not boundary) finish setup WS -2.5 → -1.4 ps (better) mock-alu 0 → 0 (stress-test design, no change) Regenerate rules-base.json for each affected design via \`make update_rules_force\` so the regression thresholds reflect the new metrics. All 25 per-design rules pass on every affected design. Out of scope (follow-up passes): - cva6: set_input/output_delay already commented out in its SDC; the 429 hold buffers come from real fakeram7 SRAM timing, not a fabricated boundary budget. - ethmac_lvt: multi-clock (three async clocks wb_clk_i, mtx_clk_pad_i, mrx_clk_pad_i); can't source the single-clock platform template. Co-Authored-By: Claude Opus 4.7 (1M context) Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/constraint.sdc | 15 ++++---- flow/designs/asap7/aes-block/rules-base.json | 34 +++++++++---------- flow/designs/asap7/aes-mbff/constraint.sdc | 15 ++++---- flow/designs/asap7/aes-mbff/rules-base.json | 26 +++++++------- flow/designs/asap7/aes_lvt/constraint.sdc | 15 ++++---- flow/designs/asap7/aes_lvt/rules-base.json | 18 +++++----- .../designs/asap7/jpeg/jpeg_encoder15_7nm.sdc | 15 ++++---- flow/designs/asap7/jpeg/rules-base.json | 14 ++++---- .../asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc | 15 ++++---- flow/designs/asap7/jpeg_lvt/rules-base.json | 14 ++++---- flow/designs/asap7/mock-alu/constraints.sdc | 16 ++++----- flow/designs/asap7/mock-alu/rules-base.json | 24 ++++++------- .../asap7/swerv_wrapper/constraint.sdc | 15 ++++---- .../asap7/swerv_wrapper/rules-base.json | 20 +++++------ 14 files changed, 125 insertions(+), 131 deletions(-) diff --git a/flow/designs/asap7/aes-block/constraint.sdc b/flow/designs/asap7/aes-block/constraint.sdc index 05f966e5e6..3bf7f2f029 100644 --- a/flow/designs/asap7/aes-block/constraint.sdc +++ b/flow/designs/asap7/aes-block/constraint.sdc @@ -1,13 +1,12 @@ set clk_name clk set clk_port_name clk set clk_period 450 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input/output_delay = 0.2 * clk_period budget, as +# optimization targets only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index f727c2d2bf..1e53a4bc37 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 2010.0, + "value": 1930.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7139, + "value": 6700, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 9621, + "value": 10206, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,27 +20,27 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 837, + "value": 888, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 837, + "value": 888, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -78.0, + "value": -83.3, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -4840.0, + "value": -2570.0, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -52.3, + "value": -22.5, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -6310.0, + "value": -90.0, "compare": ">=" }, "globalroute__antenna_diodes_count": { @@ -48,23 +48,23 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -125.0, + "value": -79.3, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -3660.0, + "value": -2300.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -25.9, + "value": -22.5, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -1080.0, + "value": -90.0, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 51873, + "value": 50680, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -94.0, + "value": -49.5, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -1470.0, + "value": -801.0, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7205, + "value": 6750, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes-mbff/constraint.sdc b/flow/designs/asap7/aes-mbff/constraint.sdc index fd7d806652..09b55083d9 100644 --- a/flow/designs/asap7/aes-mbff/constraint.sdc +++ b/flow/designs/asap7/aes-mbff/constraint.sdc @@ -1,13 +1,12 @@ set clk_name clk set clk_port_name clk set clk_period 380 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input/output_delay = 0.2 * clk_period budget, as +# optimization targets only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index 08c173c711..8a9b41759f 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1900.0, + "value": 1780.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 2103, + "value": 1909, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 19594, + "value": 18274, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1704, + "value": 1589, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1704, + "value": 1589, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -28.8, + "value": -26.2, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -164.0, + "value": -96.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -48,11 +48,11 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -41.3, + "value": -31.4, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -1010.0, + "value": -259.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 74169, + "value": 69613, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -31.8, + "value": -20.4, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -235.0, + "value": -79.4, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 2206, + "value": 1966, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes_lvt/constraint.sdc b/flow/designs/asap7/aes_lvt/constraint.sdc index c55ecb8cf6..68227cb969 100644 --- a/flow/designs/asap7/aes_lvt/constraint.sdc +++ b/flow/designs/asap7/aes_lvt/constraint.sdc @@ -1,13 +1,12 @@ set clk_name clk set clk_port_name clk set clk_period 360 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input/output_delay = 0.2 * clk_period budget, as +# optimization targets only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/asap7/aes_lvt/rules-base.json b/flow/designs/asap7/aes_lvt/rules-base.json index 2fb6b362f8..d1bbe54595 100644 --- a/flow/designs/asap7/aes_lvt/rules-base.json +++ b/flow/designs/asap7/aes_lvt/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1910.0, + "value": 1780.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 1954, + "value": 1818, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 17740, + "value": 17450, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1543, + "value": 1517, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1543, + "value": 1517, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 68956, + "value": 65052, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -18.0, + "value": -46.8, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -72.0, + "value": -219.0, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 1992, + "value": 1846, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc index 063b06987a..59a02fa15c 100644 --- a/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg/jpeg_encoder15_7nm.sdc @@ -3,15 +3,14 @@ current_design jpeg_encoder set clk_name clk set clk_port_name clk set clk_period 680 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input/output_delay = 0.2 * clk_period budget, as +# optimization targets only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc set_max_fanout 10 [current_design] diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json index bbcd2221de..b4bddc6931 100644 --- a/flow/designs/asap7/jpeg/rules-base.json +++ b/flow/designs/asap7/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 7008.24, + "value": 7350.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7105, + "value": 7430, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 63593, + "value": 70302, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5530, + "value": 6113, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5530, + "value": 6113, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 172630, + "value": 177906, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7253, + "value": 7599, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc index aea1920f55..3fef65b618 100644 --- a/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc +++ b/flow/designs/asap7/jpeg_lvt/jpeg_encoder15_7nm.sdc @@ -3,13 +3,12 @@ current_design jpeg_encoder set clk_name clk set clk_port_name clk set clk_period 600 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input/output_delay = 0.2 * clk_period budget, as +# optimization targets only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json index 5304309a43..8bca2988e8 100644 --- a/flow/designs/asap7/jpeg_lvt/rules-base.json +++ b/flow/designs/asap7/jpeg_lvt/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 7047.572508, + "value": 7390.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7019, + "value": 7352, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 64302, + "value": 70502, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 5592, + "value": 6131, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 5592, + "value": 6131, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 176948, + "value": 182177, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7124, + "value": 7520, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-alu/constraints.sdc b/flow/designs/asap7/mock-alu/constraints.sdc index f5a7e5d92d..f0cd3bd6ef 100644 --- a/flow/designs/asap7/mock-alu/constraints.sdc +++ b/flow/designs/asap7/mock-alu/constraints.sdc @@ -1,16 +1,16 @@ set clk_name clock set clk_port_name clock set clk_period 300 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input_delay = 0.7 * clk_period (tight, stress-test) +# and set_output_delay = 0.2 * clk_period budgets, as optimization targets +# only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.3 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.1 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc set output_regs [get_cells *io_out_REG*] if { [llength $output_regs] == 0 } { diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json index fa18407f83..48008054b6 100644 --- a/flow/designs/asap7/mock-alu/rules-base.json +++ b/flow/designs/asap7/mock-alu/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 1790, + "value": 1793, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 14790, + "value": 15125, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1286, + "value": 1315, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1286, + "value": 1315, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -308.0, + "value": -302.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -14100.0, + "value": -16800.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -48,11 +48,11 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -321.0, + "value": -319.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -18100.0, + "value": -18500.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 50078, + "value": 54688, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -303.0, + "value": -300.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -15700.0, + "value": -16600.0, "compare": ">=" }, "finish__timing__hold__ws": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 1858, + "value": 1876, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index 99e95e8e24..a3eb1dd11a 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -3,13 +3,12 @@ current_design swerv_wrapper set clk_name core_clock set clk_port_name clk set clk_period 1600 -set clk_io_pct 0.2 -set clk_port [get_ports $clk_port_name] +# Match the old set_input/output_delay = 0.2 * clk_period budget, as +# optimization targets only (no set_input/output_delay — see rationale in +# $PLATFORM_DIR/constraints.sdc). +set in2reg_max [expr { $clk_period * 0.8 }] +set reg2out_max [expr { $clk_period * 0.8 }] +set in2out_max [expr { $clk_period * 0.6 }] -create_clock -name $clk_name -period $clk_period $clk_port - -set non_clock_inputs [all_inputs -no_clocks] - -set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs -set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs] +source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index 037a9c707e..61f29d7f23 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 54990, + "value": 54984, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 155444, + "value": 155394, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 13517, + "value": 13512, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 13517, + "value": 13512, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 1288494, + "value": 1287970, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,23 +80,23 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -142.0, + "value": -80.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -2390.0, + "value": -320.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -134.0, + "value": -89.0, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -17100.0, + "value": -338.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 55427, + "value": 55438, "compare": "<=" } } \ No newline at end of file From 0aba8ee5e52bc123901073ff63c1c620fc7f605b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Wed, 22 Apr 2026 10:52:48 +0200 Subject: [PATCH 2/4] asap7: refresh rules-base.json for aes-block and aes-mbff MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Regenerated via `make update_rules` after the recent SDC change in 0dfc20b5d (drop fictitious set_input/output_delay from single-clock macro SDCs), which loosened timing metrics for these two designs. Co-Authored-By: Claude Opus 4.7 (1M context) Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/rules-base.json | 14 +++++++------- flow/designs/asap7/aes-mbff/rules-base.json | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 1e53a4bc37..d075684521 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -83.3, + "value": -113.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -2570.0, + "value": -7390.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -48,11 +48,11 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -79.3, + "value": -137.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -2300.0, + "value": -6000.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 50680, + "value": 49870, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -49.5, + "value": -91.5, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -801.0, + "value": -2720.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index 8a9b41759f..0c12f4c981 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -259.0, + "value": -622.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -79.4, + "value": -185.0, "compare": ">=" }, "finish__timing__hold__ws": { From 29dc481ee3b04c511e070ffb4f47320cee4dddfc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Wed, 22 Apr 2026 16:40:20 +0200 Subject: [PATCH 3/4] asap7: regenerate rules-base.json via make update_ok MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previous rules for these designs were produced by `update_rules_force`, which rewrites every rule to metric+padding, regardless of whether the old rule still passes. `update_ok` (== `update_rules`, with --failing --tighten) only updates rules that are currently failing or that can be tightened — leaving untouched rules within the old rule's padding window, which keeps the diff minimal and avoids silently loosening rules that didn't need to move. Per-design result: - aes-block, aes-mbff, aes_lvt, mock-alu, swerv_wrapper: narrower diff than the force-update; only tightenings and failing fixes remain. - jpeg, jpeg_lvt: no rule changes needed — the original master rules still pass against the new metrics. All 25 per-design rules pass on every affected design. Co-Authored-By: Claude Opus 4.7 (1M context) Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/rules-base.json | 14 ++++++------ flow/designs/asap7/aes-mbff/rules-base.json | 22 +++++++++---------- flow/designs/asap7/jpeg/rules-base.json | 14 ++++++------ flow/designs/asap7/jpeg_lvt/rules-base.json | 14 ++++++------ flow/designs/asap7/mock-alu/rules-base.json | 12 +++++----- .../asap7/swerv_wrapper/rules-base.json | 2 +- 6 files changed, 39 insertions(+), 39 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index d075684521..7de3cf60f4 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1930.0, + "value": 2010.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 6700, + "value": 7139, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 10206, + "value": 9621, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 888, + "value": 837, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 888, + "value": 837, "compare": "<=" }, "cts__timing__setup__ws": { @@ -48,7 +48,7 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -137.0, + "value": -125.0, "compare": ">=" }, "globalroute__timing__setup__tns": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 6750, + "value": 7205, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index 0c12f4c981..ecf9d33269 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 1780.0, + "value": 1900.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 1909, + "value": 2087, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 18274, + "value": 19594, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,19 +20,19 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1589, + "value": 1704, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1589, + "value": 1704, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -26.2, + "value": -26.6, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -96.0, + "value": -146.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -48,7 +48,7 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -31.4, + "value": -37.1, "compare": ">=" }, "globalroute__timing__setup__tns": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 69613, + "value": 74169, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -80,7 +80,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -20.4, + "value": -31.8, "compare": ">=" }, "finish__timing__setup__tns": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 1966, + "value": 2180, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg/rules-base.json b/flow/designs/asap7/jpeg/rules-base.json index b4bddc6931..bbcd2221de 100644 --- a/flow/designs/asap7/jpeg/rules-base.json +++ b/flow/designs/asap7/jpeg/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 7350.0, + "value": 7008.24, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7430, + "value": 7105, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 70302, + "value": 63593, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6113, + "value": 5530, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6113, + "value": 5530, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 177906, + "value": 172630, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7599, + "value": 7253, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/jpeg_lvt/rules-base.json b/flow/designs/asap7/jpeg_lvt/rules-base.json index 8bca2988e8..5304309a43 100644 --- a/flow/designs/asap7/jpeg_lvt/rules-base.json +++ b/flow/designs/asap7/jpeg_lvt/rules-base.json @@ -1,6 +1,6 @@ { "synth__design__instance__area__stdcell": { - "value": 7390.0, + "value": 7047.572508, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 7352, + "value": 7019, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 70502, + "value": 64302, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 6131, + "value": 5592, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 6131, + "value": 5592, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 182177, + "value": 176948, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 7520, + "value": 7124, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json index 48008054b6..9b79b80aa4 100644 --- a/flow/designs/asap7/mock-alu/rules-base.json +++ b/flow/designs/asap7/mock-alu/rules-base.json @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 1793, + "value": 1790, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 15125, + "value": 14790, "compare": "<=" }, "detailedplace__design__violations": { @@ -20,11 +20,11 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 1315, + "value": 1286, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 1315, + "value": 1286, "compare": "<=" }, "cts__timing__setup__ws": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 54688, + "value": 50078, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 1876, + "value": 1858, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index 61f29d7f23..f1bb7eda4a 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -96,7 +96,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 55438, + "value": 55427, "compare": "<=" } } \ No newline at end of file From cd586bcd9e2183ef59173f4c2dc49bc8ddb3e63f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 23 Apr 2026 12:18:51 +0200 Subject: [PATCH 4/4] asap7: refresh rules-base.json for mock-alu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pulled metadata.json from Jenkins PR-4170-merge build #6 and ran `genRuleFile.py --failing --tighten` (the `make update_ok` logic) to resolve the failing CTS/globalroute/finish setup TNS checks. Signed-off-by: Øyvind Harboe --- flow/designs/asap7/mock-alu/rules-base.json | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/flow/designs/asap7/mock-alu/rules-base.json b/flow/designs/asap7/mock-alu/rules-base.json index 9b79b80aa4..47563e2724 100644 --- a/flow/designs/asap7/mock-alu/rules-base.json +++ b/flow/designs/asap7/mock-alu/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -302.0, + "value": -289.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -16800.0, + "value": -18200.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -48,11 +48,11 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -319.0, + "value": -309.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -18500.0, + "value": -20700.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -300.0, + "value": -292.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -16600.0, + "value": -18500.0, "compare": ">=" }, "finish__timing__hold__ws": {