diff --git a/.gitignore b/.gitignore index 47b9b47bc0f..e8709fddfe1 100644 --- a/.gitignore +++ b/.gitignore @@ -16,6 +16,7 @@ TAGS .~lock.*# .DS_Store Makefile +__pycache__ include/ord/Version.hh diff --git a/include/ord/Design.h b/include/ord/Design.h new file mode 100644 index 00000000000..7f1211bdb5f --- /dev/null +++ b/include/ord/Design.h @@ -0,0 +1,74 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// BSD 3-Clause License +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +/////////////////////////////////////////////////////////////////////////////// + +#pragma once + +#include + +namespace odb { +class dbBlock; +} // namespace odb + +namespace ifp { +class InitFloorplan; +} + +namespace ord { + +class Tech; + +class Design +{ + public: + Design(Tech* tech); + void readVerilog(const std::string& file_name); + void link(const std::string& design_name); + + void writeDb(const std::string& file_name); + void writeDef(const std::string& file_name); + + odb::dbBlock* getBlock(); + utl::Logger* getLogger(); + + int micronToDBU(double coord); + + // Services + ifp::InitFloorplan* getFloorplan(); + + private: + Tech* tech_; +}; + +} // namespace ord diff --git a/include/ord/Tech.h b/include/ord/Tech.h new file mode 100644 index 00000000000..da5bd994e88 --- /dev/null +++ b/include/ord/Tech.h @@ -0,0 +1,62 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// BSD 3-Clause License +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +/////////////////////////////////////////////////////////////////////////////// + +#pragma once + +#include + +namespace odb { +class dbDatabase; +} + +namespace utl { +class Logger; +} + +namespace ord { + +class Tech +{ + public: + Tech(); + void readLEF(const std::string& file_name); + void readLiberty(const std::string& file_name); + odb::dbDatabase* getDB(); + + private: + odb::dbDatabase* db_; +}; + +} // namespace ord diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index f42e127825e..0b5826a3479 100755 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -31,6 +31,8 @@ set(RESIZER_HOME ${PROJECT_SOURCE_DIR}/src/rsz) set(PAD_HOME ${OPENROAD_HOME}/src/pad) set(OPENROAD_SOURCE + Design.cc + Tech.cc OpenRoad.cc Main.cc ) @@ -324,10 +326,10 @@ if (Python3_FOUND AND BUILD_PYTHON) target_compile_definitions(openroad PRIVATE ENABLE_PYTHON3) swig_lib(NAME openroad_swig_py - NAMESPACE ord - LANGUAGE python - I_FILE OpenRoad-py.i - SCRIPTS ${CMAKE_CURRENT_BINARY_DIR}/openroad_swig_py.py + NAMESPACE ord + LANGUAGE python + I_FILE OpenRoad-py.i + SCRIPTS ${CMAKE_CURRENT_BINARY_DIR}/openroad_swig_py.py ) target_link_libraries(openroad_swig_py @@ -339,6 +341,7 @@ if (Python3_FOUND AND BUILD_PYTHON) target_link_libraries(openroad openroad_swig_py odbpy + ifp_py ) else() message(STATUS "Python3 disabled") diff --git a/src/Design.cc b/src/Design.cc new file mode 100644 index 00000000000..69f170d9621 --- /dev/null +++ b/src/Design.cc @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// BSD 3-Clause License +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +/////////////////////////////////////////////////////////////////////////////// + +#include "odb/db.h" +#include "ord/Design.h" +#include "ifp/InitFloorplan.hh" +#include "ord/OpenRoad.hh" +#include "ord/Tech.h" +#include "utl/Logger.h" + +namespace ord { + +Design::Design(Tech* tech) : tech_(tech) +{ +} + +odb::dbBlock* Design::getBlock() +{ + auto chip = tech_->getDB()->getChip(); + return chip ? chip->getBlock() : nullptr; +} + +void Design::readVerilog(const std::string& file_name) +{ + auto chip = tech_->getDB()->getChip(); + if (chip && chip->getBlock()) { + getLogger()->error(utl::ORD, 36, "A block already exists in the db"); + } + + auto app = OpenRoad::openRoad(); + app->readVerilog(file_name.c_str()); +} + +void Design::link(const std::string& design_name) +{ + auto app = OpenRoad::openRoad(); + app->linkDesign(design_name.c_str()); +} + +void Design::writeDb(const std::string& file_name) +{ + auto app = OpenRoad::openRoad(); + app->writeDb(file_name.c_str()); +} + +void Design::writeDef(const std::string& file_name) +{ + auto app = OpenRoad::openRoad(); + app->writeDef(file_name.c_str(), "5.8"); +} + +ifp::InitFloorplan* Design::getFloorplan() +{ + auto app = OpenRoad::openRoad(); + auto block = getBlock(); + if (!block) { + getLogger()->error(utl::ORD, 37, "No block loaded."); + } + return new ifp::InitFloorplan(block, app->getLogger(), app->getDbNetwork()); +} + +utl::Logger* Design::getLogger() +{ + auto app = OpenRoad::openRoad(); + return app->getLogger(); +} + +int Design::micronToDBU(double coord) +{ + int dbuPerMicron = getBlock()->getDbUnitsPerMicron(); + return round(coord * dbuPerMicron); +} + +} // namespace ord diff --git a/src/Main.cc b/src/Main.cc index dd7ef2ab178..8c3afbd321b 100755 --- a/src/Main.cc +++ b/src/Main.cc @@ -33,136 +33,163 @@ // /////////////////////////////////////////////////////////////////////////////// -#include +#include +#include +#include #include -#include #include -#include -#include +#include + +#include #include #include #include -#include // We have had too many problems with this std::filesytem on various platforms // so it is disabled but kept for future reference #ifdef USE_STD_FILESYSTEM #include #endif #ifdef ENABLE_READLINE - // If you get an error on this include be sure you have - // the package tcl-tclreadline-devel installed - #include +// If you get an error on this include be sure you have +// the package tcl-tclreadline-devel installed +#include #endif #ifdef ENABLE_PYTHON3 - #define PY_SSIZE_T_CLEAN - #include "Python.h" +#define PY_SSIZE_T_CLEAN +#include "Python.h" #endif #ifdef ENABLE_TCLX - #include +#include #endif -#include "sta/StringUtil.hh" -#include "sta/StaMain.hh" -#include "ord/Version.hh" +#include "gui/gui.h" #include "ord/InitOpenRoad.hh" #include "ord/OpenRoad.hh" +#include "ord/Version.hh" +#include "sta/StaMain.hh" +#include "sta/StringUtil.hh" #include "utl/Logger.h" -#include "gui/gui.h" -using std::string; -using sta::stringEq; using sta::findCmdLineFlag; using sta::findCmdLineKey; -using sta::sourceTclFile; using sta::is_regular_file; +using sta::sourceTclFile; +using sta::stringEq; +using std::string; #ifdef ENABLE_PYTHON3 -extern "C" -{ - extern PyObject* PyInit__openroad_swig_py(); - extern PyObject* PyInit__odbpy(); +extern "C" { +extern PyObject* PyInit__ifp_py(); +extern PyObject* PyInit__openroad_swig_py(); +extern PyObject* PyInit__odbpy(); } #endif int cmd_argc; -char **cmd_argv; +char** cmd_argv; const char* log_filename = nullptr; const char* metrics_filename = nullptr; -static const char *init_filename = ".openroad"; +static const char* init_filename = ".openroad"; -static void -showUsage(const char *prog, const char *init_filename); -static void -showSplash(); +static void showUsage(const char* prog, const char* init_filename); +static void showSplash(); #ifdef ENABLE_PYTHON3 namespace sta { -extern const char *odbpy_python_inits[]; -extern const char *openroad_swig_py_python_inits[]; -} +extern const char* ifp_py_python_inits[]; +extern const char* odbpy_python_inits[]; +extern const char* openroad_swig_py_python_inits[]; +} // namespace sta -static void -initPython() +static void initPython() { + if (PyImport_AppendInittab("_ifp_py", PyInit__ifp_py) == -1) { + fprintf(stderr, "Error: could not add module _ifp_py\n"); + exit(1); + } + if (PyImport_AppendInittab("_odbpy", PyInit__odbpy) == -1) { fprintf(stderr, "Error: could not add module odbpy\n"); exit(1); } - if (PyImport_AppendInittab("_openroad_swig_py", PyInit__openroad_swig_py) == -1) { + if (PyImport_AppendInittab("_openroad_swig_py", PyInit__openroad_swig_py) + == -1) { fprintf(stderr, "Error: could not add module openroadpy\n"); exit(1); } Py_Initialize(); - char *unencoded = sta::unencode(sta::odbpy_python_inits); + { + char* unencoded = sta::unencode(sta::ifp_py_python_inits); - PyObject* odb_code = Py_CompileString(unencoded, "odbpy.py", Py_file_input); - if (odb_code == nullptr) { - PyErr_Print(); - fprintf(stderr, "Error: could not compile odbpy\n"); - exit(1); - } + PyObject* code = Py_CompileString(unencoded, "ifp_py.py", Py_file_input); + if (code == nullptr) { + PyErr_Print(); + fprintf(stderr, "Error: could not compile ifp_py\n"); + exit(1); + } - if (PyImport_ExecCodeModule("odb", odb_code) == nullptr) { - PyErr_Print(); - fprintf(stderr, "Error: could not add module odb\n"); - exit(1); + if (PyImport_ExecCodeModule("ifp", code) == nullptr) { + PyErr_Print(); + fprintf(stderr, "Error: could not add module ifp\n"); + exit(1); + } + + delete[] unencoded; } - delete [] unencoded; + { + char* unencoded = sta::unencode(sta::odbpy_python_inits); - unencoded = sta::unencode(sta::openroad_swig_py_python_inits); + PyObject* code = Py_CompileString(unencoded, "odbpy.py", Py_file_input); + if (code == nullptr) { + PyErr_Print(); + fprintf(stderr, "Error: could not compile odbpy\n"); + exit(1); + } - PyObject* ord_code = Py_CompileString(unencoded, "openroad.py", Py_file_input); - if (ord_code == nullptr) { - PyErr_Print(); - fprintf(stderr, "Error: could not compile openroad.py\n"); - exit(1); - } + if (PyImport_ExecCodeModule("odb", code) == nullptr) { + PyErr_Print(); + fprintf(stderr, "Error: could not add module odb\n"); + exit(1); + } - if (PyImport_ExecCodeModule("openroad", ord_code) == nullptr) { - PyErr_Print(); - fprintf(stderr, "Error: could not add module openroad\n"); - exit(1); + delete[] unencoded; } - delete [] unencoded; + { + char* unencoded = sta::unencode(sta::openroad_swig_py_python_inits); + + PyObject* code = Py_CompileString(unencoded, "openroad.py", Py_file_input); + if (code == nullptr) { + PyErr_Print(); + fprintf(stderr, "Error: could not compile openroad.py\n"); + exit(1); + } + + if (PyImport_ExecCodeModule("openroad", code) == nullptr) { + PyErr_Print(); + fprintf(stderr, "Error: could not add module openroad\n"); + exit(1); + } + + delete[] unencoded; + } } #endif -static void handler(int) { +static void handler(int) +{ std::cerr << "Stack trace:\n"; std::cerr << boost::stacktrace::stacktrace(); exit(1); } -int -main(int argc, - char *argv[]) +int main(int argc, char* argv[]) { // This avoids problems with locale setting dependent // C functions like strtod (e.g. 0.5 vs 0,5). @@ -213,17 +240,52 @@ main(int argc, showSplash(); } - std::vector args; - for(int i = 0; i < cmd_argc; i++) { - size_t sz = strlen(cmd_argv[i]); - args.push_back(new wchar_t[sz+1]); - args[i][sz] = '\0'; - for(size_t j = 0;j < sz; j++) { - args[i][j] = (wchar_t) cmd_argv[i][j]; + utl::Logger* logger = ord::OpenRoad::openRoad()->getLogger(); + if (findCmdLineFlag(cmd_argc, cmd_argv, "-gui")) { + logger->warn(utl::ORD, 38, "-gui is not yet supported with -python"); + } + + if (!findCmdLineFlag(cmd_argc, cmd_argv, "-no_init")) { + logger->warn(utl::ORD, 39, ".openroad ignored with -python"); + } + + const char* threads = findCmdLineKey(cmd_argc, cmd_argv, "-threads"); + if (threads) { + ord::OpenRoad::openRoad()->setThreadCount(threads); + } else { + // set to default number of threads + ord::OpenRoad::openRoad()->setThreadCount( + ord::OpenRoad::openRoad()->getThreadCount(), false); + } + + bool exit_after_cmd_file = findCmdLineFlag(cmd_argc, cmd_argv, "-exit"); + if (cmd_argc > 2 || (cmd_argc > 1 && cmd_argv[1][0] == '-')) { + showUsage(cmd_argv[0], init_filename); + } else if (cmd_argc == 2) { + char* cmd_filename = cmd_argv[1]; + FILE* cmd_file = fopen(cmd_filename, "r"); + if (cmd_file) { + wchar_t* arg = Py_DecodeLocale(cmd_filename, nullptr); + PySys_SetArgv(1, &arg); + PyMem_RawFree(arg); + int result = PyRun_SimpleFile(cmd_file, cmd_filename); + fclose(cmd_file); + if (exit_after_cmd_file) { + int exit_code = (result == 0) ? EXIT_SUCCESS : EXIT_FAILURE; + exit(exit_code); + } } } - return Py_Main(cmd_argc, args.data()); + std::vector args; + size_t sz = strlen(cmd_argv[0]); + args.push_back(new wchar_t[sz + 1]); + args[0][sz] = '\0'; + for (size_t j = 0; j < sz; j++) { + args[0][j] = (wchar_t) cmd_argv[0][j]; + } + + return Py_Main(1, args.data()); } else { // Python wants to install its own SIGINT handler to print KeyboardInterrupt // on ctrl-C. We don't want that if python is not the main interpreter. @@ -239,18 +301,16 @@ main(int argc, } #ifdef ENABLE_READLINE -static int -tclReadlineInit(Tcl_Interp *interp) +static int tclReadlineInit(Tcl_Interp* interp) { - std::array readline_cmds = { - "history event", - "eval $auto_index(::tclreadline::ScriptCompleter)", - "::tclreadline::readline builtincompleter true", - "::tclreadline::readline customcompleter ::tclreadline::ScriptCompleter", - "proc ::tclreadline::prompt1 {} { return \"openroad> \" }", - "proc ::tclreadline::prompt2 {} { return \"...> \" }", - "::tclreadline::Loop" - }; + std::array readline_cmds = { + "history event", + "eval $auto_index(::tclreadline::ScriptCompleter)", + "::tclreadline::readline builtincompleter true", + "::tclreadline::readline customcompleter ::tclreadline::ScriptCompleter", + "proc ::tclreadline::prompt1 {} { return \"openroad> \" }", + "proc ::tclreadline::prompt2 {} { return \"...> \" }", + "::tclreadline::Loop"}; for (auto cmd : readline_cmds) { if (TCL_ERROR == Tcl_Eval(interp, cmd)) { @@ -262,18 +322,19 @@ tclReadlineInit(Tcl_Interp *interp) #endif // Tcl init executed inside Tcl_Main. -static int -tclAppInit(int& argc, - char *argv[], - const char *init_filename, - Tcl_Interp *interp) +static int tclAppInit(int& argc, + char* argv[], + const char* init_filename, + Tcl_Interp* interp) { // first check if gui was requested and launch. // gui will call this function again as part of setup // ensuring the else {} will be utilized to initialize tcl and OR. if (findCmdLineFlag(argc, argv, "-gui")) { - // gobble up remaining -gui flags if present, since this could result in second invocation of the GUI - while (findCmdLineFlag(argc, argv, "-gui")); + // gobble up remaining -gui flags if present, since this could result in + // second invocation of the GUI + while (findCmdLineFlag(argc, argv, "-gui")) + ; gui::startGui(argc, argv, interp); } else { @@ -290,7 +351,8 @@ tclAppInit(int& argc, if (Tclreadline_Init(interp) == TCL_ERROR) { return TCL_ERROR; } - Tcl_StaticPackage(interp, "tclreadline", Tclreadline_Init, Tclreadline_SafeInit); + Tcl_StaticPackage( + interp, "tclreadline", Tclreadline_Init, Tclreadline_SafeInit); if (Tcl_EvalFile(interp, TCLRL_LIBRARY "/tclreadlineInit.tcl") != TCL_OK) { printf("Failed to load tclreadline\n"); } @@ -307,7 +369,8 @@ tclAppInit(int& argc, ord::OpenRoad::openRoad()->setThreadCount(threads); } else { // set to default number of threads - ord::OpenRoad::openRoad()->setThreadCount(ord::OpenRoad::openRoad()->getThreadCount(), false); + ord::OpenRoad::openRoad()->setThreadCount( + ord::OpenRoad::openRoad()->getThreadCount(), false); } bool exit_after_cmd_file = findCmdLineFlag(argc, argv, "-exit"); @@ -323,8 +386,10 @@ tclAppInit(int& argc, if (!gui_enabled) { sourceTclFile(init.c_str(), true, true, interp); } else { - // need to delay loading of file until after GUI is completed initialized - gui::Gui::get()->addRestoreStateCommand(fmt::format(restore_state_cmd, init.string())); + // need to delay loading of file until after GUI is completed + // initialized + gui::Gui::get()->addRestoreStateCommand( + fmt::format(restore_state_cmd, init.string())); } } #else @@ -335,8 +400,10 @@ tclAppInit(int& argc, if (!gui_enabled) { sourceTclFile(init_path.c_str(), true, true, interp); } else { - // need to delay loading of file until after GUI is completed initialized - gui::Gui::get()->addRestoreStateCommand(fmt::format(restore_state_cmd, init_path)); + // need to delay loading of file until after GUI is completed + // initialized + gui::Gui::get()->addRestoreStateCommand( + fmt::format(restore_state_cmd, init_path)); } } #endif @@ -344,10 +411,9 @@ tclAppInit(int& argc, if (argc > 2 || (argc > 1 && argv[1][0] == '-')) { showUsage(argv[0], init_filename); - } - else { + } else { if (argc == 2) { - char *cmd_file = argv[1]; + char* cmd_file = argv[1]; if (cmd_file) { if (!gui_enabled) { int result = sourceTclFile(cmd_file, false, false, interp); @@ -356,9 +422,11 @@ tclAppInit(int& argc, exit(exit_code); } } else { - // need to delay loading of file until after GUI is completed initialized + // need to delay loading of file until after GUI is completed + // initialized const char* restore_state_cmd = "source {{{}}}"; - gui::Gui::get()->addRestoreStateCommand(fmt::format(restore_state_cmd, cmd_file)); + gui::Gui::get()->addRestoreStateCommand( + fmt::format(restore_state_cmd, cmd_file)); if (exit_after_cmd_file) { gui::Gui::get()->addRestoreStateCommand("exit"); } @@ -375,15 +443,12 @@ tclAppInit(int& argc, return TCL_OK; } -int -ord::tclAppInit(Tcl_Interp *interp) +int ord::tclAppInit(Tcl_Interp* interp) { return tclAppInit(cmd_argc, cmd_argv, init_filename, interp); } - -static void -showUsage(const char *prog, const char *init_filename) +static void showUsage(const char* prog, const char* init_filename) { printf("Usage: %s [-help] [-version] [-no_init] [-exit] [-gui] ", prog); printf("[-threads count|max] [-log file_name] [-metrics file_name] "); @@ -403,14 +468,15 @@ showUsage(const char *prog, const char *init_filename) printf(" cmd_file source cmd_file\n"); } -static void -showSplash() +static void showSplash() { - utl::Logger *logger = ord::OpenRoad::openRoad()->getLogger(); + utl::Logger* logger = ord::OpenRoad::openRoad()->getLogger(); string sha = OPENROAD_GIT_DESCRIBE; - logger->report("OpenROAD {} {}", - OPENROAD_VERSION, - sha.c_str()); - logger->report("This program is licensed under the BSD-3 license. See the LICENSE file for details."); - logger->report("Components of this program may be licensed under more restrictive licenses which must be honored."); + logger->report("OpenROAD {} {}", OPENROAD_VERSION, sha.c_str()); + logger->report( + "This program is licensed under the BSD-3 license. See the LICENSE file " + "for details."); + logger->report( + "Components of this program may be licensed under more restrictive " + "licenses which must be honored."); } diff --git a/src/OpenRoad-py.i b/src/OpenRoad-py.i index bf8760236d9..33fc74ba400 100644 --- a/src/OpenRoad-py.i +++ b/src/OpenRoad-py.i @@ -33,9 +33,13 @@ // /////////////////////////////////////////////////////////////////////////////// +%include + %{ #include "odb/db.h" +#include "ord/Tech.h" +#include "ord/Design.h" using odb::dbDatabase; using odb::dbBlock; @@ -62,6 +66,11 @@ get_db_block(); %} +%include "ord/Tech.h" +%include "ord/Design.h" + +%newobject Design::getFloorplan(); + const char * openroad_version(); diff --git a/src/OpenRoad.tcl b/src/OpenRoad.tcl index 00356c8eb66..191214c6c5c 100644 --- a/src/OpenRoad.tcl +++ b/src/OpenRoad.tcl @@ -201,6 +201,14 @@ proc set_debug_level {args} { ord::set_debug_level $tool $group $level } +sta::define_cmd_args "suppress_message" { tool id } +proc suppress_message {args} { + sta::check_argc_eq2 "suppress_message" $args + lassign $args tool id + sta::check_integer "suppress_message_level" $id + utl::suppress_message $tool $id +} + sta::define_cmd_args "python" { args } proc python {args} { ord::python_cmd $args diff --git a/src/Tech.cc b/src/Tech.cc new file mode 100644 index 00000000000..e412e094ced --- /dev/null +++ b/src/Tech.cc @@ -0,0 +1,85 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// BSD 3-Clause License +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +/////////////////////////////////////////////////////////////////////////////// + +#include "db_sta/dbSta.hh" +#include "odb/db.h" +#include "odb/lefin.h" +#include "ord/OpenRoad.hh" +#include "ord/Tech.h" + +namespace ord { + +Tech::Tech() +{ + auto app = OpenRoad::openRoad(); + db_ = app->getDb(); +} + +odb::dbDatabase* Tech::getDB() +{ + return db_; +} + +void Tech::readLEF(const std::string& file_name) +{ + auto app = OpenRoad::openRoad(); + const bool make_tech = db_->getTech() == nullptr; + const bool make_library = true; + std::string lib_name = file_name; + + // Hacky but easier than dealing with stdc++fs linking + auto slash_pos = lib_name.find_last_of('/'); + if (slash_pos != std::string::npos) { + lib_name.erase(0, slash_pos + 1); + } + auto dot_pos = lib_name.find_last_of('.'); + if (dot_pos != std::string::npos) { + lib_name.erase(lib_name.begin() + dot_pos, lib_name.end()); + } + + app->readLef(file_name.c_str(), lib_name.c_str(), make_tech, make_library); +} + +void Tech::readLiberty(const std::string& file_name) +{ + auto sta = OpenRoad::openRoad()->getSta(); + // TODO: take corner & min/max args + sta->readLiberty(file_name.c_str(), + sta->cmdCorner(), + sta::MinMaxAll::all(), + true /* infer_latches */); +} + +} // namespace ord diff --git a/src/ant/test/check_api1.ok b/src/ant/test/check_api1.ok index 717bf283c77..d4399680f0b 100644 --- a/src/ant/test/check_api1.ok +++ b/src/ant/test/check_api1.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 30 technology vias [INFO ODB-0225] Created 387 library cells [INFO ODB-0226] Finished LEF file: merged_spacing.lef -[INFO ODB-0127] Reading DEF file: sw130_random.def [INFO ODB-0128] Design: gcd [INFO ODB-0131] Created 6 components and 48 component-terminals. [INFO ODB-0133] Created 2 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: sw130_random.def Net net50 output50/A (sky130_fd_sc_ms__buf_1) met2 diff --git a/src/ant/test/check_api1.tcl b/src/ant/test/check_api1.tcl index cbc49ec8085..da2cb788e3f 100644 --- a/src/ant/test/check_api1.tcl +++ b/src/ant/test/check_api1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # check_antennas tcl api commands read_lef merged_spacing.lef read_def sw130_random.def diff --git a/src/ant/test/check_drt1.ok b/src/ant/test/check_drt1.ok index e64072745e0..315debc5a0e 100644 --- a/src/ant/test/check_drt1.ok +++ b/src/ant/test/check_drt1.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 30 technology vias [INFO ODB-0225] Created 387 library cells [INFO ODB-0226] Finished LEF file: merged_spacing.lef -[INFO ODB-0127] Reading DEF file: sw130_random.def [INFO ODB-0128] Design: gcd [INFO ODB-0131] Created 6 components and 48 component-terminals. [INFO ODB-0133] Created 2 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: sw130_random.def Net net50 output50/A (sky130_fd_sc_ms__buf_1) met2 diff --git a/src/ant/test/check_drt1.tcl b/src/ant/test/check_drt1.tcl index fe97cfae56e..649c8da88cc 100644 --- a/src/ant/test/check_drt1.tcl +++ b/src/ant/test/check_drt1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # check_antennas detail routes read_lef merged_spacing.lef read_def sw130_random.def diff --git a/src/ant/test/check_grt1.ok b/src/ant/test/check_grt1.ok index 3ef82309c68..2c29b11cb1e 100644 --- a/src/ant/test/check_grt1.ok +++ b/src/ant/test/check_grt1.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1360 components and 6650 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130.def Net clk clkbuf_0_clk/A (sky130_fd_sc_hs__clkbuf_1) met2 diff --git a/src/ant/test/check_grt1.tcl b/src/ant/test/check_grt1.tcl index 6182813acf4..063a7f37941 100644 --- a/src/ant/test/check_grt1.tcl +++ b/src/ant/test/check_grt1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_antennas global route read_liberty "sky130hs/sky130hs_tt.lib" read_lef "sky130hs/sky130hs.tlef" diff --git a/src/cmake/swig_lib.cmake b/src/cmake/swig_lib.cmake index 8f171606240..85544632a04 100644 --- a/src/cmake/swig_lib.cmake +++ b/src/cmake/swig_lib.cmake @@ -66,6 +66,8 @@ function(swig_lib) PROPERTY SWIG_MODULE_NAME ${ARG_NAME}) set_property(SOURCE ${ARG_I_FILE} PROPERTY USE_SWIG_DEPENDENCIES TRUE) + set_property(SOURCE ${ARG_I_FILE} + PROPERTY USE_TARGET_INCLUDE_DIRECTORIES true) swig_add_library(${ARG_NAME} LANGUAGE ${ARG_LANGUAGE} @@ -74,7 +76,7 @@ function(swig_lib) ) # Disable problematic compiler warnings on generated files. - # At this point the only the swig generated sources are present. + # At this point only the swig generated sources are present. get_target_property(GEN_SRCS ${ARG_NAME} SOURCES) foreach(GEN_SRC ${GEN_SRCS}) diff --git a/src/cts/test/balance_levels.tcl b/src/cts/test/balance_levels.tcl index eaa7f2f30c5..c0e70d95b8a 100644 --- a/src/cts/test/balance_levels.tcl +++ b/src/cts/test/balance_levels.tcl @@ -1,4 +1,5 @@ source "helpers.tcl" +source "cts-helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/cts/test/check_buffers.ok b/src/cts/test/check_buffers.ok index 23b649ee7cf..c9ffe3281d4 100644 --- a/src/cts/test/check_buffers.ok +++ b/src/cts/test/check_buffers.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: check_buffers.def [INFO ODB-0128] Design: multi_sink [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 288 components and 1728 component-terminals. [INFO ODB-0133] Created 1 nets and 288 connections. -[INFO ODB-0134] Finished DEF file: check_buffers.def [INFO CTS-0049] Characterization buffer is: CLKBUF_X3. [INFO CTS-0039] Number of created patterns = 2376. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/check_charBuf.ok b/src/cts/test/check_charBuf.ok index cf7e65fbc27..6077b6bbe37 100644 --- a/src/cts/test/check_charBuf.ok +++ b/src/cts/test/check_charBuf.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: 16sinks.def [INFO ODB-0128] Design: test_16_sinks [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 16 components and 96 component-terminals. [INFO ODB-0133] Created 1 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: 16sinks.def [INFO CTS-0049] Characterization buffer is: BUF_X4. [INFO CTS-0039] Number of created patterns = 14256. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/check_charBuf.tcl b/src/cts/test/check_charBuf.tcl index 983a02183de..7bad4a73e79 100644 --- a/src/cts/test/check_charBuf.tcl +++ b/src/cts/test/check_charBuf.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib read_def "16sinks.def" diff --git a/src/cts/test/check_wire_rc_cts.ok b/src/cts/test/check_wire_rc_cts.ok index e8004832ade..81883c934bb 100644 --- a/src/cts/test/check_wire_rc_cts.ok +++ b/src/cts/test/check_wire_rc_cts.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: check_buffers.def [INFO ODB-0128] Design: multi_sink [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 288 components and 1728 component-terminals. [INFO ODB-0133] Created 1 nets and 288 connections. -[INFO ODB-0134] Finished DEF file: check_buffers.def [INFO CTS-0049] Characterization buffer is: CLKBUF_X3. [INFO CTS-0039] Number of created patterns = 11880. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/cts-helpers.tcl b/src/cts/test/cts-helpers.tcl new file mode 100644 index 00000000000..693aff568e4 --- /dev/null +++ b/src/cts/test/cts-helpers.tcl @@ -0,0 +1,64 @@ +# Helper functions common to multiple regressions. + +# Make an array of FF and connect all their clocks to a single +# top level terminal +proc make_array { sinks { width 200000 } { height 200000 } \ + { clock_gate -1 } } { + set db [ord::get_db] + set chip [odb::dbChip_create $db] + set block [odb::dbBlock_create $chip "multi_sink"] + set master [$db findMaster "DFF_X1"] + set tech [$db getTech] + set layer [$tech findLayer "metal6"] + set min_width [$layer getWidth] + + $block setDefUnits [$tech getDbUnitsPerMicron] + set rect [odb::Rect] + $rect init 0 0 $width $height + $block setDieArea $rect + + set clk [odb::dbNet_create $block "clk"] + set term [odb::dbBTerm_create $clk "clk"] + set pin [odb::dbBPin_create $term] + $pin setPlacementStatus FIRM + odb::dbBox_create $pin $layer \ + [expr ($width - $min_width) / 2] \ + [expr $height - $min_width] \ + [expr ($width + $min_width) / 2] \ + $height + + if {$clock_gate >= 0} { + set clock_master [$db findMaster "BUF_X1"] + set clock_gate_inst [odb::dbInst_create $block $clock_master "CKGATE"] + $clock_gate_inst setOrigin [expr $width / 2] [expr $height / 2] + $clock_gate_inst setPlacementStatus PLACED + [$clock_gate_inst findITerm "A"] connect $clk + + set clk2 [odb::dbNet_create $block "clk2"] + [$clock_gate_inst findITerm "Z"] connect $clk2 + } + + # Make instance array + set size [expr int(ceil(sqrt(${sinks})))] + set distance [expr $width / $size] + set limit $size + set i 0 + set j 0 + while {$i < $sinks} { + if {$i >= $limit} { + incr j + set limit [expr $limit + $size] + } + set inst [odb::dbInst_create $block $master "ff$i"] + $inst setOrigin [expr ${distance}/2 + (($i % $size) * $distance)] \ + [expr ${distance}/2 + ($j * $distance)] + $inst setPlacementStatus PLACED + if { $clock_gate >= 0 && $i >= $clock_gate } { + [$inst findITerm "CK"] connect $clk2 + } else { + [$inst findITerm "CK"] connect $clk + } + incr i + } + return $block +} diff --git a/src/cts/test/find_clock.ok b/src/cts/test/find_clock.ok index c4b89984b1d..025d39d4576 100644 --- a/src/cts/test/find_clock.ok +++ b/src/cts/test/find_clock.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: 16sinks.def [INFO ODB-0128] Design: test_16_sinks [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 16 components and 96 component-terminals. [INFO ODB-0133] Created 1 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: 16sinks.def [WARNING CTS-0104] Clock wire resistance/capacitance values are zero. Use set_wire_rc to set them. [INFO CTS-0049] Characterization buffer is: CLKBUF_X3. diff --git a/src/cts/test/find_clock.tcl b/src/cts/test/find_clock.tcl index 5c8478df7dc..6a9f3604619 100644 --- a/src/cts/test/find_clock.tcl +++ b/src/cts/test/find_clock.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib read_def "16sinks.def" diff --git a/src/cts/test/find_clock_pad.ok b/src/cts/test/find_clock_pad.ok index d1ec32e76ad..a71aa2f7809 100644 --- a/src/cts/test/find_clock_pad.ok +++ b/src/cts/test/find_clock_pad.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: find_clock_pad.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 4 components and 22 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 6 nets and 10 connections. -[INFO ODB-0134] Finished DEF file: find_clock_pad.def [INFO CTS-0049] Characterization buffer is: BUF_X1. [INFO CTS-0039] Number of created patterns = 4320. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/find_clock_pad.tcl b/src/cts/test/find_clock_pad.tcl index 3e7d834a4b7..93d6e5e2d52 100644 --- a/src/cts/test/find_clock_pad.tcl +++ b/src/cts/test/find_clock_pad.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" #Unit test to find clocks from pads. Also checks if the number of clocks found by TritonCTS is correct. #This unit test was created with the help of James Cherry. The script this test is based on can be found in dbSta/test. diff --git a/src/cts/test/helpers.tcl b/src/cts/test/helpers.tcl deleted file mode 100644 index 81dfa8107a9..00000000000 --- a/src/cts/test/helpers.tcl +++ /dev/null @@ -1,109 +0,0 @@ -# Helper functions common to multiple regressions. - -set test_dir [file dirname [file normalize [info script]]] -set result_dir [file join $test_dir "results"] - -proc make_result_file { filename } { - variable result_dir - return [file join $result_dir $filename] -} - -# puts [exec cat $file] without forking. -proc report_file { file } { - set stream [open $file r] - - while { [gets $stream line] >= 0 } { - puts $line - } - close $stream -} - -proc diff_files { file1 file2 } { - set stream1 [open $file1 r] - set stream2 [open $file2 r] - - set line 1 - set diff_line 0; - while { [gets $stream1 line1] >= 0 && [gets $stream2 line2] >= 0 } { - if { $line1 != $line2 } { - set diff_line $line - break - } - incr line - } - close $stream1 - close $stream2 - - if { $diff_line } { - puts "Differences found at line $diff_line." - puts "$line1" - puts "$line2" - return 1 - } else { - puts "No differences found." - return 0 - } -} - -# Make an array of FF and connect all their clocks to a single -# top level terminal -proc make_array { sinks { width 200000 } { height 200000 } \ - { clock_gate -1 } } { - set db [ord::get_db] - set chip [odb::dbChip_create $db] - set block [odb::dbBlock_create $chip "multi_sink"] - set master [$db findMaster "DFF_X1"] - set tech [$db getTech] - set layer [$tech findLayer "metal6"] - set min_width [$layer getWidth] - - $block setDefUnits [$tech getDbUnitsPerMicron] - set rect [odb::Rect] - $rect init 0 0 $width $height - $block setDieArea $rect - - set clk [odb::dbNet_create $block "clk"] - set term [odb::dbBTerm_create $clk "clk"] - set pin [odb::dbBPin_create $term] - $pin setPlacementStatus FIRM - odb::dbBox_create $pin $layer \ - [expr ($width - $min_width) / 2] \ - [expr $height - $min_width] \ - [expr ($width + $min_width) / 2] \ - $height - - if {$clock_gate >= 0} { - set clock_master [$db findMaster "BUF_X1"] - set clock_gate_inst [odb::dbInst_create $block $clock_master "CKGATE"] - $clock_gate_inst setOrigin [expr $width / 2] [expr $height / 2] - $clock_gate_inst setPlacementStatus PLACED - [$clock_gate_inst findITerm "A"] connect $clk - - set clk2 [odb::dbNet_create $block "clk2"] - [$clock_gate_inst findITerm "Z"] connect $clk2 - } - - # Make instance array - set size [expr int(ceil(sqrt(${sinks})))] - set distance [expr $width / $size] - set limit $size - set i 0 - set j 0 - while {$i < $sinks} { - if {$i >= $limit} { - incr j - set limit [expr $limit + $size] - } - set inst [odb::dbInst_create $block $master "ff$i"] - $inst setOrigin [expr ${distance}/2 + (($i % $size) * $distance)] \ - [expr ${distance}/2 + ($j * $distance)] - $inst setPlacementStatus PLACED - if { $clock_gate >= 0 && $i >= $clock_gate } { - [$inst findITerm "CK"] connect $clk2 - } else { - [$inst findITerm "CK"] connect $clk - } - incr i - } - return $block -} diff --git a/src/cts/test/helpers.tcl b/src/cts/test/helpers.tcl new file mode 120000 index 00000000000..509ca07b27e --- /dev/null +++ b/src/cts/test/helpers.tcl @@ -0,0 +1 @@ +../../../test/helpers.tcl \ No newline at end of file diff --git a/src/cts/test/max_cap.ok b/src/cts/test/max_cap.ok index 0ce03910a12..4f88afeb629 100644 --- a/src/cts/test/max_cap.ok +++ b/src/cts/test/max_cap.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: max_cap.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 21 components and 146 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 41 connections. -[INFO ODB-0134] Finished DEF file: max_cap.def [INFO CTS-0049] Characterization buffer is: sky130_fd_sc_hs__clkbuf_1. [INFO CTS-0039] Number of created patterns = 10440. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/max_cap.tcl b/src/cts/test/max_cap.tcl index 882214ae978..23f3ba7a478 100644 --- a/src/cts/test/max_cap.tcl +++ b/src/cts/test/max_cap.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # sky130hs liberty cap axis != max_capacitance -> max cap violations read_lef sky130hs/sky130hs.tlef read_lef sky130hs/sky130hs_std_cell.lef diff --git a/src/cts/test/no_clocks.ok b/src/cts/test/no_clocks.ok index 8a137bc588a..d1c17833821 100644 --- a/src/cts/test/no_clocks.ok +++ b/src/cts/test/no_clocks.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: no_clock.def [INFO ODB-0128] Design: test_no_clk [INFO ODB-0131] Created 2 components and 8 component-terminals. [INFO ODB-0133] Created 1 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: no_clock.def [INFO CTS-0049] Characterization buffer is: CLKBUF_X3. [INFO CTS-0039] Number of created patterns = 2376. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/no_clocks.tcl b/src/cts/test/no_clocks.tcl index fee7dab635e..4d60a502ffc 100644 --- a/src/cts/test/no_clocks.tcl +++ b/src/cts/test/no_clocks.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib read_def "no_clock.def" diff --git a/src/cts/test/no_sinks.ok b/src/cts/test/no_sinks.ok index 63bbb0bd97a..613c9c19d8a 100644 --- a/src/cts/test/no_sinks.ok +++ b/src/cts/test/no_sinks.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: no_sinks.def [INFO ODB-0128] Design: test_no_sinks [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 1 components and 6 component-terminals. [INFO ODB-0133] Created 1 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: no_sinks.def [INFO CTS-0049] Characterization buffer is: CLKBUF_X3. [INFO CTS-0039] Number of created patterns = 2376. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/no_sinks.tcl b/src/cts/test/no_sinks.tcl index ba0ae33cec4..58632b5577d 100644 --- a/src/cts/test/no_sinks.tcl +++ b/src/cts/test/no_sinks.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib read_def "no_sinks.def" diff --git a/src/cts/test/post_cts_opt.tcl b/src/cts/test/post_cts_opt.tcl index 417d6069bac..027c1d0449d 100644 --- a/src/cts/test/post_cts_opt.tcl +++ b/src/cts/test/post_cts_opt.tcl @@ -1,4 +1,5 @@ source "helpers.tcl" +source "cts-helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/cts/test/simple_test.ok b/src/cts/test/simple_test.ok index 676d82bf092..adb414e0b3e 100644 --- a/src/cts/test/simple_test.ok +++ b/src/cts/test/simple_test.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: 16sinks.def [INFO ODB-0128] Design: test_16_sinks [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 16 components and 96 component-terminals. [INFO ODB-0133] Created 1 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: 16sinks.def [INFO CTS-0049] Characterization buffer is: CLKBUF_X3. [INFO CTS-0039] Number of created patterns = 2376. [INFO CTS-0084] Compiling LUT. diff --git a/src/cts/test/simple_test.tcl b/src/cts/test/simple_test.tcl index 92550d85df3..b0e2c95c2ab 100644 --- a/src/cts/test/simple_test.tcl +++ b/src/cts/test/simple_test.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib read_def "16sinks.def" diff --git a/src/cts/test/simple_test_clustered.tcl b/src/cts/test/simple_test_clustered.tcl index cc630d98e4c..ee59aa3a026 100644 --- a/src/cts/test/simple_test_clustered.tcl +++ b/src/cts/test/simple_test_clustered.tcl @@ -1,4 +1,5 @@ source "helpers.tcl" +source "cts-helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/cts/test/simple_test_clustered_max_cap.tcl b/src/cts/test/simple_test_clustered_max_cap.tcl index 557d42dcc09..a16a263e7f3 100644 --- a/src/cts/test/simple_test_clustered_max_cap.tcl +++ b/src/cts/test/simple_test_clustered_max_cap.tcl @@ -1,4 +1,5 @@ source "helpers.tcl" +source "cts-helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/dbSta/test/block_sta1.ok b/src/dbSta/test/block_sta1.ok index 65de3025af7..6b59594b067 100644 --- a/src/dbSta/test/block_sta1.ok +++ b/src/dbSta/test/block_sta1.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: example1.lef -[INFO ODB-0127] Reading DEF file: example1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: example1.def Startpoint: r2 (rising edge-triggered flip-flop clocked by clk1) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk1) Path Group: clk1 diff --git a/src/dbSta/test/constant1.tcl b/src/dbSta/test/constant1.tcl index f53b7643d54..3f7e3df3dd3 100644 --- a/src/dbSta/test/constant1.tcl +++ b/src/dbSta/test/constant1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # constant propgation thru registers read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/dbSta/test/find_clks1.ok b/src/dbSta/test/find_clks1.ok index 05847d57de4..57ddf9ce8da 100644 --- a/src/dbSta/test/find_clks1.ok +++ b/src/dbSta/test/find_clks1.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: find_clks1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 4 components and 22 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 6 nets and 10 connections. -[INFO ODB-0134] Finished DEF file: find_clks1.def find_all_clk_nets: clk1 find_all_clk_nets: clk2 diff --git a/src/dbSta/test/find_clks1.tcl b/src/dbSta/test/find_clks1.tcl index c55f24b472d..49931ff2f31 100644 --- a/src/dbSta/test/find_clks1.tcl +++ b/src/dbSta/test/find_clks1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # findClkNets from input port thru pad read_lef Nangate45/Nangate45.lef read_lef pad.lef diff --git a/src/dbSta/test/find_clks2.ok b/src/dbSta/test/find_clks2.ok index 4002ac86016..ee3f268bfbc 100644 --- a/src/dbSta/test/find_clks2.ok +++ b/src/dbSta/test/find_clks2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: find_clks2.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 5 pins. [INFO ODB-0131] Created 8 components and 39 component-terminals. [INFO ODB-0132] Created 2 special nets and 16 connections. [INFO ODB-0133] Created 12 nets and 20 connections. -[INFO ODB-0134] Finished DEF file: find_clks2.def clk1 clk2 clk3 diff --git a/src/dbSta/test/find_clks2.tcl b/src/dbSta/test/find_clks2.tcl index c554155e58f..880580421d2 100644 --- a/src/dbSta/test/find_clks2.tcl +++ b/src/dbSta/test/find_clks2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # findClkNets(clock) read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/dbSta/test/network_edit1.ok b/src/dbSta/test/network_edit1.ok index c4570ee04d2..3833a316505 100644 --- a/src/dbSta/test/network_edit1.ok +++ b/src/dbSta/test/network_edit1.ok @@ -3,23 +3,19 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg3.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 8 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg3.def Net in1 [WARNING ODB-0173] warning: pin in1 skipped because it has no net No differences found. -[INFO ODB-0127] Reading DEF file: ./results/network_edit1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 8 nets and 13 connections. -[INFO ODB-0134] Finished DEF file: ./results/network_edit1.def [WARNING STA-0337] port 'in1' not found. Net in1 Load pins diff --git a/src/dbSta/test/power1.tcl b/src/dbSta/test/power1.tcl index da0118906ce..6b2b8b020a4 100644 --- a/src/dbSta/test/power1.tcl +++ b/src/dbSta/test/power1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # power for reg with sequential internal pins read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/dbSta/test/read_liberty1.tcl b/src/dbSta/test/read_liberty1.tcl index c599be7a52d..81cdab24afb 100644 --- a/src/dbSta/test/read_liberty1.tcl +++ b/src/dbSta/test/read_liberty1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # read_liberty port check read_lef read_liberty1.lef read_liberty read_liberty1.lib diff --git a/src/dbSta/test/read_verilog3.tcl b/src/dbSta/test/read_verilog3.tcl index d06c9600eeb..327e5d65c24 100644 --- a/src/dbSta/test/read_verilog3.tcl +++ b/src/dbSta/test/read_verilog3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # read_verilog 16b bus with lef/liberty read_lef bus1.lef read_liberty bus1.lib diff --git a/src/dbSta/test/read_verilog6.tcl b/src/dbSta/test/read_verilog6.tcl index 54144a7eeca..701cb94cdde 100644 --- a/src/dbSta/test/read_verilog6.tcl +++ b/src/dbSta/test/read_verilog6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # read_verilog missing liberty cell, missing lef and liberty cell read_lef Nangate45/Nangate45.lef # BUF_X10 diff --git a/src/dbSta/test/report_json1.ok b/src/dbSta/test/report_json1.ok index d3d47ee1fb4..1d758ac7129 100644 --- a/src/dbSta/test/report_json1.ok +++ b/src/dbSta/test/report_json1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg6.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 8 components and 39 component-terminals. [INFO ODB-0132] Created 2 special nets and 16 connections. [INFO ODB-0133] Created 10 nets and 20 connections. -[INFO ODB-0134] Finished DEF file: reg6.def { "path": [ { "pin": "r2/Q", diff --git a/src/dbSta/test/report_json1.tcl b/src/dbSta/test/report_json1.tcl index a6dd8244b06..9a15a8b16f1 100644 --- a/src/dbSta/test/report_json1.tcl +++ b/src/dbSta/test/report_json1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # report_path -format json read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/dbSta/test/sdc_get1.ok b/src/dbSta/test/sdc_get1.ok index cd5908aa972..0f555fe9f7e 100644 --- a/src/dbSta/test/sdc_get1.ok +++ b/src/dbSta/test/sdc_get1.ok @@ -2,12 +2,10 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: example1.lef -[INFO ODB-0127] Reading DEF file: example1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: example1.def clk1 r1/CK diff --git a/src/dbSta/test/sdc_get1.tcl b/src/dbSta/test/sdc_get1.tcl index 4b824c0251d..ef3f49f2754 100644 --- a/src/dbSta/test/sdc_get1.tcl +++ b/src/dbSta/test/sdc_get1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # sdc get_* read_lef example1.lef read_def example1.def diff --git a/src/dbSta/test/sdc_names1.ok b/src/dbSta/test/sdc_names1.ok index de6eb055a42..3607663bd39 100644 --- a/src/dbSta/test/sdc_names1.ok +++ b/src/dbSta/test/sdc_names1.ok @@ -2,12 +2,10 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: liberty1.lef -[INFO ODB-0127] Reading DEF file: hier1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 6 components and 26 component-terminals. [INFO ODB-0133] Created 5 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: hier1.def b1/r1 b1/r1 b1/u1 diff --git a/src/dbSta/test/sdc_names1.tcl b/src/dbSta/test/sdc_names1.tcl index 34683917a55..59b092ed90a 100644 --- a/src/dbSta/test/sdc_names1.tcl +++ b/src/dbSta/test/sdc_names1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # hierarchical names read_lef liberty1.lef read_def hier1.def diff --git a/src/dbSta/test/sdc_names2.ok b/src/dbSta/test/sdc_names2.ok index 002e235e733..c24bbf16c3b 100644 --- a/src/dbSta/test/sdc_names2.ok +++ b/src/dbSta/test/sdc_names2.ok @@ -2,12 +2,10 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: liberty1.lef -[INFO ODB-0127] Reading DEF file: sdc_names2.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: sdc_names2.def foo[0].bar[2].baz foo[0].bar[2].baz/A A -> Z combinational diff --git a/src/dbSta/test/sdc_names2.tcl b/src/dbSta/test/sdc_names2.tcl index 13d6f6692f1..040104315d3 100644 --- a/src/dbSta/test/sdc_names2.tcl +++ b/src/dbSta/test/sdc_names2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # get_cells/pins with brackets read_lef liberty1.lef read_liberty liberty1.lib diff --git a/src/dbSta/test/sta1.ok b/src/dbSta/test/sta1.ok index ea44019ee2b..938e430b40b 100644 --- a/src/dbSta/test/sta1.ok +++ b/src/dbSta/test/sta1.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: example1.lef -[INFO ODB-0127] Reading DEF file: example1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: example1.def Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/dbSta/test/sta1.tcl b/src/dbSta/test/sta1.tcl index 19fab6d538a..30b5147b7e7 100644 --- a/src/dbSta/test/sta1.tcl +++ b/src/dbSta/test/sta1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # lef/def reg1 read_lef example1.lef read_def example1.def diff --git a/src/dbSta/test/sta2.tcl b/src/dbSta/test/sta2.tcl index 526df2e4e56..cbf290a91d9 100644 --- a/src/dbSta/test/sta2.tcl +++ b/src/dbSta/test/sta2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # read_verilog, sdf read_liberty example1_slow.lib read_lef example1.lef diff --git a/src/dbSta/test/sta3.ok b/src/dbSta/test/sta3.ok index 48c6cfe60d7..5ff4e64f79c 100644 --- a/src/dbSta/test/sta3.ok +++ b/src/dbSta/test/sta3.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: example1.lef -[INFO ODB-0127] Reading DEF file: example1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: example1.def Startpoint: in1 (input port clocked by clk) Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/dbSta/test/sta3.tcl b/src/dbSta/test/sta3.tcl index a4a16058063..4a238460a99 100644 --- a/src/dbSta/test/sta3.tcl +++ b/src/dbSta/test/sta3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # min/max delay calc read_lef example1.lef read_liberty -min example1_fast.lib diff --git a/src/dbSta/test/sta4.ok b/src/dbSta/test/sta4.ok index 7d4aedf333a..a4121196bd0 100644 --- a/src/dbSta/test/sta4.ok +++ b/src/dbSta/test/sta4.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: example1.lef -[INFO ODB-0127] Reading DEF file: example1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: example1.def Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/dbSta/test/sta4.tcl b/src/dbSta/test/sta4.tcl index cd3fb821cbd..1a5ecf56a6f 100644 --- a/src/dbSta/test/sta4.tcl +++ b/src/dbSta/test/sta4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # delay calc example with parasitics read_lef example1.lef read_liberty example1_slow.lib diff --git a/src/dbSta/test/sta5.ok b/src/dbSta/test/sta5.ok index 8bac20ff1e3..bf76635b880 100644 --- a/src/dbSta/test/sta5.ok +++ b/src/dbSta/test/sta5.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: example1.lef -[INFO ODB-0127] Reading DEF file: example1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: example1.def Startpoint: in1 (input port clocked by clk) Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/dbSta/test/sta5.tcl b/src/dbSta/test/sta5.tcl index 6b25eb6b5c7..b99ae53d154 100644 --- a/src/dbSta/test/sta5.tcl +++ b/src/dbSta/test/sta5.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # 3 corners with +/- 10% derating example define_corners ss tt ff read_liberty -corner ss example1_slow.lib diff --git a/src/dbSta/test/write_verilog1.ok b/src/dbSta/test/write_verilog1.ok index 253e93260e5..28713ab399b 100644 --- a/src/dbSta/test/write_verilog1.ok +++ b/src/dbSta/test/write_verilog1.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: liberty1.lef -[INFO ODB-0127] Reading DEF file: reg1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg1.def module top (in1, in2, clk1, diff --git a/src/dbSta/test/write_verilog2.ok b/src/dbSta/test/write_verilog2.ok index f1d2d727cd3..6d9264d8e31 100644 --- a/src/dbSta/test/write_verilog2.ok +++ b/src/dbSta/test/write_verilog2.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: liberty1.lef -[INFO ODB-0127] Reading DEF file: reg4.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg4.def module reg1 (out, clk, in); diff --git a/src/dbSta/test/write_verilog3.ok b/src/dbSta/test/write_verilog3.ok index 08da0c60f5a..e14b38a64a4 100644 --- a/src/dbSta/test/write_verilog3.ok +++ b/src/dbSta/test/write_verilog3.ok @@ -4,12 +4,10 @@ [INFO ODB-0222] Reading LEF file: bus1.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: bus1.lef -[INFO ODB-0127] Reading DEF file: bus1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 9 pins. [INFO ODB-0131] Created 1 components and 11 component-terminals. [INFO ODB-0133] Created 9 nets and 9 connections. -[INFO ODB-0134] Finished DEF file: bus1.def module top (clk, in, out); diff --git a/src/dbSta/test/write_verilog4.ok b/src/dbSta/test/write_verilog4.ok index b2b055f1e5f..57e9fbbcdb9 100644 --- a/src/dbSta/test/write_verilog4.ok +++ b/src/dbSta/test/write_verilog4.ok @@ -2,13 +2,11 @@ [INFO ODB-0223] Created 2 technology layers [INFO ODB-0225] Created 6 library cells [INFO ODB-0226] Finished LEF file: liberty1.lef -[INFO ODB-0127] Reading DEF file: write_verilog4.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 24 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: write_verilog4.def module top (clk1, clk2, clk3, diff --git a/src/dbSta/test/write_verilog5.ok b/src/dbSta/test/write_verilog5.ok index 922b96d4797..cf4ebe4e42b 100644 --- a/src/dbSta/test/write_verilog5.ok +++ b/src/dbSta/test/write_verilog5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: write_verilog5.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: write_verilog5.def module top (in1, out1); input in1; diff --git a/src/dbSta/test/write_verilog6.ok b/src/dbSta/test/write_verilog6.ok index e56cb770b31..e9f538efbea 100644 --- a/src/dbSta/test/write_verilog6.ok +++ b/src/dbSta/test/write_verilog6.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: write_verilog5.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: write_verilog5.def module top (in1, out1, VDD, diff --git a/src/dbSta/test/write_verilog7.ok b/src/dbSta/test/write_verilog7.ok index 09ea10a335c..9c497585c02 100644 --- a/src/dbSta/test/write_verilog7.ok +++ b/src/dbSta/test/write_verilog7.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: write_verilog7.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 8 component-terminals. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: write_verilog7.def module top (in1, out1); input in1; diff --git a/src/dpl/test/aes.ok b/src/dpl/test/aes.ok index c99b4000342..553d6ee435c 100644 --- a/src/dpl/test/aes.ok +++ b/src/dpl/test/aes.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: aes_cipher_top_replace.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 391 pins. [INFO ODB-0131] Created 21340 components and 108388 component-terminals. [INFO ODB-0133] Created 19675 nets and 65708 connections. -[INFO ODB-0134] Finished DEF file: aes_cipher_top_replace.def Placement Analysis --------------------------------- total displacement 16976.0 u diff --git a/src/dpl/test/cell_on_block1.ok b/src/dpl/test/cell_on_block1.ok index 38f0f4cb144..a09d42c5e30 100644 --- a/src/dpl/test/cell_on_block1.ok +++ b/src/dpl/test/cell_on_block1.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: block2.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: block2.lef -[INFO ODB-0127] Reading DEF file: cell_on_block1.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 5 components and 20 component-terminals. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: cell_on_block1.def Placement Analysis --------------------------------- total displacement 62.6 u diff --git a/src/dpl/test/cell_on_block2.ok b/src/dpl/test/cell_on_block2.ok index c07c9d784e7..ad1c294caf7 100644 --- a/src/dpl/test/cell_on_block2.ok +++ b/src/dpl/test/cell_on_block2.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: cell_on_block2.lef [INFO ODB-0225] Created 16 library cells [INFO ODB-0226] Finished LEF file: cell_on_block2.lef -[INFO ODB-0127] Reading DEF file: cell_on_block2.def [INFO ODB-0128] Design: eFPGA_top [INFO ODB-0130] Created 201 pins. [INFO ODB-0131] Created 11904 components and 90887 component-terminals. [INFO ODB-0133] Created 31790 nets and 67032 connections. -[INFO ODB-0134] Finished DEF file: cell_on_block2.def Placement Analysis --------------------------------- total displacement 301889.2 u diff --git a/src/dpl/test/check1.ok b/src/dpl/test/check1.ok index ad17ac3615c..afb980d6bc6 100644 --- a/src/dpl/test/check1.ok +++ b/src/dpl/test/check1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def [WARNING DPL-0004] Placed in rows check failed (1). _277_ [ERROR DPL-0033] detailed placement checks failed. diff --git a/src/dpl/test/check1.tcl b/src/dpl/test/check1.tcl index 3d58616ba57..04ea0541b21 100644 --- a/src/dpl/test/check1.tcl +++ b/src/dpl/test/check1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # check_placement without detailed_placement read_lef Nangate45/Nangate45.lef read_def simple01.def diff --git a/src/dpl/test/check2.ok b/src/dpl/test/check2.ok index b124283262f..4af48e67afe 100644 --- a/src/dpl/test/check2.ok +++ b/src/dpl/test/check2.ok @@ -3,10 +3,8 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: check2.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0131] Created 2 components and 10 component-terminals. -[INFO ODB-0134] Finished DEF file: check2.def [WARNING DPL-0005] Overlap check failed (1). _284_ overlaps _285_ [ERROR DPL-0033] detailed placement checks failed. diff --git a/src/dpl/test/check2.tcl b/src/dpl/test/check2.tcl index a1139364e75..e347aa4e73e 100644 --- a/src/dpl/test/check2.tcl +++ b/src/dpl/test/check2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # overlapping cells read_lef Nangate45/Nangate45.lef read_def check2.def diff --git a/src/dpl/test/check3.ok b/src/dpl/test/check3.ok index c18d7aa8403..4af48e67afe 100644 --- a/src/dpl/test/check3.ok +++ b/src/dpl/test/check3.ok @@ -3,10 +3,8 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: check3.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0131] Created 2 components and 10 component-terminals. -[INFO ODB-0134] Finished DEF file: check3.def [WARNING DPL-0005] Overlap check failed (1). _284_ overlaps _285_ [ERROR DPL-0033] detailed placement checks failed. diff --git a/src/dpl/test/check3.tcl b/src/dpl/test/check3.tcl index 3f79ee6e843..d676cdb358a 100644 --- a/src/dpl/test/check3.tcl +++ b/src/dpl/test/check3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # abutting cells / overlap padded read_lef Nangate45/Nangate45.lef read_def check3.def diff --git a/src/dpl/test/check4.ok b/src/dpl/test/check4.ok index 664d189be6e..1926594729d 100644 --- a/src/dpl/test/check4.ok +++ b/src/dpl/test/check4.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: check4.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 2 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check4.def [WARNING DPL-0006] Site aligned check failed (1). FILL01 [ERROR DPL-0033] detailed placement checks failed. diff --git a/src/dpl/test/check4.tcl b/src/dpl/test/check4.tcl index 74826653708..5fdf43ba107 100644 --- a/src/dpl/test/check4.tcl +++ b/src/dpl/test/check4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # off grid fixed inst read_lef Nangate45/Nangate45.lef read_def check4.def diff --git a/src/dpl/test/check5.ok b/src/dpl/test/check5.ok index 7066edf2f3e..3616acc90db 100644 --- a/src/dpl/test/check5.ok +++ b/src/dpl/test/check5.ok @@ -6,10 +6,8 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check5.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 14 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check5.def diff --git a/src/dpl/test/check5.tcl b/src/dpl/test/check5.tcl index 1dde9ee1787..aa45a5171c2 100644 --- a/src/dpl/test/check5.tcl +++ b/src/dpl/test/check5.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # abutting blocks off grid read_lef Nangate45/Nangate45.lef read_lef extra.lef diff --git a/src/dpl/test/check6.ok b/src/dpl/test/check6.ok index 69bd7ea556c..3b38f1c51c6 100644 --- a/src/dpl/test/check6.ok +++ b/src/dpl/test/check6.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check6.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 11 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check6.def Placement Analysis --------------------------------- total displacement 0.0 u diff --git a/src/dpl/test/check6.tcl b/src/dpl/test/check6.tcl index 59125aa5aac..a4f38711678 100644 --- a/src/dpl/test/check6.tcl +++ b/src/dpl/test/check6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # std cell abutting block read_lef Nangate45/Nangate45.lef read_lef extra.lef diff --git a/src/dpl/test/check7.ok b/src/dpl/test/check7.ok index fe5c94e9ffe..cfe5bb3d6de 100644 --- a/src/dpl/test/check7.ok +++ b/src/dpl/test/check7.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check6.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 11 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check6.def [WARNING DPL-0005] Overlap check failed (1). block1 overlaps _277_ [ERROR DPL-0033] detailed placement checks failed. diff --git a/src/dpl/test/check7.tcl b/src/dpl/test/check7.tcl index 6f581333a87..0d2404c5787 100644 --- a/src/dpl/test/check7.tcl +++ b/src/dpl/test/check7.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # check_placement std cell abutting block set_placement_padding -right read_lef Nangate45/Nangate45.lef read_lef extra.lef diff --git a/src/dpl/test/check8.ok b/src/dpl/test/check8.ok index 9ff05bd714d..719ab3d4bf2 100644 --- a/src/dpl/test/check8.ok +++ b/src/dpl/test/check8.ok @@ -6,8 +6,6 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check8.def [INFO ODB-0128] Design: single_cell [INFO ODB-0131] Created 6 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 12 connections. -[INFO ODB-0134] Finished DEF file: check8.def diff --git a/src/dpl/test/check8.tcl b/src/dpl/test/check8.tcl index 57ab353760f..8335634d2a4 100644 --- a/src/dpl/test/check8.tcl +++ b/src/dpl/test/check8.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # welltap and spacing cells on core boundary read_lef Nangate45/Nangate45.lef read_lef extra.lef diff --git a/src/dpl/test/check9.ok b/src/dpl/test/check9.ok index 95a8f476de1..0495325b39b 100644 --- a/src/dpl/test/check9.ok +++ b/src/dpl/test/check9.ok @@ -6,10 +6,8 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check9.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 7 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check9.def diff --git a/src/dpl/test/check9.tcl b/src/dpl/test/check9.tcl index 977c99bc03a..4fb98a6e9be 100644 --- a/src/dpl/test/check9.tcl +++ b/src/dpl/test/check9.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # check_placement block off grid (no error) read_lef Nangate45/Nangate45.lef read_lef extra.lef diff --git a/src/dpl/test/fence01.ok b/src/dpl/test/fence01.ok index 10d99794b17..8166e7e1de7 100644 --- a/src/dpl/test/fence01.ok +++ b/src/dpl/test/fence01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fence01.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: fence01.def Placement Analysis --------------------------------- total displacement 9.1 u diff --git a/src/dpl/test/fence02.ok b/src/dpl/test/fence02.ok index 1340242d9de..424efc84405 100644 --- a/src/dpl/test/fence02.ok +++ b/src/dpl/test/fence02.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fence02.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: fence02.def Placement Analysis --------------------------------- total displacement 9.6 u diff --git a/src/dpl/test/fence03.ok b/src/dpl/test/fence03.ok index 56b0e50063c..341e5a992ad 100644 --- a/src/dpl/test/fence03.ok +++ b/src/dpl/test/fence03.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fence03.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: fence03.def Placement Analysis --------------------------------- total displacement 3.9 u diff --git a/src/dpl/test/fillers1.ok b/src/dpl/test/fillers1.ok index 23e686647f3..f94df194f5b 100644 --- a/src/dpl/test/fillers1.ok +++ b/src/dpl/test/fillers1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 3.3 u diff --git a/src/dpl/test/fillers2.ok b/src/dpl/test/fillers2.ok index 6f024b376cd..abd98c81875 100644 --- a/src/dpl/test/fillers2.ok +++ b/src/dpl/test/fillers2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 3.7 u diff --git a/src/dpl/test/fillers3.ok b/src/dpl/test/fillers3.ok index c875eb2db71..c77db19b328 100644 --- a/src/dpl/test/fillers3.ok +++ b/src/dpl/test/fillers3.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 3.3 u diff --git a/src/dpl/test/fillers3.tcl b/src/dpl/test/fillers3.tcl index 759491914fd..0b24b920407 100644 --- a/src/dpl/test/fillers3.tcl +++ b/src/dpl/test/fillers3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # filler_placement list arg read_lef Nangate45/Nangate45.lef read_def simple01.def diff --git a/src/dpl/test/fillers4.ok b/src/dpl/test/fillers4.ok index f83cb9b7d64..0073e4983ba 100644 --- a/src/dpl/test/fillers4.ok +++ b/src/dpl/test/fillers4.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: fill3.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: fill3.lef -[INFO ODB-0127] Reading DEF file: fillers4.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 8 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fillers4.def [INFO DPL-0001] Placed 10 filler instances. diff --git a/src/dpl/test/fillers4.tcl b/src/dpl/test/fillers4.tcl index e592b31758d..73ea4f2f17c 100644 --- a/src/dpl/test/fillers4.tcl +++ b/src/dpl/test/fillers4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # filler_placement size 2 3 4 8 read_lef Nangate45/Nangate45.lef read_lef fill3.lef diff --git a/src/dpl/test/fillers5.ok b/src/dpl/test/fillers5.ok index 776e08554dd..e9cfd0ececf 100644 --- a/src/dpl/test/fillers5.ok +++ b/src/dpl/test/fillers5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fragmented_row04.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fragmented_row04.def Placement Analysis --------------------------------- total displacement 1.4 u diff --git a/src/dpl/test/fillers6.ok b/src/dpl/test/fillers6.ok index 90af0f5e89b..f041de804a2 100644 --- a/src/dpl/test/fillers6.ok +++ b/src/dpl/test/fillers6.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: fill3.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: fill3.lef -[INFO ODB-0127] Reading DEF file: fillers6.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 8 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fillers6.def [ERROR DPL-0002] could not fill gap of size 1 at 4940,2800 dbu between B1 and B2 diff --git a/src/dpl/test/fillers6.tcl b/src/dpl/test/fillers6.tcl index 6bbcec46fec..f676951352e 100644 --- a/src/dpl/test/fillers6.tcl +++ b/src/dpl/test/fillers6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # filler_placement size 2 3 4 8 with gap of 1 (error) read_lef Nangate45/Nangate45.lef read_lef fill3.lef diff --git a/src/dpl/test/fillers7.ok b/src/dpl/test/fillers7.ok index 23e686647f3..f94df194f5b 100644 --- a/src/dpl/test/fillers7.ok +++ b/src/dpl/test/fillers7.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 3.3 u diff --git a/src/dpl/test/fillers8.ok b/src/dpl/test/fillers8.ok index 29cc2d9bbfd..22317bb729e 100644 --- a/src/dpl/test/fillers8.ok +++ b/src/dpl/test/fillers8.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fillers8.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 7 components and 16 component-terminals. [INFO ODB-0132] Created 2 special nets and 14 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fillers8.def [WARNING DPL-0037] Use remove_fillers before detailed placement. Placement Analysis --------------------------------- diff --git a/src/dpl/test/fragmented_row01.ok b/src/dpl/test/fragmented_row01.ok index 592fffdd390..8eeb5618ce7 100644 --- a/src/dpl/test/fragmented_row01.ok +++ b/src/dpl/test/fragmented_row01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fragmented_row01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fragmented_row01.def Placement Analysis --------------------------------- total displacement 0.2 u diff --git a/src/dpl/test/fragmented_row02.ok b/src/dpl/test/fragmented_row02.ok index 9b02576a5ab..12631dfe024 100644 --- a/src/dpl/test/fragmented_row02.ok +++ b/src/dpl/test/fragmented_row02.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fragmented_row02.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fragmented_row02.def Placement Analysis --------------------------------- total displacement 0.4 u diff --git a/src/dpl/test/fragmented_row03.ok b/src/dpl/test/fragmented_row03.ok index f4846fb07de..d4ad7574479 100644 --- a/src/dpl/test/fragmented_row03.ok +++ b/src/dpl/test/fragmented_row03.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fragmented_row03.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fragmented_row03.def [INFO DPL-0034] Detailed placement failed on: [INFO DPL-0035] _277_ [ERROR DPL-0036] Detailed placement failed. diff --git a/src/dpl/test/fragmented_row04.ok b/src/dpl/test/fragmented_row04.ok index 5a9bb8c00b1..554de345430 100644 --- a/src/dpl/test/fragmented_row04.ok +++ b/src/dpl/test/fragmented_row04.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fragmented_row04.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: fragmented_row04.def [WARNING DPL-0004] Placed in rows check failed (1). _277_ [ERROR DPL-0033] detailed placement checks failed. diff --git a/src/dpl/test/gcd.ok b/src/dpl/test/gcd.ok index 4696f91d426..5f575be5142 100644 --- a/src/dpl/test/gcd.ok +++ b/src/dpl/test/gcd.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_replace.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 549 components and 2166 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: gcd_replace.def Placement Analysis --------------------------------- total displacement 617.0 u diff --git a/src/dpl/test/gcd_nangate45.tcl b/src/dpl/test/gcd_nangate45.tcl index 679502abb01..02c4d544305 100644 --- a/src/dpl/test/gcd_nangate45.tcl +++ b/src/dpl/test/gcd_nangate45.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45.lef read_def nangate45-bench/gcd/gcd_replace.def detailed_placement diff --git a/src/dpl/test/ibex.ok b/src/dpl/test/ibex.ok index 795e668a897..ce3209968fa 100644 --- a/src/dpl/test/ibex.ok +++ b/src/dpl/test/ibex.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ibex_core_replace.def [INFO ODB-0128] Design: ibex_core [INFO ODB-0130] Created 231 pins. [INFO ODB-0131] Created 34184 components and 173049 component-terminals. [INFO ODB-0133] Created 33171 nets and 104681 connections. -[INFO ODB-0134] Finished DEF file: ibex_core_replace.def Placement Analysis --------------------------------- total displacement 23906.6 u diff --git a/src/dpl/test/max_disp1.ok b/src/dpl/test/max_disp1.ok index 93c1370da21..3c218455807 100644 --- a/src/dpl/test/max_disp1.ok +++ b/src/dpl/test/max_disp1.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_1024x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_1024x32.lef -[INFO ODB-0127] Reading DEF file: max_disp1.def [INFO ODB-0128] Design: test_RAM [INFO ODB-0130] Created 65 pins. [INFO ODB-0131] Created 1768 components and 3775 component-terminals. [INFO ODB-0133] Created 130 nets and 195 connections. -[INFO ODB-0134] Finished DEF file: max_disp1.def Placement Analysis --------------------------------- total displacement 3442.7 u diff --git a/src/dpl/test/max_disp1.tcl b/src/dpl/test/max_disp1.tcl index 765643ec5f2..782d8fb8995 100644 --- a/src/dpl/test/max_disp1.tcl +++ b/src/dpl/test/max_disp1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # floorplan corner missing rows requires -max_displacement to pull in pin buffers read_lef Nangate45/Nangate45_tech.lef read_lef Nangate45/Nangate45_stdcell.lef diff --git a/src/dpl/test/mirror1.ok b/src/dpl/test/mirror1.ok index 2f3b39942ef..8d414fa13a0 100644 --- a/src/dpl/test/mirror1.ok +++ b/src/dpl/test/mirror1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_replace.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 549 components and 2166 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: gcd_replace.def Placement Analysis --------------------------------- total displacement 1329.2 u diff --git a/src/dpl/test/mirror1.tcl b/src/dpl/test/mirror1.tcl index 4c0afc4526a..fada64acf47 100644 --- a/src/dpl/test/mirror1.tcl +++ b/src/dpl/test/mirror1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # optimize_mirroring read_lef Nangate45/Nangate45.lef read_def gcd_replace.def diff --git a/src/dpl/test/mirror2.ok b/src/dpl/test/mirror2.ok index d26b4393a7c..cb62395db5a 100644 --- a/src/dpl/test/mirror2.ok +++ b/src/dpl/test/mirror2.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: mirror2.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 11 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 3 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: mirror2.def Placement Analysis --------------------------------- total displacement 2.9 u diff --git a/src/dpl/test/mirror2.tcl b/src/dpl/test/mirror2.tcl index d60837335ec..397bc95aa1b 100644 --- a/src/dpl/test/mirror2.tcl +++ b/src/dpl/test/mirror2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # optimize_mirroring ignore BLOCKs, unconnected pins read_lef Nangate45/Nangate45.lef read_lef extra.lef diff --git a/src/dpl/test/mirror3.ok b/src/dpl/test/mirror3.ok index 9dcd6310f3c..619f8dd2155 100644 --- a/src/dpl/test/mirror3.ok +++ b/src/dpl/test/mirror3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_replace.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 549 components and 2166 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: gcd_replace.def [INFO DPL-0020] Mirrored 140 instances [INFO DPL-0021] HPWL before 6950.8 u [INFO DPL-0022] HPWL after 6881.9 u diff --git a/src/dpl/test/mirror3.tcl b/src/dpl/test/mirror3.tcl index c37d004ce3c..052bcbe64eb 100644 --- a/src/dpl/test/mirror3.tcl +++ b/src/dpl/test/mirror3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # optimize_mirroring without detailed placement read_lef Nangate45/Nangate45.lef read_def gcd_replace.def diff --git a/src/dpl/test/obstruction1.ok b/src/dpl/test/obstruction1.ok index 5538b9fa7a7..93453564999 100644 --- a/src/dpl/test/obstruction1.ok +++ b/src/dpl/test/obstruction1.ok @@ -6,10 +6,8 @@ [INFO ODB-0222] Reading LEF file: obstruction1.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: obstruction1.lef -[INFO ODB-0127] Reading DEF file: obstruction1.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0131] Created 121 components and 621 component-terminals. -[INFO ODB-0134] Finished DEF file: obstruction1.def Placement Analysis --------------------------------- total displacement 47.3 u diff --git a/src/dpl/test/obstruction2.ok b/src/dpl/test/obstruction2.ok index ec6c424648d..087dc3be758 100644 --- a/src/dpl/test/obstruction2.ok +++ b/src/dpl/test/obstruction2.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: obstruction2.def [INFO ODB-0128] Design: gcd_mem1 [INFO ODB-0130] Created 61 pins. [INFO ODB-0131] Created 32 components and 201 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 384 nets and 137 connections. -[INFO ODB-0134] Finished DEF file: obstruction2.def Placement Analysis --------------------------------- total displacement 73.5 u diff --git a/src/dpl/test/pad01.ok b/src/dpl/test/pad01.ok index b2277ba13ca..52e476e63bc 100644 --- a/src/dpl/test/pad01.ok +++ b/src/dpl/test/pad01.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 4.2 u diff --git a/src/dpl/test/pad02.ok b/src/dpl/test/pad02.ok index 3fd7397e2d6..3fde5262b93 100644 --- a/src/dpl/test/pad02.ok +++ b/src/dpl/test/pad02.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def [ERROR DPL-0015] instance _277_ does not fit inside the ROW core area. DPL-0015 diff --git a/src/dpl/test/pad03.ok b/src/dpl/test/pad03.ok index e9368377529..318396a0238 100644 --- a/src/dpl/test/pad03.ok +++ b/src/dpl/test/pad03.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple03.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple03.def No differences found. diff --git a/src/dpl/test/pad04.ok b/src/dpl/test/pad04.ok index cc0e30843c6..7bb7eef27f3 100644 --- a/src/dpl/test/pad04.ok +++ b/src/dpl/test/pad04.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: pad04.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0132] Created 2 special nets and 20 connections. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: pad04.def Placement Analysis --------------------------------- total displacement 0.0 u diff --git a/src/dpl/test/pad05.ok b/src/dpl/test/pad05.ok index ef512139549..7acdc99de6d 100644 --- a/src/dpl/test/pad05.ok +++ b/src/dpl/test/pad05.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check6.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 11 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check6.def Placement Analysis --------------------------------- total displacement 2.7 u diff --git a/src/dpl/test/pad06.ok b/src/dpl/test/pad06.ok index ef512139549..7acdc99de6d 100644 --- a/src/dpl/test/pad06.ok +++ b/src/dpl/test/pad06.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: extra.lef [INFO ODB-0225] Created 4 library cells [INFO ODB-0226] Finished LEF file: extra.lef -[INFO ODB-0127] Reading DEF file: check6.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 11 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 2 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: check6.def Placement Analysis --------------------------------- total displacement 2.7 u diff --git a/src/dpl/test/pad07.ok b/src/dpl/test/pad07.ok index b2277ba13ca..52e476e63bc 100644 --- a/src/dpl/test/pad07.ok +++ b/src/dpl/test/pad07.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 4.2 u diff --git a/src/dpl/test/pad08.ok b/src/dpl/test/pad08.ok index b2277ba13ca..52e476e63bc 100644 --- a/src/dpl/test/pad08.ok +++ b/src/dpl/test/pad08.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 4.2 u diff --git a/src/dpl/test/simple01.ok b/src/dpl/test/simple01.ok index cf3720c8fa8..ce03420c343 100644 --- a/src/dpl/test/simple01.ok +++ b/src/dpl/test/simple01.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple01.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple01.def Placement Analysis --------------------------------- total displacement 3.3 u diff --git a/src/dpl/test/simple02.ok b/src/dpl/test/simple02.ok index 0a4b71bd6fa..959f453ca9b 100644 --- a/src/dpl/test/simple02.ok +++ b/src/dpl/test/simple02.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple02.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple02.def Placement Analysis --------------------------------- total displacement 0.0 u diff --git a/src/dpl/test/simple03.ok b/src/dpl/test/simple03.ok index d9e6faff060..fe92478a871 100644 --- a/src/dpl/test/simple03.ok +++ b/src/dpl/test/simple03.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple03.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple03.def Placement Analysis --------------------------------- total displacement 49.4 u diff --git a/src/dpl/test/simple04.ok b/src/dpl/test/simple04.ok index 080b67cbe31..b936c3696c7 100644 --- a/src/dpl/test/simple04.ok +++ b/src/dpl/test/simple04.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple04.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0132] Created 2 special nets and 20 connections. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: simple04.def Placement Analysis --------------------------------- total displacement 0.0 u diff --git a/src/dpl/test/simple05.ok b/src/dpl/test/simple05.ok index 4289577c178..ec14f074743 100644 --- a/src/dpl/test/simple05.ok +++ b/src/dpl/test/simple05.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple05.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: simple05.def Placement Analysis --------------------------------- total displacement 2.3 u diff --git a/src/dpl/test/simple07.ok b/src/dpl/test/simple07.ok index a3362dde933..4829e99c523 100644 --- a/src/dpl/test/simple07.ok +++ b/src/dpl/test/simple07.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple07.def [INFO ODB-0128] Design: ten_cells [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 10 components and 45 component-terminals. [INFO ODB-0133] Created 11 nets and 25 connections. -[INFO ODB-0134] Finished DEF file: simple07.def Placement Analysis --------------------------------- total displacement 15.9 u diff --git a/src/dpl/test/simple08.ok b/src/dpl/test/simple08.ok index 98e6105720a..d400442d838 100644 --- a/src/dpl/test/simple08.ok +++ b/src/dpl/test/simple08.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple08.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple08.def Placement Analysis --------------------------------- total displacement 28.0 u diff --git a/src/dpl/test/simple09.ok b/src/dpl/test/simple09.ok index 1ceb45e866c..fc55076ba8d 100644 --- a/src/dpl/test/simple09.ok +++ b/src/dpl/test/simple09.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple09.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple09.def Placement Analysis --------------------------------- total displacement 2003.3 u diff --git a/src/dpl/test/simple09.tcl b/src/dpl/test/simple09.tcl index f9d80aeebd7..d1e814367c2 100644 --- a/src/dpl/test/simple09.tcl +++ b/src/dpl/test/simple09.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # inst way way outside of core read_lef Nangate45/Nangate45.lef read_def simple09.def diff --git a/src/dpl/test/simple10.ok b/src/dpl/test/simple10.ok index 7f8385b8e26..809c754fbe9 100644 --- a/src/dpl/test/simple10.ok +++ b/src/dpl/test/simple10.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: simple10.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: simple10.def Placement Analysis --------------------------------- total displacement 7.3 u diff --git a/src/dpo/test/aes.ok b/src/dpo/test/aes.ok index dbaf48bf9c3..ad5aab456ca 100644 --- a/src/dpo/test/aes.ok +++ b/src/dpo/test/aes.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: aes.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 391 pins. [INFO ODB-0131] Created 21340 components and 108388 component-terminals. [INFO ODB-0133] Created 19675 nets and 65708 connections. -[INFO ODB-0134] Finished DEF file: aes.def Detailed placement improvement. Importing netlist into detailed improver. [INFO DPO-0100] Creating network with 21340 cells, 391 terminals, 19675 edges and 66099 pins. diff --git a/src/dpo/test/gcd.ok b/src/dpo/test/gcd.ok index 3c86b923616..3305d1071fe 100644 --- a/src/dpo/test/gcd.ok +++ b/src/dpo/test/gcd.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 549 components and 2166 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Detailed placement improvement. Importing netlist into detailed improver. [INFO DPO-0100] Creating network with 549 cells, 54 terminals, 364 edges and 1122 pins. diff --git a/src/dpo/test/ibex.ok b/src/dpo/test/ibex.ok index cf144d35e65..ada11bf76c9 100644 --- a/src/dpo/test/ibex.ok +++ b/src/dpo/test/ibex.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ibex.def [INFO ODB-0128] Design: ibex_core [INFO ODB-0130] Created 231 pins. [INFO ODB-0131] Created 34184 components and 173049 component-terminals. [INFO ODB-0133] Created 33171 nets and 104681 connections. -[INFO ODB-0134] Finished DEF file: ibex.def Detailed placement improvement. Importing netlist into detailed improver. [INFO DPO-0100] Creating network with 34184 cells, 231 terminals, 33171 edges and 104912 pins. diff --git a/src/drt/test/aes_nangate45.tcl b/src/drt/test/aes_nangate45.tcl index e7088300493..aee28fa8c10 100644 --- a/src/drt/test/aes_nangate45.tcl +++ b/src/drt/test/aes_nangate45.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45_tech.lef read_lef Nangate45/Nangate45_stdcell.lef read_def aes_nangate45_preroute.def diff --git a/src/drt/test/balancer.tcl b/src/drt/test/balancer.tcl index d85647c60e4..0671c242b37 100644 --- a/src/drt/test/balancer.tcl +++ b/src/drt/test/balancer.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" add_worker_address -host 127.0.0.1 -port 1111 add_worker_address -host 127.0.0.1 -port 1112 run_load_balancer -host 127.0.0.1 -port 1234 diff --git a/src/drt/test/gcd_nangate45.tcl b/src/drt/test/gcd_nangate45.tcl index 18d32314b02..0cce1b8a79a 100644 --- a/src/drt/test/gcd_nangate45.tcl +++ b/src/drt/test/gcd_nangate45.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45_tech.lef read_lef Nangate45/Nangate45_stdcell.lef read_def gcd_nangate45_preroute.def diff --git a/src/drt/test/gcd_nangate45_dump_worker.tcl b/src/drt/test/gcd_nangate45_dump_worker.tcl index 8c4612479e7..092a8dac747 100644 --- a/src/drt/test/gcd_nangate45_dump_worker.tcl +++ b/src/drt/test/gcd_nangate45_dump_worker.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45/Nangate45_tech.lef read_lef Nangate45/Nangate45_stdcell.lef read_def gcd_nangate45_preroute.def diff --git a/src/drt/test/gcd_nangate45_test_worker.tcl b/src/drt/test/gcd_nangate45_test_worker.tcl index 12d623cfa20..b178e7f62f8 100644 --- a/src/drt/test/gcd_nangate45_test_worker.tcl +++ b/src/drt/test/gcd_nangate45_test_worker.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" set_debug_level DRT autotuner 1 detailed_route_debug -dr detailed_route_worker_debug -maze_end_iter 1 -drc_cost 8 -marker_cost 8 -follow_guide 1 -ripup_mode 1 diff --git a/src/drt/test/ispd18_sample.ok b/src/drt/test/ispd18_sample.ok index 17090439c44..410ebf23de2 100644 --- a/src/drt/test/ispd18_sample.ok +++ b/src/drt/test/ispd18_sample.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 22 technology vias [INFO ODB-0225] Created 16 library cells [INFO ODB-0226] Finished LEF file: testcase/ispd18_sample/ispd18_sample.input.lef -[INFO ODB-0127] Reading DEF file: testcase/ispd18_sample/ispd18_sample.input.def [INFO ODB-0128] Design: ispd18_sample [INFO ODB-0131] Created 22 components and 146 component-terminals. [INFO ODB-0133] Created 11 nets and 22 connections. -[INFO ODB-0134] Finished DEF file: testcase/ispd18_sample/ispd18_sample.input.def [WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule. [WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule. [WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule. diff --git a/src/drt/test/server1.tcl b/src/drt/test/server1.tcl index 20c44233534..69b0a7b25d9 100644 --- a/src/drt/test/server1.tcl +++ b/src/drt/test/server1.tcl @@ -1,2 +1,3 @@ +source "helpers.tcl" set_thread_count [expr [exec getconf _NPROCESSORS_ONLN] / 4] run_worker -host 127.0.0.1 -port 1111 \ No newline at end of file diff --git a/src/drt/test/server2.tcl b/src/drt/test/server2.tcl index c4746bb693d..c717320cc43 100644 --- a/src/drt/test/server2.tcl +++ b/src/drt/test/server2.tcl @@ -1,2 +1,3 @@ +source "helpers.tcl" set_thread_count [expr [exec getconf _NPROCESSORS_ONLN] / 4] run_worker -host 127.0.0.1 -port 1112 diff --git a/src/drt/test/single_step.ok b/src/drt/test/single_step.ok index 17090439c44..410ebf23de2 100644 --- a/src/drt/test/single_step.ok +++ b/src/drt/test/single_step.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 22 technology vias [INFO ODB-0225] Created 16 library cells [INFO ODB-0226] Finished LEF file: testcase/ispd18_sample/ispd18_sample.input.lef -[INFO ODB-0127] Reading DEF file: testcase/ispd18_sample/ispd18_sample.input.def [INFO ODB-0128] Design: ispd18_sample [INFO ODB-0131] Created 22 components and 146 component-terminals. [INFO ODB-0133] Created 11 nets and 22 connections. -[INFO ODB-0134] Finished DEF file: testcase/ispd18_sample/ispd18_sample.input.def [WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule. [WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule. [WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule. diff --git a/src/gpl/test/aes_test_01.tcl b/src/gpl/test/aes_test_01.tcl index 5882214aa8a..3014a36a004 100644 --- a/src/gpl/test/aes_test_01.tcl +++ b/src/gpl/test/aes_test_01.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" set design aes_cipher_top set lib_dir library/nangate45/ set design_dir design/nangate45/${design} diff --git a/src/gpl/test/ar01.ok b/src/gpl/test/ar01.ok index b346796efba..10aa425861a 100644 --- a/src/gpl/test/ar01.ok +++ b/src/gpl/test/ar01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./ar01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./ar01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 2280 2240 diff --git a/src/gpl/test/ar02.ok b/src/gpl/test/ar02.ok index c144a4f5795..89050a7ec10 100644 --- a/src/gpl/test/ar02.ok +++ b/src/gpl/test/ar02.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./ar02.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./ar02.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 2280 2240 diff --git a/src/gpl/test/core01.ok b/src/gpl/test/core01.ok index a7115105126..82394cc2627 100644 --- a/src/gpl/test/core01.ok +++ b/src/gpl/test/core01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./core01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./core01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 2280 2240 diff --git a/src/gpl/test/density01.ok b/src/gpl/test/density01.ok index 3d9517657b8..5729225e3e3 100644 --- a/src/gpl/test/density01.ok +++ b/src/gpl/test/density01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./density01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./density01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/diverge01.ok b/src/gpl/test/diverge01.ok index 6a71f31c53a..ecc8113b3fa 100644 --- a/src/gpl/test/diverge01.ok +++ b/src/gpl/test/diverge01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./diverge01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./diverge01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/error01.ok b/src/gpl/test/error01.ok index 0d361b9f2e9..cb1dea38a52 100644 --- a/src/gpl/test/error01.ok +++ b/src/gpl/test/error01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./error01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./error01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/fragmented_row_test_01.tcl b/src/gpl/test/fragmented_row_test_01.tcl index 3ef06b3b11f..f22712183b5 100644 --- a/src/gpl/test/fragmented_row_test_01.tcl +++ b/src/gpl/test/fragmented_row_test_01.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" set design gcd set lib_dir library/nangate45/ set design_dir design/nangate45/${design} diff --git a/src/gpl/test/incremental01.ok b/src/gpl/test/incremental01.ok index 023f7a36ea2..627a6d69839 100644 --- a/src/gpl/test/incremental01.ok +++ b/src/gpl/test/incremental01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./incremental01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./incremental01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/incremental02.ok b/src/gpl/test/incremental02.ok index 327fc9255e3..cd96f12f713 100644 --- a/src/gpl/test/incremental02.ok +++ b/src/gpl/test/incremental02.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./incremental02.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 388 pins. [INFO ODB-0131] Created 24951 components and 119534 component-terminals. [INFO ODB-0132] Created 2 special nets and 49902 connections. [INFO ODB-0133] Created 21886 nets and 69632 connections. -[INFO ODB-0134] Finished DEF file: ./incremental02.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 20140 25200 diff --git a/src/gpl/test/report_hpwl.tcl b/src/gpl/test/report_hpwl.tcl index 3359ad9d3bc..47626ee6757 100644 --- a/src/gpl/test/report_hpwl.tcl +++ b/src/gpl/test/report_hpwl.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" set db [::ord::get_db] set block [[$db getChip] getBlock] diff --git a/src/gpl/test/simple01-obs.ok b/src/gpl/test/simple01-obs.ok index ab77a20c314..9466d6b8354 100644 --- a/src/gpl/test/simple01-obs.ok +++ b/src/gpl/test/simple01-obs.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01-obs.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple01-obs.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple01-ref.ok b/src/gpl/test/simple01-ref.ok index 5c755df012c..b24270383df 100644 --- a/src/gpl/test/simple01-ref.ok +++ b/src/gpl/test/simple01-ref.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01-ref.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple01-ref.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple01-skip-io.ok b/src/gpl/test/simple01-skip-io.ok index da872f41b4f..faa41764280 100644 --- a/src/gpl/test/simple01-skip-io.ok +++ b/src/gpl/test/simple01-skip-io.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01-skip-io.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple01-skip-io.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple01-td-tune.ok b/src/gpl/test/simple01-td-tune.ok index 38176974396..3ab19d4f283 100644 --- a/src/gpl/test/simple01-td-tune.ok +++ b/src/gpl/test/simple01-td-tune.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01-td-tune.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 286 components and 1624 component-terminals. [INFO ODB-0133] Created 356 nets and 1052 connections. -[INFO ODB-0134] Finished DEF file: ./simple01-td-tune.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple01-td.ok b/src/gpl/test/simple01-td.ok index 287f8487c81..749efae0a8e 100644 --- a/src/gpl/test/simple01-td.ok +++ b/src/gpl/test/simple01-td.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01-td.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 286 components and 1624 component-terminals. [INFO ODB-0133] Created 356 nets and 1052 connections. -[INFO ODB-0134] Finished DEF file: ./simple01-td.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple01-uniform.ok b/src/gpl/test/simple01-uniform.ok index 393126ed743..5d9fae1f95b 100644 --- a/src/gpl/test/simple01-uniform.ok +++ b/src/gpl/test/simple01-uniform.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple01.ok b/src/gpl/test/simple01.ok index 97ed3577691..faf23079558 100644 --- a/src/gpl/test/simple01.ok +++ b/src/gpl/test/simple01.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple01.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple01.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple02.ok b/src/gpl/test/simple02.ok index 8594b97d8ff..ff7b019ed32 100644 --- a/src/gpl/test/simple02.ok +++ b/src/gpl/test/simple02.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple02.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple02.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple03.ok b/src/gpl/test/simple03.ok index cef6b5ddf0a..098d5eafbb7 100644 --- a/src/gpl/test/simple03.ok +++ b/src/gpl/test/simple03.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple03.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple03.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple04.ok b/src/gpl/test/simple04.ok index b18dc927fc8..c404318ba0d 100644 --- a/src/gpl/test/simple04.ok +++ b/src/gpl/test/simple04.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple04.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple04.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple05.ok b/src/gpl/test/simple05.ok index 7cd52ac9e5d..d0127d132b2 100644 --- a/src/gpl/test/simple05.ok +++ b/src/gpl/test/simple05.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple05.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: ./simple05.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 3800 2800 diff --git a/src/gpl/test/simple06.ok b/src/gpl/test/simple06.ok index 0781ecdf362..d52a546223e 100644 --- a/src/gpl/test/simple06.ok +++ b/src/gpl/test/simple06.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple06.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1656 component-terminals. [INFO ODB-0133] Created 364 nets and 1068 connections. -[INFO ODB-0134] Finished DEF file: ./simple06.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/gpl/test/simple07.ok b/src/gpl/test/simple07.ok index 119a931655e..a90c1141787 100644 --- a/src/gpl/test/simple07.ok +++ b/src/gpl/test/simple07.ok @@ -7,13 +7,11 @@ To avoid this warning in the future, remove this statement from the LEF file wit [INFO ODB-0224] Created 25 technology vias [INFO ODB-0225] Created 441 library cells [INFO ODB-0226] Finished LEF file: ./sky130hd.lef -[INFO ODB-0127] Reading DEF file: ./simple07.def [INFO ODB-0128] Design: inverter [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 32 components and 116 component-terminals. [INFO ODB-0132] Created 2 special nets and 114 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: ./simple07.def [INFO GPL-0002] DBU: 1000 [INFO GPL-0003] SiteSize: 460 2720 [INFO GPL-0004] CoreAreaLxLy: 5520 10880 diff --git a/src/gpl/test/simple08.ok b/src/gpl/test/simple08.ok index 8b91b899687..64911e0d75e 100644 --- a/src/gpl/test/simple08.ok +++ b/src/gpl/test/simple08.ok @@ -7,13 +7,11 @@ To avoid this warning in the future, remove this statement from the LEF file wit [INFO ODB-0224] Created 25 technology vias [INFO ODB-0225] Created 441 library cells [INFO ODB-0226] Finished LEF file: ./sky130hd.lef -[INFO ODB-0127] Reading DEF file: ./simple08.def [INFO ODB-0128] Design: inverter [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 32 components and 116 component-terminals. [INFO ODB-0132] Created 2 special nets and 114 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: ./simple08.def [INFO GPL-0002] DBU: 1000 [INFO GPL-0003] SiteSize: 460 2720 [INFO GPL-0004] CoreAreaLxLy: 5520 10880 diff --git a/src/gpl/test/simple09.ok b/src/gpl/test/simple09.ok index 9f2a5fc8a50..2c3881988d5 100644 --- a/src/gpl/test/simple09.ok +++ b/src/gpl/test/simple09.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: ./nangate45.lef -[INFO ODB-0127] Reading DEF file: ./simple09.def [INFO ODB-0128] Design: single_cell [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: ./simple09.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 0 0 diff --git a/src/grt/test/clock_route.ok b/src/grt/test/clock_route.ok index 38e9e074113..15d97c04165 100644 --- a/src/grt/test/clock_route.ok +++ b/src/grt/test/clock_route.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/clock_route_error1.ok b/src/grt/test/clock_route_error1.ok index bdb18e06017..7b79efa503b 100644 --- a/src/grt/test/clock_route_error1.ok +++ b/src/grt/test/clock_route_error1.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [ERROR STT-0001] The alpha value must be between 0.0 and 1.0. STT-0001 diff --git a/src/grt/test/clock_route_error2.ok b/src/grt/test/clock_route_error2.ok index bdb18e06017..7b79efa503b 100644 --- a/src/grt/test/clock_route_error2.ok +++ b/src/grt/test/clock_route_error2.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [ERROR STT-0001] The alpha value must be between 0.0 and 1.0. STT-0001 diff --git a/src/grt/test/congestion1.ok b/src/grt/test/congestion1.ok index 783dccbd0b1..9064eb4ce72 100644 --- a/src/grt/test/congestion1.ok +++ b/src/grt/test/congestion1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/congestion2.ok b/src/grt/test/congestion2.ok index 9019c192ea7..0fbb00f8847 100644 --- a/src/grt/test/congestion2.ok +++ b/src/grt/test/congestion2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/congestion3.ok b/src/grt/test/congestion3.ok index e1682f2b312..d7c837e44ed 100644 --- a/src/grt/test/congestion3.ok +++ b/src/grt/test/congestion3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: congestion3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 508 components and 2514 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: congestion3.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal2 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/congestion4.ok b/src/grt/test/congestion4.ok index 6429b28c5ac..b9938f457e6 100644 --- a/src/grt/test/congestion4.ok +++ b/src/grt/test/congestion4.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: congestion3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 508 components and 2514 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: congestion3.def [INFO GRT-0020] Min routing layer: metal3 [INFO GRT-0021] Max routing layer: metal3 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/congestion5.ok b/src/grt/test/congestion5.ok index 7f5fd238624..651c0431d5d 100644 --- a/src/grt/test/congestion5.ok +++ b/src/grt/test/congestion5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/congestion6.ok b/src/grt/test/congestion6.ok index 401da50ad73..93a8d83dbe6 100644 --- a/src/grt/test/congestion6.ok +++ b/src/grt/test/congestion6.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/est_rc1.ok b/src/grt/test/est_rc1.ok index d65e61e3fe6..0006826a415 100644 --- a/src/grt/test/est_rc1.ok +++ b/src/grt/test/est_rc1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/est_rc2.ok b/src/grt/test/est_rc2.ok index add26002d80..6c3e400307a 100644 --- a/src/grt/test/est_rc2.ok +++ b/src/grt/test/est_rc2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: est_rc2.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 7 components and 35 component-terminals. [INFO ODB-0133] Created 10 nets and 18 connections. -[INFO ODB-0134] Finished DEF file: est_rc2.def [INFO GRT-0020] Min routing layer: metal2 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/gcd.ok b/src/grt/test/gcd.ok index 5cc9346b2bb..9b19bd8c3d2 100644 --- a/src/grt/test/gcd.ok +++ b/src/grt/test/gcd.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/gcd_flute.ok b/src/grt/test/gcd_flute.ok index a5f79873d1b..46f5417e748 100644 --- a/src/grt/test/gcd_flute.ok +++ b/src/grt/test/gcd_flute.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/inst_pin_out_of_die.ok b/src/grt/test/inst_pin_out_of_die.ok index e6fcba75a30..4e12b9cd0bc 100644 --- a/src/grt/test/inst_pin_out_of_die.ok +++ b/src/grt/test/inst_pin_out_of_die.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: inst_pin_out_of_die.def [INFO ODB-0128] Design: gcd [INFO ODB-0131] Created 3 components and 23 component-terminals. [INFO ODB-0133] Created 1 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: inst_pin_out_of_die.def [INFO GRT-0020] Min routing layer: li1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/invalid_pin_placement.ok b/src/grt/test/invalid_pin_placement.ok index 00cda957e43..55c129a6330 100644 --- a/src/grt/test/invalid_pin_placement.ok +++ b/src/grt/test/invalid_pin_placement.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: invalid_pin_placement.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 35 components and 210 component-terminals. [INFO ODB-0133] Created 1 nets and 35 connections. -[INFO ODB-0134] Finished DEF file: invalid_pin_placement.def [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/invalid_routing_layer.ok b/src/grt/test/invalid_routing_layer.ok index 60f27faaf99..99e98a14ee5 100644 --- a/src/grt/test/invalid_routing_layer.ok +++ b/src/grt/test/invalid_routing_layer.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [ERROR GRT-0005] Layer met1 not found. GRT-0005 diff --git a/src/grt/test/macro_obs_not_aligned.ok b/src/grt/test/macro_obs_not_aligned.ok index 259c9fc74a9..e93e305f0f2 100644 --- a/src/grt/test/macro_obs_not_aligned.ok +++ b/src/grt/test/macro_obs_not_aligned.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 25 technology vias [INFO ODB-0225] Created 445 library cells [INFO ODB-0226] Finished LEF file: macro_obs_not_aligned.lef -[INFO ODB-0127] Reading DEF file: macro_obs_not_aligned.def [INFO ODB-0128] Design: user_project_wrapper [INFO ODB-0131] Created 3 components and 304 component-terminals. [INFO ODB-0133] Created 1 nets and 3 connections. -[INFO ODB-0134] Finished DEF file: macro_obs_not_aligned.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/multiple_calls.ok b/src/grt/test/multiple_calls.ok index 3d89640d717..44e3a2f0929 100644 --- a/src/grt/test/multiple_calls.ok +++ b/src/grt/test/multiple_calls.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: multiple_calls.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 87 nets and 250 connections. -[INFO ODB-0134] Finished DEF file: multiple_calls.def [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/ndr_1w_3s.ok b/src/grt/test/ndr_1w_3s.ok index e02e0d9a532..0cc7dc0eeae 100644 --- a/src/grt/test/ndr_1w_3s.ok +++ b/src/grt/test/ndr_1w_3s.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/ndr_2w_3s.ok b/src/grt/test/ndr_2w_3s.ok index 1190efc19d3..6c5859192fd 100644 --- a/src/grt/test/ndr_2w_3s.ok +++ b/src/grt/test/ndr_2w_3s.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/no_tracks.tcl b/src/grt/test/no_tracks.tcl index 64b943fd936..828eee0d286 100644 --- a/src/grt/test/no_tracks.tcl +++ b/src/grt/test/no_tracks.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # design with no routing tracks read_lef Nangate45/Nangate45.lef read_lib Nangate45/Nangate45_typ.lib diff --git a/src/grt/test/obs_out_of_die.ok b/src/grt/test/obs_out_of_die.ok index 18e5fbbdd95..66c6ca6d064 100644 --- a/src/grt/test/obs_out_of_die.ok +++ b/src/grt/test/obs_out_of_die.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: obs_out_of_die.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 9 components and 62 component-terminals. [INFO ODB-0133] Created 2 nets and 9 connections. -[INFO ODB-0134] Finished DEF file: obs_out_of_die.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/pd1.ok b/src/grt/test/pd1.ok index 9720ef668aa..4517ca6ac0c 100644 --- a/src/grt/test/pd1.ok +++ b/src/grt/test/pd1.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/pd2.ok b/src/grt/test/pd2.ok index 1955626d94c..6989f0f68b4 100644 --- a/src/grt/test/pd2.ok +++ b/src/grt/test/pd2.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/pd3.ok b/src/grt/test/pd3.ok index 2e0b7446c25..6eedf4336ce 100644 --- a/src/grt/test/pd3.ok +++ b/src/grt/test/pd3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/pd4.ok b/src/grt/test/pd4.ok index 6a6ed13ee82..b44b5c19124 100644 --- a/src/grt/test/pd4.ok +++ b/src/grt/test/pd4.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/pin_access1.ok b/src/grt/test/pin_access1.ok index 6ff05175d95..92c6979bc1d 100644 --- a/src/grt/test/pin_access1.ok +++ b/src/grt/test/pin_access1.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: clock_route.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: clock_route.def [INFO DRT-0167] List of default vias: Layer mcon default via: L1M1_PR diff --git a/src/grt/test/pin_access2.ok b/src/grt/test/pin_access2.ok index 0cac5964b5a..ef2452d3884 100644 --- a/src/grt/test/pin_access2.ok +++ b/src/grt/test/pin_access2.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1360 components and 6650 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130.def [INFO DRT-0167] List of default vias: Layer mcon default via: L1M1_PR diff --git a/src/grt/test/pre_routed1.ok b/src/grt/test/pre_routed1.ok index a82ba94be2c..16ce4d7595d 100644 --- a/src/grt/test/pre_routed1.ok +++ b/src/grt/test/pre_routed1.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: pre_routed1.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: pre_routed1.def [INFO GRT-0020] Min routing layer: met1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 50% diff --git a/src/grt/test/region_adjustment.ok b/src/grt/test/region_adjustment.ok index faadf9b7660..98cc01b6dba 100644 --- a/src/grt/test/region_adjustment.ok +++ b/src/grt/test/region_adjustment.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: region_adjustment.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 7 components and 35 component-terminals. [INFO ODB-0133] Created 10 nets and 18 connections. -[INFO ODB-0134] Finished DEF file: region_adjustment.def [INFO GRT-0020] Min routing layer: metal1 [INFO GRT-0021] Max routing layer: metal10 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/repair_antennas1.ok b/src/grt/test/repair_antennas1.ok index e996565c437..42fc0524f8d 100644 --- a/src/grt/test/repair_antennas1.ok +++ b/src/grt/test/repair_antennas1.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1360 components and 6650 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130.def Net clk clkbuf_0_clk/A (sky130_fd_sc_hs__clkbuf_1) met2 diff --git a/src/grt/test/repair_antennas2.ok b/src/grt/test/repair_antennas2.ok index c2c463fec01..af646522e2c 100644 --- a/src/grt/test/repair_antennas2.ok +++ b/src/grt/test/repair_antennas2.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_antennas2.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1277 components and 6322 component-terminals. [INFO ODB-0132] Created 2 special nets and 2554 connections. [INFO ODB-0133] Created 437 nets and 1214 connections. -[INFO ODB-0134] Finished DEF file: repair_antennas2.def Net _224_ _511_/B1 (sky130_fd_sc_hs__o21a_1) met1 diff --git a/src/grt/test/repair_antennas3.ok b/src/grt/test/repair_antennas3.ok index 054cedd3df4..21f380b682e 100644 --- a/src/grt/test/repair_antennas3.ok +++ b/src/grt/test/repair_antennas3.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_antennas2.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1277 components and 6322 component-terminals. [INFO ODB-0132] Created 2 special nets and 2554 connections. [INFO ODB-0133] Created 437 nets and 1214 connections. -[INFO ODB-0134] Finished DEF file: repair_antennas2.def Net _224_ _511_/B1 (sky130_fd_sc_hs__o21a_1) met1 diff --git a/src/grt/test/repair_antennas4.ok b/src/grt/test/repair_antennas4.ok index 4580897532d..ed06516168d 100644 --- a/src/grt/test/repair_antennas4.ok +++ b/src/grt/test/repair_antennas4.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1360 components and 6650 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130.def [INFO GRT-0012] Found 8 antenna violations. [WARNING GRT-0243] Unable to repair antennas on net with diodes. [INFO GRT-0015] Inserted 0 diodes. diff --git a/src/grt/test/repair_antennas_error1.ok b/src/grt/test/repair_antennas_error1.ok index f10969e4e28..7a3fa4937f9 100644 --- a/src/grt/test/repair_antennas_error1.ok +++ b/src/grt/test/repair_antennas_error1.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1360 components and 6650 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130.def [ERROR GRT-0045] Run global_route before repair_antennas. GRT-0045 [ERROR GRT-0069] Diode cell sky130_fd_sc_hs__diode_ not found. diff --git a/src/grt/test/repair_antennas_error2.ok b/src/grt/test/repair_antennas_error2.ok index 9c263707086..ec5e0855041 100644 --- a/src/grt/test/repair_antennas_error2.ok +++ b/src/grt/test/repair_antennas_error2.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1360 components and 6650 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130.def [ERROR GRT-0073] Diode cell has more than one non power/ground port. GRT-0073 diff --git a/src/grt/test/report_wire_length1.ok b/src/grt/test/report_wire_length1.ok index 2793443e90d..c836142cd28 100644 --- a/src/grt/test/report_wire_length1.ok +++ b/src/grt/test/report_wire_length1.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: report_wire_length1.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: report_wire_length1.def [INFO GRT-0237] Net clk global route wire length: 201.60um [INFO GRT-0240] Net clk detailed route wire length: 184.95um [INFO GRT-0237] Net net60 global route wire length: 14.40um diff --git a/src/grt/test/report_wire_length2.ok b/src/grt/test/report_wire_length2.ok index d19ba7c153a..0ebf798725d 100644 --- a/src/grt/test/report_wire_length2.ok +++ b/src/grt/test/report_wire_length2.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: report_wire_length1.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: report_wire_length1.def [INFO GRT-0237] Net clk global route wire length: 201.60um [INFO GRT-0240] Net clk detailed route wire length: 184.95um [INFO GRT-0237] Net clknet_0_clk global route wire length: 93.60um diff --git a/src/grt/test/report_wire_length3.ok b/src/grt/test/report_wire_length3.ok index 9ec56dcf592..930533812f6 100644 --- a/src/grt/test/report_wire_length3.ok +++ b/src/grt/test/report_wire_length3.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: report_wire_length1.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: report_wire_length1.def [INFO GRT-0237] Net clk global route wire length: 201.60um Layer met3 : 144.00um Layer met4 : 57.60um diff --git a/src/grt/test/report_wire_length4.ok b/src/grt/test/report_wire_length4.ok index 392083de58f..e591a0a49da 100644 --- a/src/grt/test/report_wire_length4.ok +++ b/src/grt/test/report_wire_length4.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: report_wire_length1.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: report_wire_length1.def [INFO GRT-0237] Net clk global route wire length: 201.60um Layer met3 : 144.00um Layer met4 : 57.60um diff --git a/src/grt/test/report_wire_length5.ok b/src/grt/test/report_wire_length5.ok index 03d62f1e6fe..1e847dafa64 100644 --- a/src/grt/test/report_wire_length5.ok +++ b/src/grt/test/report_wire_length5.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: report_wire_length1.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: report_wire_length1.def [INFO GRT-0237] Net clk global route wire length: 201.60um [INFO GRT-0240] Net clk detailed route wire length: 184.95um [INFO GRT-0237] Net net60 global route wire length: 14.40um diff --git a/src/grt/test/silence.ok b/src/grt/test/silence.ok index 81862030814..ac75cb5710e 100644 --- a/src/grt/test/silence.ok +++ b/src/grt/test/silence.ok @@ -3,10 +3,8 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 676 components and 2850 component-terminals. [INFO ODB-0133] Created 579 nets and 1498 connections. -[INFO ODB-0134] Finished DEF file: gcd.def No differences found. diff --git a/src/grt/test/tracks1.ok b/src/grt/test/tracks1.ok index 097718f30f7..dee6c9ce462 100644 --- a/src/grt/test/tracks1.ok +++ b/src/grt/test/tracks1.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: tracks1.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: tracks1.def [INFO GRT-0020] Min routing layer: li1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/tracks2.ok b/src/grt/test/tracks2.ok index da9d4e4bd05..07105b3cd25 100644 --- a/src/grt/test/tracks2.ok +++ b/src/grt/test/tracks2.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: tracks2.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: tracks2.def [INFO GRT-0020] Min routing layer: li1 [INFO GRT-0021] Max routing layer: met5 [INFO GRT-0022] Global adjustment: 0% diff --git a/src/grt/test/tracks3.ok b/src/grt/test/tracks3.ok index 244b9cf0606..41a47cfbee6 100644 --- a/src/grt/test/tracks3.ok +++ b/src/grt/test/tracks3.ok @@ -5,10 +5,8 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: tracks3.def [INFO ODB-0128] Design: gcd [WARNING ODB-0099] error: netlist component (_462_) is not defined [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 170 components and 1258 component-terminals. [INFO ODB-0133] Created 15 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: tracks3.def diff --git a/src/ifp/include/ifp/InitFloorplan.hh b/src/ifp/include/ifp/InitFloorplan.hh index d094d1fb316..566db6097a7 100644 --- a/src/ifp/include/ifp/InitFloorplan.hh +++ b/src/ifp/include/ifp/InitFloorplan.hh @@ -35,6 +35,8 @@ #pragma once +#include + namespace utl { class Logger; } @@ -79,7 +81,8 @@ class InitFloorplan const odb::Rect& core, const std::string& site_name); - void insertTiecells(odb::dbMTerm* tie_term, const std::string& prefix); + void insertTiecells(odb::dbMTerm* tie_term, + const std::string& prefix = "TIEOFF_"); void makeTracks(); void makeTracks(odb::dbTechLayer* layer, diff --git a/src/ifp/src/CMakeLists.txt b/src/ifp/src/CMakeLists.txt index 4995c7595dc..25ec35c78d4 100644 --- a/src/ifp/src/CMakeLists.txt +++ b/src/ifp/src/CMakeLists.txt @@ -60,6 +60,21 @@ target_link_libraries(ifp utl ) +if (Python3_FOUND AND BUILD_PYTHON) + swig_lib(NAME ifp_py + NAMESPACE ifp + LANGUAGE python + I_FILE InitFloorplan-py.i + SWIG_INCLUDES ${PROJECT_SOURCE_DIR}/src/ifp/include + SCRIPTS ${CMAKE_CURRENT_BINARY_DIR}/ifp_py.py + ) + + target_include_directories(ifp_py + PUBLIC + ../include + ) +endif() + messages( TARGET ifp OUTPUT_DIR .. diff --git a/src/ifp/src/InitFloorplan-py.i b/src/ifp/src/InitFloorplan-py.i new file mode 100644 index 00000000000..12a55ebbd0d --- /dev/null +++ b/src/ifp/src/InitFloorplan-py.i @@ -0,0 +1,42 @@ +///////////////////////////////////////////////////////////////////////////// +// +// BSD 3-Clause License +// +// Copyright (c) 2022, The Regents of the University of California +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// * Neither the name of the copyright holder nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// +/////////////////////////////////////////////////////////////////////////////// + +%{ +#include "ifp/InitFloorplan.hh" +%} + +%include + +%include "ifp/InitFloorplan.hh" diff --git a/src/ifp/test/helpers.py b/src/ifp/test/helpers.py new file mode 120000 index 00000000000..e10a2da7588 --- /dev/null +++ b/src/ifp/test/helpers.py @@ -0,0 +1 @@ +../../../test/helpers.py \ No newline at end of file diff --git a/src/ifp/test/ifp_helpers.py b/src/ifp/test/ifp_helpers.py new file mode 100644 index 00000000000..8e6e950c816 --- /dev/null +++ b/src/ifp/test/ifp_helpers.py @@ -0,0 +1,93 @@ +############################################################################ +## +## BSD 3-Clause License +## +## Copyright (c) 2022, The Regents of the University of California +## All rights reserved. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, this +## list of conditions and the following disclaimer. +## +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## +## * Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from +## this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. +## +############################################################################ +import openroad as ord +import odb + +class IFPError(Exception): + def __init__(self, msg): + print(msg) + +# To be removed once we have UPF support +def create_voltage_domain(domain_name, area): + # which flavor of error reporting should be used here? + if len(area) != 4: + raise IFPError("utl::error ODB 315 '-area is a list of 4 coordinates'") + + db = ord.get_db() + chip = db.getChip() + + if chip == None: + raise IFPError("utl::error ODB 317 'please load the design before trying to use this command'") + + block = chip.getBlock() + region = odb.dbRegion_create(block, domain_name) + + if region == None: + raise IFPError("utl::error ODB 318 'duplicate region name'") + + lx, ly, ux, uy = area + box = odb.dbBox_create(region, lx, ly, ux, uy) + group = odb.dbGroup_create(region, domain_name) + + if group == None: + raise IFPError("utl::error ODB 319 'duplicate group name'") + + group.setType("VOLTAGE_DOMAIN") + + +def insert_tiecells(floorplan, args, prefix=None): + tie_pin_split = args.split("/") + port = tie_pin_split[-1] + tie_cell = "/".join(tie_pin_split[0:-1]) + master = None + + db = ord.get_db() + + for lib in db.getLibs(): + master = lib.findMaster(tie_cell) + if master != None: + break + + if master == None: + raise IFPError(f"IFP 31 Unable to find master: {tie_cell}") + + mterm = master.findMTerm(port) + if mterm == None: + raise IFPError(f"IFP 32 Unable to find master pin: {args}") + + if prefix: + floorplan.insertTiecells(mterm, prefix) + else: + floorplan.insertTiecells(mterm) diff --git a/src/ifp/test/init_floorplan1.py b/src/ifp/test/init_floorplan1.py new file mode 100644 index 00000000000..719b1e08d3b --- /dev/null +++ b/src/ifp/test/init_floorplan1.py @@ -0,0 +1,19 @@ +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan1.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan1.defok', def_file) diff --git a/src/ifp/test/init_floorplan2.py b/src/ifp/test/init_floorplan2.py new file mode 100644 index 00000000000..7fe5ac10eb6 --- /dev/null +++ b/src/ifp/test/init_floorplan2.py @@ -0,0 +1,22 @@ +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +space = design.micronToDBU(1) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(30, + 0.5, + space, space, space, space, + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan2.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan2.defok', def_file) diff --git a/src/ifp/test/init_floorplan3.py b/src/ifp/test/init_floorplan3.py new file mode 100644 index 00000000000..0b6cd1f517a --- /dev/null +++ b/src/ifp/test/init_floorplan3.py @@ -0,0 +1,22 @@ +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +space = design.micronToDBU(2) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(30, + 0.5, + space, space, space, space, + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan3.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan3.defok', def_file) diff --git a/src/ifp/test/init_floorplan4.py b/src/ifp/test/init_floorplan4.py new file mode 100644 index 00000000000..8f5268e8bf8 --- /dev/null +++ b/src/ifp/test/init_floorplan4.py @@ -0,0 +1,22 @@ +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +die_area = helpers.make_rect(design, 0, 0, 1000, 1000) +core_area = helpers.make_rect(design, 110, 110, 900, 900) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(die_area, + core_area, + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan4.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan4.defok', def_file) diff --git a/src/ifp/test/init_floorplan6.py b/src/ifp/test/init_floorplan6.py new file mode 100644 index 00000000000..d94fc456894 --- /dev/null +++ b/src/ifp/test/init_floorplan6.py @@ -0,0 +1,25 @@ +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +bottom = design.micronToDBU(100) +top = design.micronToDBU(150) +left = design.micronToDBU(200) +right = design.micronToDBU(300) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(30, + 0.5, + bottom, top, left, right, + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan6.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan6.defok', def_file) diff --git a/src/ifp/test/init_floorplan7.py b/src/ifp/test/init_floorplan7.py new file mode 100644 index 00000000000..261df3ee79b --- /dev/null +++ b/src/ifp/test/init_floorplan7.py @@ -0,0 +1,27 @@ +# init_floorplan called twice for some stupid reason + +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +die1 = helpers.make_rect(design, 0, 0, 1000, 1000) +core1 = helpers.make_rect(design, 100, 100, 900, 900) +die2 = helpers.make_rect(design, 100, 100, 1100, 1100) +core2 = helpers.make_rect(design, 200, 200, 800, 800) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(die1, core1, + "FreePDK45_38x28_10R_NP_162NW_34O") +floorplan.initFloorplan(die2, core2, + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan7.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan7.defok', def_file) diff --git a/src/ifp/test/init_floorplan8.py b/src/ifp/test/init_floorplan8.py new file mode 100644 index 00000000000..0cc31c98ae5 --- /dev/null +++ b/src/ifp/test/init_floorplan8.py @@ -0,0 +1,28 @@ +from openroad import Tech, Design +import odb +import helpers +import ifp_helpers as ifph + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +die = helpers.make_rect(design, 0, 0, 150, 150) +core = helpers.make_rect(design, 20, 20, 130, 130) + +l = design.micronToDBU(27) +u = design.micronToDBU(60) + +ifph.create_voltage_domain("TEMP_ANALOG", (l, l, u, u)) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(die, core, + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan8.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan8.defok', def_file) diff --git a/src/ifp/test/init_floorplan9.py b/src/ifp/test/init_floorplan9.py new file mode 100644 index 00000000000..37198ea50fa --- /dev/null +++ b/src/ifp/test/init_floorplan9.py @@ -0,0 +1,32 @@ +from openroad import Tech, Design +import helpers +import ifp_helpers as ifph + +tech = Tech() +tech.readLEF("sky130hd/sky130hd.tlef") +tech.readLEF("sky130hd/sky130_fd_sc_hd_merged.lef") +tech.readLiberty("sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib") + +design = Design(tech) +design.readVerilog("reg2.v") +design.link("top") + +die = helpers.make_rect(design, 0, 0, 155.48, 146.88) +core = helpers.make_rect(design, 18.4, 16.32, 137.08, 130.56) + +floorplan = design.getFloorplan() + +lx = design.micronToDBU(33.58) +ly = design.micronToDBU(32.64) +ux = design.micronToDBU(64.86) +uy = design.micronToDBU(62.56) + +ifph.create_voltage_domain("TEMP_ANALOG", (lx, ly, ux, uy)) + +floorplan.initFloorplan(die, core, "unithd") + ##"FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("init_floorplan9.def") +design.writeDef(def_file) +helpers.diff_files('init_floorplan9.defok', def_file) + diff --git a/src/ifp/test/make_tracks1.py b/src/ifp/test/make_tracks1.py new file mode 100644 index 00000000000..40a430bcc36 --- /dev/null +++ b/src/ifp/test/make_tracks1.py @@ -0,0 +1,21 @@ +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + +floorplan.makeTracks() + +def_file = helpers.make_result_file("make_tracks1.def") +design.writeDef(def_file) +helpers.diff_files('make_tracks1.defok', def_file) diff --git a/src/ifp/test/make_tracks2.py b/src/ifp/test/make_tracks2.py new file mode 100644 index 00000000000..c7c01cda8ca --- /dev/null +++ b/src/ifp/test/make_tracks2.py @@ -0,0 +1,31 @@ +import openroad as ord +from openroad import Tech, Design +import odb +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + +db_tech = ord.get_db_tech() +m1 = db_tech.findLayer("metal1") +m2 = db_tech.findLayer("metal2") + +t1 = design.micronToDBU(0.1) +t2 = design.micronToDBU(0.2) + +floorplan.makeTracks(m1, t1, t2, t1, t2) +floorplan.makeTracks(m2, t1, t2, t1, t2) + +def_file = helpers.make_result_file("make_tracks2.def") +design.writeDef(def_file) +helpers.diff_files('make_tracks2.defok', def_file) diff --git a/src/ifp/test/make_tracks3.py b/src/ifp/test/make_tracks3.py new file mode 100644 index 00000000000..4c0de9aa8f5 --- /dev/null +++ b/src/ifp/test/make_tracks3.py @@ -0,0 +1,33 @@ +import openroad as ord +from openroad import Tech, Design +import odb +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 10, 20, 1010, 1020), + helpers.make_rect(design, 110, 120, 910, 920), + "FreePDK45_38x28_10R_NP_162NW_34O") + +db_tech = ord.get_db_tech() +m1 = db_tech.findLayer("metal1") +m2 = db_tech.findLayer("metal2") + +x_offset = design.micronToDBU(0.1) +x_pitch = design.micronToDBU(0.2) +y_offset = design.micronToDBU(0.1) +y_pitch = design.micronToDBU(0.2) + +floorplan.makeTracks(m1, x_offset, x_pitch, y_offset, y_pitch) +floorplan.makeTracks(m2, x_offset, x_pitch, y_offset, y_pitch) + +def_file = helpers.make_result_file("make_tracks3.def") +design.writeDef(def_file) +helpers.diff_files('make_tracks3.defok', def_file) diff --git a/src/ifp/test/make_tracks4.py b/src/ifp/test/make_tracks4.py new file mode 100644 index 00000000000..8b775bfde97 --- /dev/null +++ b/src/ifp/test/make_tracks4.py @@ -0,0 +1,32 @@ +import openroad as ord +from openroad import Tech, Design +import odb +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 200, 200), + helpers.make_rect(design, 10, 10, 190, 190), + "FreePDK45_38x28_10R_NP_162NW_34O") + +db_tech = ord.get_db_tech() +m2 = db_tech.findLayer("metal2") + +x_offset = design.micronToDBU(300) +x_pitch = design.micronToDBU(0.2) +y_offset = design.micronToDBU(0.1) +y_pitch = design.micronToDBU(0.2) +floorplan.makeTracks(m2, x_offset, x_pitch, y_offset, y_pitch) + +x_offset = design.micronToDBU(0.1) +x_pitch = design.micronToDBU(0.2) +y_offset = design.micronToDBU(300) +y_pitch = design.micronToDBU(0.2) +floorplan.makeTracks(m2, x_offset, x_pitch, y_offset, y_pitch) diff --git a/src/ifp/test/make_tracks5.py b/src/ifp/test/make_tracks5.py new file mode 100644 index 00000000000..5579a244b24 --- /dev/null +++ b/src/ifp/test/make_tracks5.py @@ -0,0 +1,36 @@ +import openroad as ord +from openroad import Tech, Design +import odb +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + +db_tech = ord.get_db_tech() +m1 = db_tech.findLayer("metal1") + +x_offset = design.micronToDBU(0.1) +x_pitch = design.micronToDBU(0.2) +y_offset = design.micronToDBU(0.1) +y_pitch = design.micronToDBU(0.2) + +floorplan.makeTracks(m1, x_offset, x_pitch, y_offset, y_pitch) + +x_offset = design.micronToDBU(0.15) +y_offset = design.micronToDBU(0.15) + +floorplan.makeTracks(m1, x_offset, x_pitch, y_offset, y_pitch) + +def_file = helpers.make_result_file("make_tracks5.def") +design.writeDef(def_file) +helpers.diff_files('make_tracks5.defok', def_file) diff --git a/src/ifp/test/make_tracks6.py b/src/ifp/test/make_tracks6.py new file mode 100644 index 00000000000..4957719907b --- /dev/null +++ b/src/ifp/test/make_tracks6.py @@ -0,0 +1,23 @@ +import openroad as ord +from openroad import Tech, Design +import odb +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + + +floorplan.makeTracks() + +def_file = helpers.make_result_file("make_tracks6.def") +design.writeDef(def_file) +helpers.diff_files('make_tracks6.defok', def_file) diff --git a/src/ifp/test/placement_blockage1.py b/src/ifp/test/placement_blockage1.py new file mode 100644 index 00000000000..9f05f8742cf --- /dev/null +++ b/src/ifp/test/placement_blockage1.py @@ -0,0 +1,24 @@ +import openroad as ord +import odb +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +odb.dbBlockage_create(ord.get_db_block(), 0, 0, 1000000, 208400) +odb.dbBlockage_create(ord.get_db_block(), 0, 508400, 1000000, 708400) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("placement_blockage1.def") +design.writeDef(def_file) +helpers.diff_files('placement_blockage1.defok', def_file) diff --git a/src/ifp/test/placement_blockage2.py b/src/ifp/test/placement_blockage2.py new file mode 100644 index 00000000000..8d6224532ef --- /dev/null +++ b/src/ifp/test/placement_blockage2.py @@ -0,0 +1,23 @@ +import openroad as ord +import odb +from openroad import Tech, Design +import helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("reg1.v") +design.link("top") + +odb.dbBlockage_create(ord.get_db_block(), 0, 0, 2000000, 208400) + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + +def_file = helpers.make_result_file("placement_blockage2.def") +design.writeDef(def_file) +helpers.diff_files('placement_blockage2.defok', def_file) diff --git a/src/ifp/test/tiecells.py b/src/ifp/test/tiecells.py new file mode 100644 index 00000000000..d5e3f9be7cb --- /dev/null +++ b/src/ifp/test/tiecells.py @@ -0,0 +1,25 @@ +import openroad as ord +import odb +from openroad import Tech, Design +import helpers, ifp_helpers + +tech = Tech() +tech.readLEF("Nangate45/Nangate45.lef") +tech.readLiberty("Nangate45/Nangate45_typ.lib") + +design = Design(tech) +design.readVerilog("tiecells.v") +design.link("top") + +floorplan = design.getFloorplan() +floorplan.initFloorplan(helpers.make_rect(design, 0, 0, 1000, 1000), + helpers.make_rect(design, 100, 100, 900, 900), + "FreePDK45_38x28_10R_NP_162NW_34O") + + +ifp_helpers.insert_tiecells(floorplan, "LOGIC0_X1/Z", "TIE_ZERO_") +ifp_helpers.insert_tiecells(floorplan, "LOGIC1_X1/Z") + +def_file = helpers.make_result_file("tiecells.def") +design.writeDef(def_file) +helpers.diff_files('tiecells.defok', def_file) diff --git a/src/mpl/test/east_west.tcl b/src/mpl/test/east_west.tcl index c8a64abc62c..61ca2fbad18 100644 --- a/src/mpl/test/east_west.tcl +++ b/src/mpl/test/east_west.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_liberty Nangate45/fakeram45_64x7.lib diff --git a/src/mpl/test/east_west1.ok b/src/mpl/test/east_west1.ok index 19be66eddf4..515c5e52e42 100644 --- a/src/mpl/test/east_west1.ok +++ b/src/mpl/test/east_west1.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: east_west1.def [INFO ODB-0128] Design: mem2 [INFO ODB-0130] Created 15 pins. [INFO ODB-0131] Created 2 components and 64 component-terminals. [INFO ODB-0133] Created 15 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: east_west1.def [INFO MPL-0005] Found 2 macros. [INFO MPL-0009] West pins 7. [INFO MPL-0009] East pins 5. diff --git a/src/mpl/test/east_west2.ok b/src/mpl/test/east_west2.ok index 444629adf4a..c084a9eecc2 100644 --- a/src/mpl/test/east_west2.ok +++ b/src/mpl/test/east_west2.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: east_west1.def [INFO ODB-0128] Design: mem2 [INFO ODB-0130] Created 15 pins. [INFO ODB-0131] Created 2 components and 64 component-terminals. [INFO ODB-0133] Created 15 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: east_west1.def [INFO MPL-0005] Found 2 macros. [INFO MPL-0009] West pins 7. [INFO MPL-0009] East pins 5. diff --git a/src/mpl/test/level3.tcl b/src/mpl/test/level3.tcl index 8e88edaffa9..c2bca533533 100644 --- a/src/mpl/test/level3.tcl +++ b/src/mpl/test/level3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_liberty Nangate45/fakeram45_64x7.lib diff --git a/src/mpl/test/level3_01.ok b/src/mpl/test/level3_01.ok index bc59e266daf..76d230a633a 100644 --- a/src/mpl/test/level3_01.ok +++ b/src/mpl/test/level3_01.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: level3.def [INFO ODB-0128] Design: gcd_mem3 [INFO ODB-0130] Created 75 pins. [INFO ODB-0131] Created 24 components and 222 component-terminals. [INFO ODB-0133] Created 139 nets and 153 connections. -[INFO ODB-0134] Finished DEF file: level3.def [INFO MPL-0005] Found 3 macros. [INFO MPL-0009] West pins 24. [INFO MPL-0009] East pins 23. diff --git a/src/mpl/test/level3_02.ok b/src/mpl/test/level3_02.ok index aaac4adc7dc..0d7dd6a282b 100644 --- a/src/mpl/test/level3_02.ok +++ b/src/mpl/test/level3_02.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: level3.def [INFO ODB-0128] Design: gcd_mem3 [INFO ODB-0130] Created 75 pins. [INFO ODB-0131] Created 24 components and 222 component-terminals. [INFO ODB-0133] Created 139 nets and 153 connections. -[INFO ODB-0134] Finished DEF file: level3.def [INFO GPL-0002] DBU: 2000 [INFO GPL-0003] SiteSize: 380 2800 [INFO GPL-0004] CoreAreaLxLy: 10260 11200 diff --git a/src/mpl/test/snap_layer1.ok b/src/mpl/test/snap_layer1.ok index f059a13f3e8..c1dc3369baf 100644 --- a/src/mpl/test/snap_layer1.ok +++ b/src/mpl/test/snap_layer1.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: east_west1.def [INFO ODB-0128] Design: mem2 [INFO ODB-0130] Created 15 pins. [INFO ODB-0131] Created 2 components and 64 component-terminals. [INFO ODB-0133] Created 15 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: east_west1.def [INFO MPL-0005] Found 2 macros. [INFO MPL-0009] West pins 7. [INFO MPL-0009] East pins 5. diff --git a/src/mpl2/test/mp_test1.ok b/src/mpl2/test/mp_test1.ok index a24035a58b5..c795afca67f 100644 --- a/src/mpl2/test/mp_test1.ok +++ b/src/mpl2/test/mp_test1.ok @@ -28,11 +28,9 @@ [INFO ODB-0225] Created 2 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/fake_macros.lef [WARNING STA-0160] ./Nangate45/fake_macros.lib line 32, default_max_transition is 0.0. -[INFO ODB-0127] Reading DEF file: ./testcases/mp_test1_fp.def [INFO ODB-0128] Design: mp_test1 [INFO ODB-0252] Updated 8 pins. [INFO ODB-0253] Updated 10 components. -[INFO ODB-0134] Finished DEF file: ./testcases/mp_test1_fp.def Running Partition Design... [INFO PAR-0402] Traversed logical hierarchy Number of std cell instances: 0 diff --git a/src/mpl2/test/save_ok b/src/mpl2/test/save_ok new file mode 120000 index 00000000000..4f5b707628d --- /dev/null +++ b/src/mpl2/test/save_ok @@ -0,0 +1 @@ +../../../test/save_ok \ No newline at end of file diff --git a/src/pad/test/caravel_sky130.ok b/src/pad/test/caravel_sky130.ok index f6995b48fe1..4199f8f368b 100644 --- a/src/pad/test/caravel_sky130.ok +++ b/src/pad/test/caravel_sky130.ok @@ -134,12 +134,10 @@ The NOWIREEXTENSIONATPIN statement will be ignored. See file caravel_sky130/lef/ [INFO ODB-0222] Reading LEF file: caravel_sky130/lef/sky130_fd_io__top_xres4v2.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: caravel_sky130/lef/sky130_fd_io__top_xres4v2.lef -[INFO ODB-0127] Reading DEF file: caravel_sky130/chip_io.def [INFO ODB-0128] Design: chip_io [INFO ODB-0130] Created 722 pins. [INFO ODB-0131] Created 818 components and 11059 component-terminals. [INFO ODB-0133] Created 767 nets and 1080 connections. -[INFO ODB-0134] Finished DEF file: caravel_sky130/chip_io.def Loading library data Extracting footprint [WARNING PAD-0046] No power nets found in design. diff --git a/src/pad/test/spell_check_documentation.tcl b/src/pad/test/spell_check_documentation.tcl index 0d80539750b..22778e46bb2 100644 --- a/src/pad/test/spell_check_documentation.tcl +++ b/src/pad/test/spell_check_documentation.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" exec aspell --lang=en create master ./en-custom.rws < ICeWall.wordlist foreach file [glob -nocomplain ../doc/*.md] { exec cat $file | aspell --ignore-case list --extra-dicts=./en-custom.rws | sort -u diff --git a/src/pad/test/tcl_interface.example.tcl b/src/pad/test/tcl_interface.example.tcl index 1d71a124016..f79cfcd4c38 100644 --- a/src/pad/test/tcl_interface.example.tcl +++ b/src/pad/test/tcl_interface.example.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef NangateOpenCellLibrary.mod.lef read_lef dummy_pads.lef diff --git a/src/pad/test/tcl_interface.flipchip.example.tcl b/src/pad/test/tcl_interface.flipchip.example.tcl index 69bea087204..116baf2c9be 100644 --- a/src/pad/test/tcl_interface.flipchip.example.tcl +++ b/src/pad/test/tcl_interface.flipchip.example.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef NangateOpenCellLibrary.mod.lef read_lef dummy_pads.lef diff --git a/src/par/test/graph_clique.ok b/src/par/test/graph_clique.ok index 7c33bc2c652..54737e5c6a7 100644 --- a/src/par/test/graph_clique.ok +++ b/src/par/test/graph_clique.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PAR-0067] Number of Nodes: 142 [INFO PAR-0068] Number of Hyperedges/Edges: 1366 diff --git a/src/par/test/graph_hybrid.ok b/src/par/test/graph_hybrid.ok index fd684d26592..58f4820a572 100644 --- a/src/par/test/graph_hybrid.ok +++ b/src/par/test/graph_hybrid.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PAR-0067] Number of Nodes: 142 [INFO PAR-0068] Number of Hyperedges/Edges: 176 diff --git a/src/par/test/graph_star.ok b/src/par/test/graph_star.ok index fd684d26592..58f4820a572 100644 --- a/src/par/test/graph_star.ok +++ b/src/par/test/graph_star.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PAR-0067] Number of Nodes: 142 [INFO PAR-0068] Number of Hyperedges/Edges: 176 diff --git a/src/pdn/test/asap7_no_via_generate.ok b/src/pdn/test/asap7_no_via_generate.ok index 38de49660f9..930381578f1 100644 --- a/src/pdn/test/asap7_no_via_generate.ok +++ b/src/pdn/test/asap7_no_via_generate.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_no_via_generate_v1_snapped.ok b/src/pdn/test/asap7_no_via_generate_v1_snapped.ok index 38de49660f9..930381578f1 100644 --- a/src/pdn/test/asap7_no_via_generate_v1_snapped.ok +++ b/src/pdn/test/asap7_no_via_generate_v1_snapped.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_offcenter_via.ok b/src/pdn/test/asap7_offcenter_via.ok index c19d73a8d33..ce0b97b1942 100644 --- a/src/pdn/test/asap7_offcenter_via.ok +++ b/src/pdn/test/asap7_offcenter_via.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_taper.ok b/src/pdn/test/asap7_taper.ok index ee9dbcbd54b..edf40ff4aa2 100644 --- a/src/pdn/test/asap7_taper.ok +++ b/src/pdn/test/asap7_taper.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: top No differences found. diff --git a/src/pdn/test/asap7_vias.ok b/src/pdn/test/asap7_vias.ok index 11cf79e30e6..de31b3df9f7 100644 --- a/src/pdn/test/asap7_vias.ok +++ b/src/pdn/test/asap7_vias.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_arrayspacing.ok b/src/pdn/test/asap7_vias_arrayspacing.ok index a66cd2d86da..534493cf950 100644 --- a/src/pdn/test/asap7_vias_arrayspacing.ok +++ b/src/pdn/test/asap7_vias_arrayspacing.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_arrayspacing_3_layer.ok b/src/pdn/test/asap7_vias_arrayspacing_3_layer.ok index a66cd2d86da..534493cf950 100644 --- a/src/pdn/test/asap7_vias_arrayspacing_3_layer.ok +++ b/src/pdn/test/asap7_vias_arrayspacing_3_layer.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_arrayspacing_notfirst.ok b/src/pdn/test/asap7_vias_arrayspacing_notfirst.ok index 39b3d53cd9e..8c05ca83620 100644 --- a/src/pdn/test/asap7_vias_arrayspacing_notfirst.ok +++ b/src/pdn/test/asap7_vias_arrayspacing_notfirst.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_arrayspacing_partial.ok b/src/pdn/test/asap7_vias_arrayspacing_partial.ok index a66cd2d86da..534493cf950 100644 --- a/src/pdn/test/asap7_vias_arrayspacing_partial.ok +++ b/src/pdn/test/asap7_vias_arrayspacing_partial.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_cutclass.ok b/src/pdn/test/asap7_vias_cutclass.ok index 11cf79e30e6..de31b3df9f7 100644 --- a/src/pdn/test/asap7_vias_cutclass.ok +++ b/src/pdn/test/asap7_vias_cutclass.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_dont_use.ok b/src/pdn/test/asap7_vias_dont_use.ok index 800766c056e..9eff0677ac5 100644 --- a/src/pdn/test/asap7_vias_dont_use.ok +++ b/src/pdn/test/asap7_vias_dont_use.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/asap7_vias_max_rows_columns.ok b/src/pdn/test/asap7_vias_max_rows_columns.ok index 11cf79e30e6..de31b3df9f7 100644 --- a/src/pdn/test/asap7_vias_max_rows_columns.ok +++ b/src/pdn/test/asap7_vias_max_rows_columns.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/convert.ok b/src/pdn/test/convert.ok index 8401e46b3d1..f9a9af20042 100644 --- a/src/pdn/test/convert.ok +++ b/src/pdn/test/convert.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def #################################### # global connections #################################### diff --git a/src/pdn/test/core_grid.ok b/src/pdn/test/core_grid.ok index 527b1190b8d..c941a76b407 100644 --- a/src/pdn/test/core_grid.ok +++ b/src/pdn/test/core_grid.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_adjacentcuts.ok b/src/pdn/test/core_grid_adjacentcuts.ok index 8ae5a3638fd..a419e1a5d08 100644 --- a/src/pdn/test/core_grid_adjacentcuts.ok +++ b/src/pdn/test/core_grid_adjacentcuts.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45_vias/Nangate45_adjacentcuts.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_auto_domain.ok b/src/pdn/test/core_grid_auto_domain.ok index 268fad4f109..846384ee6d2 100644 --- a/src/pdn/test/core_grid_auto_domain.ok +++ b/src/pdn/test/core_grid_auto_domain.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0101] Using VDD as power net for Core domain. [INFO PDN-0102] Using VSS as ground net for Core domain. [INFO PDN-0001] Inserting grid: Core diff --git a/src/pdn/test/core_grid_auto_domain_multiple_nets.ok b/src/pdn/test/core_grid_auto_domain_multiple_nets.ok index 055ff32fb1c..6a22f8eb560 100644 --- a/src/pdn/test/core_grid_auto_domain_multiple_nets.ok +++ b/src/pdn/test/core_grid_auto_domain_multiple_nets.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [ERROR PDN-0181] Found multiple possible nets for POWER net for Core domain. PDN-0181 diff --git a/src/pdn/test/core_grid_cut_pitch.ok b/src/pdn/test/core_grid_cut_pitch.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_cut_pitch.ok +++ b/src/pdn/test/core_grid_cut_pitch.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_dual_followpins.ok b/src/pdn/test/core_grid_dual_followpins.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_dual_followpins.ok +++ b/src/pdn/test/core_grid_dual_followpins.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_dual_followpins_error.ok b/src/pdn/test/core_grid_dual_followpins_error.ok index 4a4ebb123ed..8be7b81a667 100644 --- a/src/pdn/test/core_grid_dual_followpins_error.ok +++ b/src/pdn/test/core_grid_dual_followpins_error.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [ERROR PDN-0192] There are multiple (2) followpin definitions in Core, but no connect statements between them. PDN-0192 [ERROR PDN-0193] There are only (1) followpin connect statements when 2 is/are required. diff --git a/src/pdn/test/core_grid_extend_to_boundary.ok b/src/pdn/test/core_grid_extend_to_boundary.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_extend_to_boundary.ok +++ b/src/pdn/test/core_grid_extend_to_boundary.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_extend_to_boundary_no_pins.ok b/src/pdn/test/core_grid_extend_to_boundary_no_pins.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_extend_to_boundary_no_pins.ok +++ b/src/pdn/test/core_grid_extend_to_boundary_no_pins.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_failed_via_report.ok b/src/pdn/test/core_grid_failed_via_report.ok index 07d6a53aafe..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_failed_via_report.ok +++ b/src/pdn/test/core_grid_failed_via_report.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan_obstructions.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan_obstructions.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_no_trim.ok b/src/pdn/test/core_grid_no_trim.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_no_trim.ok +++ b/src/pdn/test/core_grid_no_trim.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_obstruction.ok b/src/pdn/test/core_grid_obstruction.ok index 07d6a53aafe..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_obstruction.ok +++ b/src/pdn/test/core_grid_obstruction.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan_obstructions.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan_obstructions.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_offset_strap.ok b/src/pdn/test/core_grid_offset_strap.ok index bf86da9bd5a..fbf81f7f25d 100644 --- a/src/pdn/test/core_grid_offset_strap.ok +++ b/src/pdn/test/core_grid_offset_strap.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130_fd_sc_hd_merged.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130_fd_sc_hd_merged.lef -[INFO ODB-0127] Reading DEF file: sky130_gcd/floorplan.def [INFO ODB-0128] Design: spm [INFO ODB-0130] Created 36 pins. [INFO ODB-0131] Created 488 components and 1960 component-terminals. [INFO ODB-0133] Created 352 nets and 984 connections. -[INFO ODB-0134] Finished DEF file: sky130_gcd/floorplan.def [INFO PDN-0001] Inserting grid: stdcell_grid No differences found. diff --git a/src/pdn/test/core_grid_snap.ok b/src/pdn/test/core_grid_snap.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_snap.ok +++ b/src/pdn/test/core_grid_snap.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_split_cuts.ok b/src/pdn/test/core_grid_split_cuts.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_split_cuts.ok +++ b/src/pdn/test/core_grid_split_cuts.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_start_power.ok b/src/pdn/test/core_grid_start_power.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_start_power.ok +++ b/src/pdn/test/core_grid_start_power.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_start_power_strap_ground.ok b/src/pdn/test/core_grid_start_power_strap_ground.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_start_power_strap_ground.ok +++ b/src/pdn/test/core_grid_start_power_strap_ground.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_strap_count.ok b/src/pdn/test/core_grid_strap_count.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_strap_count.ok +++ b/src/pdn/test/core_grid_strap_count.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_via_snap.ok b/src/pdn/test/core_grid_via_snap.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_via_snap.ok +++ b/src/pdn/test/core_grid_via_snap.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_M7_pins.ok b/src/pdn/test/core_grid_with_M7_pins.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_M7_pins.ok +++ b/src/pdn/test/core_grid_with_M7_pins.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_dual_rings.ok b/src/pdn/test/core_grid_with_dual_rings.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_dual_rings.ok +++ b/src/pdn/test/core_grid_with_dual_rings.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_rings.ok b/src/pdn/test/core_grid_with_rings.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_rings.ok +++ b/src/pdn/test/core_grid_with_rings.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_rings_connect.ok b/src/pdn/test/core_grid_with_rings_connect.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_rings_connect.ok +++ b/src/pdn/test/core_grid_with_rings_connect.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_rings_with_limit_straps.ok b/src/pdn/test/core_grid_with_rings_with_limit_straps.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_rings_with_limit_straps.ok +++ b/src/pdn/test/core_grid_with_rings_with_limit_straps.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_rings_with_straps.ok b/src/pdn/test/core_grid_with_rings_with_straps.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_rings_with_straps.ok +++ b/src/pdn/test/core_grid_with_rings_with_straps.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_rings_with_straps_rings_over_core.ok b/src/pdn/test/core_grid_with_rings_with_straps_rings_over_core.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_rings_with_straps_rings_over_core.ok +++ b/src/pdn/test/core_grid_with_rings_with_straps_rings_over_core.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/core_grid_with_routing_obstructions.ok b/src/pdn/test/core_grid_with_routing_obstructions.ok index 10ae98be3ad..b7b76fd1ad1 100644 --- a/src/pdn/test/core_grid_with_routing_obstructions.ok +++ b/src/pdn/test/core_grid_with_routing_obstructions.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/design_width.ok b/src/pdn/test/design_width.ok index e66067d8bff..381dca1c363 100644 --- a/src/pdn/test/design_width.ok +++ b/src/pdn/test/design_width.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [ERROR PDN-0185] Insufficient width (14.04 um) to add straps on layer M8 in grid "Core" with total strap width 6.0 um and offset 10.0 um. PDN-0185 diff --git a/src/pdn/test/existing.ok b/src/pdn/test/existing.ok index 3f527653443..659120bbf9b 100644 --- a/src/pdn/test/existing.ok +++ b/src/pdn/test/existing.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_existing/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_existing/floorplan.def [INFO PDN-0101] Using VDD as power net for Core domain. [INFO PDN-0102] Using VSS as ground net for Core domain. [INFO PDN-0001] Inserting grid: existing_grid diff --git a/src/pdn/test/macros.ok b/src/pdn/test/macros.ok index e859cdde5c6..22970e9f395 100644 --- a/src/pdn/test/macros.ok +++ b/src/pdn/test/macros.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_add_twice.ok b/src/pdn/test/macros_add_twice.ok index 2677b9e529f..cfc2bea6125 100644 --- a/src/pdn/test/macros_add_twice.ok +++ b/src/pdn/test/macros_add_twice.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [WARNING PDN-0182] Instance dcache.data.data_arrays_0.data_arrays_0_ext.mem already belongs to another grid "sram1" and therefore cannot belong to "sram2". diff --git a/src/pdn/test/macros_cells.ok b/src/pdn/test/macros_cells.ok index 78d8b095cfc..c21bae053bb 100644 --- a/src/pdn/test/macros_cells.ok +++ b/src/pdn/test/macros_cells.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_cells_dont_touch.ok b/src/pdn/test/macros_cells_dont_touch.ok index 541bd6ccd3d..317367a6671 100644 --- a/src/pdn/test/macros_cells_dont_touch.ok +++ b/src/pdn/test/macros_cells_dont_touch.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def No differences found. diff --git a/src/pdn/test/macros_cells_extend_boundary.ok b/src/pdn/test/macros_cells_extend_boundary.ok index 78d8b095cfc..c21bae053bb 100644 --- a/src/pdn/test/macros_cells_extend_boundary.ok +++ b/src/pdn/test/macros_cells_extend_boundary.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_cells_no_grid.ok b/src/pdn/test/macros_cells_no_grid.ok index 78d8b095cfc..c21bae053bb 100644 --- a/src/pdn/test/macros_cells_no_grid.ok +++ b/src/pdn/test/macros_cells_no_grid.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_cells_orient.ok b/src/pdn/test/macros_cells_orient.ok index bbd97478e72..453cc15ae8c 100644 --- a/src/pdn/test/macros_cells_orient.ok +++ b/src/pdn/test/macros_cells_orient.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan_orient.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan_orient.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - dcache.data.data_arrays_0.data_arrays_0_ext.mem diff --git a/src/pdn/test/macros_different_nets.ok b/src/pdn/test/macros_different_nets.ok index e859cdde5c6..22970e9f395 100644 --- a/src/pdn/test/macros_different_nets.ok +++ b/src/pdn/test/macros_different_nets.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_grid_through.ok b/src/pdn/test/macros_grid_through.ok index 3a9e4f6e8a8..17fe09ba4cc 100644 --- a/src/pdn/test/macros_grid_through.ok +++ b/src/pdn/test/macros_grid_through.ok @@ -5,10 +5,8 @@ [INFO ODB-0222] Reading LEF file: sky130_pll/pll.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_pll/pll.lef -[INFO ODB-0127] Reading DEF file: sky130_pll/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0131] Created 1 components and 2 component-terminals. -[INFO ODB-0134] Finished DEF file: sky130_pll/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: Macro - PLL No differences found. diff --git a/src/pdn/test/macros_narrow_channel.ok b/src/pdn/test/macros_narrow_channel.ok index bc173164d99..5e836c5c019 100644 --- a/src/pdn/test/macros_narrow_channel.ok +++ b/src/pdn/test/macros_narrow_channel.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan_narrow.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 440 components and 1090 component-terminals. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan_narrow.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_narrow_channel_jog.ok b/src/pdn/test/macros_narrow_channel_jog.ok index 82821f39cdf..285fb176bf9 100644 --- a/src/pdn/test/macros_narrow_channel_jog.ok +++ b/src/pdn/test/macros_narrow_channel_jog.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan_with_jog.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 630 components and 1680 component-terminals. [INFO ODB-0132] Created 2 special nets and 1260 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan_with_jog.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_narrow_channel_large_spacing.ok b/src/pdn/test/macros_narrow_channel_large_spacing.ok index 2ceb065341d..8e74e36376c 100644 --- a/src/pdn/test/macros_narrow_channel_large_spacing.ok +++ b/src/pdn/test/macros_narrow_channel_large_spacing.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan_very_narrow.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 535 components and 1280 component-terminals. [INFO ODB-0132] Created 2 special nets and 1070 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan_very_narrow.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_narrow_channel_repair_overlap.ok b/src/pdn/test/macros_narrow_channel_repair_overlap.ok index bc173164d99..5e836c5c019 100644 --- a/src/pdn/test/macros_narrow_channel_repair_overlap.ok +++ b/src/pdn/test/macros_narrow_channel_repair_overlap.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan_narrow.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 440 components and 1090 component-terminals. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan_narrow.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_with_halo.ok b/src/pdn/test/macros_with_halo.ok index e859cdde5c6..22970e9f395 100644 --- a/src/pdn/test/macros_with_halo.ok +++ b/src/pdn/test/macros_with_halo.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/macros_with_rings.ok b/src/pdn/test/macros_with_rings.ok index e859cdde5c6..22970e9f395 100644 --- a/src/pdn/test/macros_with_rings.ok +++ b/src/pdn/test/macros_with_rings.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_macros/fakeram45_64x32.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: nangate_macros/fakeram45_64x32.lef -[INFO ODB-0127] Reading DEF file: nangate_macros/floorplan.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 269 pins. [INFO ODB-0131] Created 547 components and 1304 component-terminals. [INFO ODB-0132] Created 2 special nets and 1094 connections. [INFO ODB-0133] Created 269 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: nangate_macros/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: sram1 - dcache.data.data_arrays_0.data_arrays_0_ext.mem [INFO PDN-0001] Inserting grid: sram2 - frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem diff --git a/src/pdn/test/max_width.ok b/src/pdn/test/max_width.ok index 80c2673804d..52231dd3ee3 100644 --- a/src/pdn/test/max_width.ok +++ b/src/pdn/test/max_width.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [ERROR PDN-0107] Width (4.0000 um) specified for layer M8 is greater than maximum width (2.0000 um). PDN-0107 diff --git a/src/pdn/test/min_spacing.ok b/src/pdn/test/min_spacing.ok index 9a81d7cd125..d7c1bcbd6f5 100644 --- a/src/pdn/test/min_spacing.ok +++ b/src/pdn/test/min_spacing.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [ERROR PDN-0108] Spacing (0.1000 um) specified for layer metal5 is less than minimum spacing (0.1400 um). PDN-0108 diff --git a/src/pdn/test/min_width.ok b/src/pdn/test/min_width.ok index f761fba4b83..bef7e13e09b 100644 --- a/src/pdn/test/min_width.ok +++ b/src/pdn/test/min_width.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [ERROR PDN-0106] Width (0.1000 um) specified for layer metal5 is less than minimum width (0.1400 um). PDN-0106 diff --git a/src/pdn/test/names.ok b/src/pdn/test/names.ok index 1bc88a4ea7f..149cbc902c2 100644 --- a/src/pdn/test/names.ok +++ b/src/pdn/test/names.ok @@ -20,12 +20,10 @@ [INFO ODB-0222] Reading LEF file: sky130_secondary_nets/vref_gen_nmos_with_trim.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_secondary_nets/vref_gen_nmos_with_trim.lef -[INFO ODB-0127] Reading DEF file: sky130_secondary_nets/floorplan.def [INFO ODB-0128] Design: ldoInst [INFO ODB-0130] Created 34 pins. [INFO ODB-0131] Created 454 components and 2681 component-terminals. [INFO ODB-0133] Created 260 nets and 856 connections. -[INFO ODB-0134] Finished DEF file: sky130_secondary_nets/floorplan.def [WARNING PDN-0183] Replacing existing core voltage domain. [ERROR PDN-0184] Cannot have region voltage domain with the same name already exists: test_domain PDN-0184 diff --git a/src/pdn/test/offgrid.ok b/src/pdn/test/offgrid.ok index 6a4cdcc97fa..1ca76e6e349 100644 --- a/src/pdn/test/offgrid.ok +++ b/src/pdn/test/offgrid.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def [ERROR PDN-0191] Width of 2.0010 does not fit the manufacturing grid of 0.0050. PDN-0191 diff --git a/src/pdn/test/pads_black_parrot.ok b/src/pdn/test/pads_black_parrot.ok index 97ece853a84..02df1478d64 100644 --- a/src/pdn/test/pads_black_parrot.ok +++ b/src/pdn/test/pads_black_parrot.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1514 components and 1480 component-terminals. [INFO ODB-0132] Created 2 special nets and 268 connections. [INFO ODB-0133] Created 350 nets and 390 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/pads_black_parrot_flipchip.ok b/src/pdn/test/pads_black_parrot_flipchip.ok index 3a3b22f0cf9..b9aab8cd0a1 100644 --- a/src/pdn/test/pads_black_parrot_flipchip.ok +++ b/src/pdn/test/pads_black_parrot_flipchip.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan_flipchip.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1489 components and 1523 component-terminals. [INFO ODB-0132] Created 143 special nets and 883 connections. [INFO ODB-0133] Created 219 nets and 267 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan_flipchip.def [INFO PDN-0001] Inserting grid: Core [WARNING PDN-0110] No via inserted between metal9 and metal10 at (174.9000, 1349.2350) - (188.5700, 1350.0000) on VSS [WARNING PDN-0110] No via inserted between metal9 and metal10 at (174.9000, 1829.2350) - (188.5700, 1830.0000) on VSS diff --git a/src/pdn/test/pads_black_parrot_flipchip_connect_overpads.ok b/src/pdn/test/pads_black_parrot_flipchip_connect_overpads.ok index 3ffca719774..878235bdd1a 100644 --- a/src/pdn/test/pads_black_parrot_flipchip_connect_overpads.ok +++ b/src/pdn/test/pads_black_parrot_flipchip_connect_overpads.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads_short.lef [INFO ODB-0225] Created 22 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads_short.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan_flipchip_short.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 135 pins. [INFO ODB-0131] Created 1400 components and 5671 component-terminals. [INFO ODB-0132] Created 139 special nets and 4915 connections. [INFO ODB-0133] Created 219 nets and 267 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan_flipchip_short.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/pads_black_parrot_limit_connect.ok b/src/pdn/test/pads_black_parrot_limit_connect.ok index 97ece853a84..02df1478d64 100644 --- a/src/pdn/test/pads_black_parrot_limit_connect.ok +++ b/src/pdn/test/pads_black_parrot_limit_connect.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1514 components and 1480 component-terminals. [INFO ODB-0132] Created 2 special nets and 268 connections. [INFO ODB-0133] Created 350 nets and 390 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/pads_black_parrot_max_width.ok b/src/pdn/test/pads_black_parrot_max_width.ok index 0208c81b844..544d6e71514 100644 --- a/src/pdn/test/pads_black_parrot_max_width.ok +++ b/src/pdn/test/pads_black_parrot_max_width.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1514 components and 1480 component-terminals. [INFO ODB-0132] Created 2 special nets and 268 connections. [INFO ODB-0133] Created 350 nets and 390 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/pads_black_parrot_no_connect.ok b/src/pdn/test/pads_black_parrot_no_connect.ok index 97ece853a84..02df1478d64 100644 --- a/src/pdn/test/pads_black_parrot_no_connect.ok +++ b/src/pdn/test/pads_black_parrot_no_connect.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1514 components and 1480 component-terminals. [INFO ODB-0132] Created 2 special nets and 268 connections. [INFO ODB-0133] Created 350 nets and 390 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/pads_black_parrot_offset.ok b/src/pdn/test/pads_black_parrot_offset.ok index 97ece853a84..02df1478d64 100644 --- a/src/pdn/test/pads_black_parrot_offset.ok +++ b/src/pdn/test/pads_black_parrot_offset.ok @@ -6,12 +6,10 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1514 components and 1480 component-terminals. [INFO ODB-0132] Created 2 special nets and 268 connections. [INFO ODB-0133] Created 350 nets and 390 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/power_switch.ok b/src/pdn/test/power_switch.ok index ba14397b56a..e81598ac575 100644 --- a/src/pdn/test/power_switch.ok +++ b/src/pdn/test/power_switch.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: sky130_power_switch/power_switch.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_power_switch/power_switch.lef -[INFO ODB-0127] Reading DEF file: sky130_power_switch/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1160 components and 3368 component-terminals. [INFO ODB-0133] Created 324 nets and 1048 connections. -[INFO ODB-0134] Finished DEF file: sky130_power_switch/floorplan.def Switched power cell: POWER_SWITCH Control pin: SLEEP Acknowledge pin: SLEEP_OUT diff --git a/src/pdn/test/power_switch_cut_rows.ok b/src/pdn/test/power_switch_cut_rows.ok index 5d225a57f7f..403a7540c5e 100644 --- a/src/pdn/test/power_switch_cut_rows.ok +++ b/src/pdn/test/power_switch_cut_rows.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: sky130_power_switch/power_switch.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_power_switch/power_switch.lef -[INFO ODB-0127] Reading DEF file: sky130_power_switch/floorplan_cut_rows.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1151 components and 3350 component-terminals. [INFO ODB-0133] Created 324 nets and 1048 connections. -[INFO ODB-0134] Finished DEF file: sky130_power_switch/floorplan_cut_rows.def [INFO PDN-0001] Inserting grid: Core [WARNING PDN-0223] Unable to insert power switch (PSW_ROW_53_0) at (28.9800, 155.0400), due to lack of available rows. [WARNING PDN-0223] Unable to insert power switch (PSW_ROW_53_1) at (56.1200, 155.0400), due to lack of available rows. diff --git a/src/pdn/test/power_switch_daisy.ok b/src/pdn/test/power_switch_daisy.ok index 4f172f05bd4..15572ad8b89 100644 --- a/src/pdn/test/power_switch_daisy.ok +++ b/src/pdn/test/power_switch_daisy.ok @@ -8,11 +8,9 @@ [INFO ODB-0222] Reading LEF file: sky130_power_switch/power_switch.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_power_switch/power_switch.lef -[INFO ODB-0127] Reading DEF file: sky130_power_switch/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1160 components and 3368 component-terminals. [INFO ODB-0133] Created 324 nets and 1048 connections. -[INFO ODB-0134] Finished DEF file: sky130_power_switch/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/power_switch_regions.ok b/src/pdn/test/power_switch_regions.ok index c138cb5ce73..47ebf866f76 100644 --- a/src/pdn/test/power_switch_regions.ok +++ b/src/pdn/test/power_switch_regions.ok @@ -14,12 +14,10 @@ [INFO ODB-0222] Reading LEF file: sky130_power_switch/power_switch.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_power_switch/power_switch.lef -[INFO ODB-0127] Reading DEF file: sky130_power_switch/floorplan_regions.def [INFO ODB-0128] Design: tempsenseInst [INFO ODB-0130] Created 35 pins. [INFO ODB-0131] Created 393 components and 1287 component-terminals. [INFO ODB-0133] Created 157 nets and 491 connections. -[INFO ODB-0134] Finished DEF file: sky130_power_switch/floorplan_regions.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: TempSensor No differences found. diff --git a/src/pdn/test/power_switch_star.ok b/src/pdn/test/power_switch_star.ok index 4f172f05bd4..15572ad8b89 100644 --- a/src/pdn/test/power_switch_star.ok +++ b/src/pdn/test/power_switch_star.ok @@ -8,11 +8,9 @@ [INFO ODB-0222] Reading LEF file: sky130_power_switch/power_switch.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_power_switch/power_switch.lef -[INFO ODB-0127] Reading DEF file: sky130_power_switch/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1160 components and 3368 component-terminals. [INFO ODB-0133] Created 324 nets and 1048 connections. -[INFO ODB-0134] Finished DEF file: sky130_power_switch/floorplan.def [INFO PDN-0001] Inserting grid: Core No differences found. diff --git a/src/pdn/test/region_non_rect.ok b/src/pdn/test/region_non_rect.ok index e8458037813..123d566de4b 100644 --- a/src/pdn/test/region_non_rect.ok +++ b/src/pdn/test/region_non_rect.ok @@ -11,11 +11,9 @@ [INFO ODB-0222] Reading LEF file: sky130_non_rect_region/SLC.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_non_rect_region/SLC.lef -[INFO ODB-0127] Reading DEF file: sky130_non_rect_region/floorplan.def [INFO ODB-0128] Design: tempsenseInst [INFO ODB-0130] Created 35 pins. [INFO ODB-0131] Created 393 components and 1287 component-terminals. [INFO ODB-0133] Created 155 nets and 491 connections. -[INFO ODB-0134] Finished DEF file: sky130_non_rect_region/floorplan.def [ERROR PDN-0104] TEMP_ANALOG region contains 2 shapes, but only one is supported. PDN-0104 diff --git a/src/pdn/test/region_secondary_nets.ok b/src/pdn/test/region_secondary_nets.ok index 4ea0946558b..5ba435ab6b8 100644 --- a/src/pdn/test/region_secondary_nets.ok +++ b/src/pdn/test/region_secondary_nets.ok @@ -20,12 +20,10 @@ [INFO ODB-0222] Reading LEF file: sky130_secondary_nets/vref_gen_nmos_with_trim.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_secondary_nets/vref_gen_nmos_with_trim.lef -[INFO ODB-0127] Reading DEF file: sky130_secondary_nets/floorplan.def [INFO ODB-0128] Design: ldoInst [INFO ODB-0130] Created 34 pins. [INFO ODB-0131] Created 454 components and 2681 component-terminals. [INFO ODB-0133] Created 260 nets and 856 connections. -[INFO ODB-0134] Finished DEF file: sky130_secondary_nets/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: Region No differences found. diff --git a/src/pdn/test/region_temp_sensor.ok b/src/pdn/test/region_temp_sensor.ok index 68ba84be8d4..333751fd5f2 100644 --- a/src/pdn/test/region_temp_sensor.ok +++ b/src/pdn/test/region_temp_sensor.ok @@ -11,12 +11,10 @@ [INFO ODB-0222] Reading LEF file: sky130_temp_sensor/SLC.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: sky130_temp_sensor/SLC.lef -[INFO ODB-0127] Reading DEF file: sky130_temp_sensor/floorplan.def [INFO ODB-0128] Design: tempsenseInst [INFO ODB-0130] Created 35 pins. [INFO ODB-0131] Created 393 components and 1287 component-terminals. [INFO ODB-0133] Created 155 nets and 491 connections. -[INFO ODB-0134] Finished DEF file: sky130_temp_sensor/floorplan.def [INFO PDN-0001] Inserting grid: Core [INFO PDN-0001] Inserting grid: TempSensor No differences found. diff --git a/src/pdn/test/repair_vias.ok b/src/pdn/test/repair_vias.ok index 2cd5401387c..7e2e8909d70 100644 --- a/src/pdn/test/repair_vias.ok +++ b/src/pdn/test/repair_vias.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan_repair.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0132] Created 2 special nets and 812 connections. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan_repair.def Via repair on VDD, VSS V1 removed 9 vias out of 2597 vias (0.35%). No differences found. diff --git a/src/pdn/test/report.ok b/src/pdn/test/report.ok index f7f6ebcd2d7..eb790ec7562 100644 --- a/src/pdn/test/report.ok +++ b/src/pdn/test/report.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: nangate_bsg_black_parrot/dummy_pads.lef [INFO ODB-0225] Created 24 library cells [INFO ODB-0226] Finished LEF file: nangate_bsg_black_parrot/dummy_pads.lef -[INFO ODB-0127] Reading DEF file: nangate_bsg_black_parrot/floorplan.def [INFO ODB-0128] Design: soc_bsg_black_parrot [INFO ODB-0130] Created 141 pins. [INFO ODB-0131] Created 1514 components and 1480 component-terminals. [INFO ODB-0132] Created 2 special nets and 268 connections. [INFO ODB-0133] Created 350 nets and 390 connections. -[INFO ODB-0134] Finished DEF file: nangate_bsg_black_parrot/floorplan.def Voltage domain: Core Power net: VDD Ground net: VSS diff --git a/src/pdn/test/reset.ok b/src/pdn/test/reset.ok index 5a5b38ded6a..00b78daf522 100644 --- a/src/pdn/test/reset.ok +++ b/src/pdn/test/reset.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan.def Voltage domain: Core Power net: VDD Ground net: VSS diff --git a/src/pdn/test/ripup.ok b/src/pdn/test/ripup.ok index f463d6fe4cb..f208863ac52 100644 --- a/src/pdn/test/ripup.ok +++ b/src/pdn/test/ripup.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: nangate_gcd/floorplan_with_grid.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 482 components and 2074 component-terminals. [INFO ODB-0132] Created 2 special nets and 964 connections. [INFO ODB-0133] Created 385 nets and 1110 connections. -[INFO ODB-0134] Finished DEF file: nangate_gcd/floorplan_with_grid.def [INFO PDN-0101] Using VDD as power net for Core domain. [INFO PDN-0102] Using VSS as ground net for Core domain. No differences found. diff --git a/src/pdn/test/widthtable.ok b/src/pdn/test/widthtable.ok index c1d214dcf56..d380fca89e4 100644 --- a/src/pdn/test/widthtable.ok +++ b/src/pdn/test/widthtable.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef [INFO ODB-0225] Created 212 library cells [INFO ODB-0226] Finished LEF file: asap7_vias/asap7sc7p5t_27_R_1x.lef -[INFO ODB-0127] Reading DEF file: asap7_vias/floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 406 components and 1816 component-terminals. [INFO ODB-0133] Created 361 nets and 1004 connections. -[INFO ODB-0134] Finished DEF file: asap7_vias/floorplan.def [ERROR PDN-0114] Width (0.0720 um) specified for layer M2 in not a valid width, must be 0.0180, 0.0900, 0.1620, 0.2340, 0.3060, 0.3780. PDN-0114 diff --git a/src/ppl/test/add_constraint1.ok b/src/ppl/test/add_constraint1.ok index c78224bfa47..4a7eaebba61 100644 --- a/src/ppl/test/add_constraint1.ok +++ b/src/ppl/test/add_constraint1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.13u, in the top edge. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/add_constraint2.ok b/src/ppl/test/add_constraint2.ok index 4e8d1c96950..af4c2485f35 100644 --- a/src/ppl/test/add_constraint2.ok +++ b/src/ppl/test/add_constraint2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.13u, in the bottom edge. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/add_constraint3.ok b/src/ppl/test/add_constraint3.ok index b3894ad4b3d..0fa3513d85d 100644 --- a/src/ppl/test/add_constraint3.ok +++ b/src/ppl/test/add_constraint3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.8u, in the left edge. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/add_constraint4.ok b/src/ppl/test/add_constraint4.ok index 75178dae1f3..e15992c6446 100644 --- a/src/ppl/test/add_constraint4.ok +++ b/src/ppl/test/add_constraint4.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.8u, in the right edge. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/add_constraint5.ok b/src/ppl/test/add_constraint5.ok index 0b5bb951d54..77f01a43076 100644 --- a/src/ppl/test/add_constraint5.ok +++ b/src/ppl/test/add_constraint5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.8u, in the right edge. [INFO PPL-0049] Restrict OUTPUT pins to region 0.0u-100.8u, in the left edge. [INFO PPL-0048] Restrict pins [resp_val resp_rdy req_rdy req_val] to region 0.0u-100.13u at the bottom edge. diff --git a/src/ppl/test/add_constraint6.ok b/src/ppl/test/add_constraint6.ok index dd3c9f0978e..07aee7e8f3f 100644 --- a/src/ppl/test/add_constraint6.ok +++ b/src/ppl/test/add_constraint6.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0048] Restrict pins [resp_val resp_rdy req_rdy req_val req_msg*] to region 0.0u-100.13u at the bottom edge. [INFO PPL-0048] Restrict pins [req_msg[15] req_msg[14] resp_msg[15] resp_msg[14]] to region 0.0u-100.13u at the top edge. Found 0 macro blocks. diff --git a/src/ppl/test/add_constraint7.ok b/src/ppl/test/add_constraint7.ok index 214385510ac..921c8b1075e 100644 --- a/src/ppl/test/add_constraint7.ok +++ b/src/ppl/test/add_constraint7.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0048] Restrict pins [resp_val resp_rdy req_rdy req_val req_msg* *msg*] to region 0.0u-100.13u at the bottom edge. Found 0 macro blocks. Using 1u default distance from corners. diff --git a/src/ppl/test/add_constraint8.ok b/src/ppl/test/add_constraint8.ok index a05a4151f4d..099751f3f00 100644 --- a/src/ppl/test/add_constraint8.ok +++ b/src/ppl/test/add_constraint8.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0048] Restrict pins [req_msg*] to region 0.0u-18.0u at the bottom edge. [INFO PPL-0048] Restrict pins [resp_msg*] to region 10.0u-20.0u at the bottom edge. Found 0 macro blocks. diff --git a/src/ppl/test/blocked_region.ok b/src/ppl/test/blocked_region.ok index aba188b9d94..20411964b36 100644 --- a/src/ppl/test/blocked_region.ok +++ b/src/ppl/test/blocked_region.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: blocked_region.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: blocked_region.lef -[INFO ODB-0127] Reading DEF file: blocked_region.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 253 components and 1357 component-terminals. [INFO ODB-0133] Created 54 nets and 155 connections. -[INFO ODB-0134] Finished DEF file: blocked_region.def Found 1 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/cells_not_placed.ok b/src/ppl/test/cells_not_placed.ok index 4e8c6f1949b..1bf185a7347 100644 --- a/src/ppl/test/cells_not_placed.ok +++ b/src/ppl/test/cells_not_placed.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: cells_not_placed.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 295 components and 1600 component-terminals. [INFO ODB-0133] Created 54 nets and 164 connections. -[INFO ODB-0134] Finished DEF file: cells_not_placed.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.13u, in the top edge. [INFO PPL-0049] Restrict OUTPUT pins to region 0.0u-100.13u, in the bottom edge. Found 0 macro blocks. diff --git a/src/ppl/test/exclude1.ok b/src/ppl/test/exclude1.ok index 7ddc69f0a76..5fc389869f5 100644 --- a/src/ppl/test/exclude1.ok +++ b/src/ppl/test/exclude1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/exclude2.ok b/src/ppl/test/exclude2.ok index 6e89b0d7647..5c54ccedf20 100644 --- a/src/ppl/test/exclude2.ok +++ b/src/ppl/test/exclude2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/exclude3.ok b/src/ppl/test/exclude3.ok index 908bb317792..6cb3efc40aa 100644 --- a/src/ppl/test/exclude3.ok +++ b/src/ppl/test/exclude3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/gcd.ok b/src/ppl/test/gcd.ok index d783a23fa5e..873cd286f8f 100644 --- a/src/ppl/test/gcd.ok +++ b/src/ppl/test/gcd.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/group_pins1.ok b/src/ppl/test/group_pins1.ok index e77c5684e78..78bede84744 100644 --- a/src/ppl/test/group_pins1.ok +++ b/src/ppl/test/group_pins1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0041] Pin group 0: [resp_val resp_rdy req_rdy] [INFO PPL-0041] Pin group 1: [req_msg[15] req_msg[14] resp_msg[15] resp_msg[14]] diff --git a/src/ppl/test/group_pins1_gui.tcl b/src/ppl/test/group_pins1_gui.tcl index 52e432c84ff..35584df9df1 100644 --- a/src/ppl/test/group_pins1_gui.tcl +++ b/src/ppl/test/group_pins1_gui.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" gui::highlight_net "resp_val" 0 gui::highlight_net "resp_rdy" 0 gui::highlight_net "req_rdy" 0 diff --git a/src/ppl/test/group_pins2.ok b/src/ppl/test/group_pins2.ok index 56bc08e703a..afd3fd97d84 100644 --- a/src/ppl/test/group_pins2.ok +++ b/src/ppl/test/group_pins2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0041] Pin group 0: [clk req_msg[31] req_msg[30] req_msg[29] req_msg[28] req_msg[27] req_msg[26] req_msg[25] req_msg[24] req_msg[23] req_msg[22] req_msg[21] req_msg[20]] [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/group_pins3.ok b/src/ppl/test/group_pins3.ok index 7c20f4b204f..ff4625e9d2f 100644 --- a/src/ppl/test/group_pins3.ok +++ b/src/ppl/test/group_pins3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: group_pins3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1577 component-terminals. [INFO ODB-0133] Created 54 nets and 131 connections. -[INFO ODB-0134] Finished DEF file: group_pins3.def Found 0 macro blocks. [INFO PPL-0041] Pin group 0: [req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] req_msg[15] req_msg[16] req_msg[17] req_msg[18] req_msg[19] req_msg[20] req_msg[21] req_msg[22] req_msg[23] req_msg[0] req_msg[1]] [INFO PPL-0041] Pin group 1: [req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] req_msg[29] req_msg[2] req_msg[30] req_msg[31] req_msg[3] req_msg[4] req_msg[5] req_msg[6] req_msg[7] req_msg[8] req_msg[9]] diff --git a/src/ppl/test/group_pins4.ok b/src/ppl/test/group_pins4.ok index f3c3bb89e76..dfabd9c8e56 100644 --- a/src/ppl/test/group_pins4.ok +++ b/src/ppl/test/group_pins4.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: group_pins3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1577 component-terminals. [INFO ODB-0133] Created 54 nets and 131 connections. -[INFO ODB-0134] Finished DEF file: group_pins3.def [INFO PPL-0048] Restrict pins [req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] req_msg[15] req_msg[16] req_msg[17] req_msg[18] req_msg[19] req_msg[20] req_msg[21] req_msg[22] req_msg[23] req_msg[0] req_msg[1] ] to region 25.0u-95.0u at the left edge. [INFO PPL-0048] Restrict pins [req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] req_msg[29] req_msg[2] req_msg[30] req_msg[31] req_msg[3] req_msg[4] req_msg[5] req_msg[6] req_msg[7] req_msg[8] req_msg[9]] to region 5.0u-95.0u at the bottom edge. [INFO PPL-0048] Restrict pins [clk req_rdy req_val reset resp_msg[0] resp_msg[10] resp_msg[11] resp_msg[12] resp_msg[13] resp_msg[14] resp_msg[15]] to region 15.0u-95.0u at the top edge. diff --git a/src/ppl/test/group_pins5.ok b/src/ppl/test/group_pins5.ok index 79b29b4c5df..53723f92785 100644 --- a/src/ppl/test/group_pins5.ok +++ b/src/ppl/test/group_pins5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: group_pins3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1577 component-terminals. [INFO ODB-0133] Created 54 nets and 131 connections. -[INFO ODB-0134] Finished DEF file: group_pins3.def Found 0 macro blocks. [INFO PPL-0041] Pin group 0: [req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] req_msg[15] req_msg[16] req_msg[17] req_msg[18] req_msg[19] req_msg[20] req_msg[21] req_msg[22] req_msg[23] req_msg[0] req_msg[1]] [INFO PPL-0041] Pin group 1: [req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] req_msg[29] req_msg[2] req_msg[30] req_msg[31] req_msg[3] req_msg[4] req_msg[5] req_msg[6] req_msg[7] req_msg[8] req_msg[9]] diff --git a/src/ppl/test/group_pins6.ok b/src/ppl/test/group_pins6.ok index 9eb6cc1a2cc..78bb0934388 100644 --- a/src/ppl/test/group_pins6.ok +++ b/src/ppl/test/group_pins6.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: group_pins3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1577 component-terminals. [INFO ODB-0133] Created 54 nets and 131 connections. -[INFO ODB-0134] Finished DEF file: group_pins3.def [INFO PPL-0048] Restrict pins [req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] req_msg[15] req_msg[16] req_msg[17] req_msg[18] req_msg[19] req_msg[20] req_msg[21] req_msg[22] req_msg[23] req_msg[0] req_msg[1] ] to region 25.0u-95.0u at the left edge. [INFO PPL-0048] Restrict pins [req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] req_msg[29] req_msg[2] req_msg[30] req_msg[31] req_msg[3] req_msg[4] req_msg[5] req_msg[6] req_msg[7] req_msg[8] req_msg[9]] to region 5.0u-95.0u at the bottom edge. [INFO PPL-0048] Restrict pins [clk req_rdy req_val reset resp_msg[0] resp_msg[10] resp_msg[11] resp_msg[12] resp_msg[13] resp_msg[14] resp_msg[15]] to region 15.0u-95.0u at the top edge. diff --git a/src/ppl/test/group_pins7.ok b/src/ppl/test/group_pins7.ok index d1cce599eb6..e78dcb704ba 100644 --- a/src/ppl/test/group_pins7.ok +++ b/src/ppl/test/group_pins7.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: group_pins3.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 294 components and 1577 component-terminals. [INFO ODB-0133] Created 54 nets and 131 connections. -[INFO ODB-0134] Finished DEF file: group_pins3.def [INFO PPL-0048] Restrict pins [req_msg[10] req_msg[11] req_msg[12] req_msg[13] req_msg[14] req_msg[15] req_msg[16] req_msg[17] req_msg[18] req_msg[19] req_msg[20] req_msg[21] req_msg[22] req_msg[23] req_msg[0] req_msg[1]] to region 0.0u-100.8u at the left edge. [INFO PPL-0048] Restrict pins [req_msg[24] req_msg[25] req_msg[26] req_msg[27] req_msg[28] req_msg[29] req_msg[2] req_msg[30] req_msg[31] req_msg[3] req_msg[4] req_msg[5] req_msg[6] req_msg[7] req_msg[8] req_msg[9]] to region 0.0u-100.13u at the bottom edge. [INFO PPL-0048] Restrict pins [clk req_rdy req_val reset resp_msg[0] resp_msg[10] resp_msg[11] resp_msg[12] resp_msg[13] resp_msg[14] resp_msg[15]] to region 0.0u-100.13u at the top edge. diff --git a/src/ppl/test/group_pins_warn1.ok b/src/ppl/test/group_pins_warn1.ok index ff87c4269be..fdca2be4b0e 100644 --- a/src/ppl/test/group_pins_warn1.ok +++ b/src/ppl/test/group_pins_warn1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0041] Pin group 0: [resp_val resp_rdy req_rdy] [INFO PPL-0041] Pin group 1: [req_msg[15] req_msg[14] resp_msg[15] resp_msg[141]] diff --git a/src/ppl/test/invalid_layer.ok b/src/ppl/test/invalid_layer.ok index 3b6c8a39442..747ea948730 100644 --- a/src/ppl/test/invalid_layer.ok +++ b/src/ppl/test/invalid_layer.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: invalid_layer.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. -[INFO ODB-0134] Finished DEF file: invalid_layer.def Found 0 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/min_dist_in_tracks1.ok b/src/ppl/test/min_dist_in_tracks1.ok index d783a23fa5e..873cd286f8f 100644 --- a/src/ppl/test/min_dist_in_tracks1.ok +++ b/src/ppl/test/min_dist_in_tracks1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/min_dist_in_tracks2.ok b/src/ppl/test/min_dist_in_tracks2.ok index a5598320b39..ec07834ab82 100644 --- a/src/ppl/test/min_dist_in_tracks2.ok +++ b/src/ppl/test/min_dist_in_tracks2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 832 diff --git a/src/ppl/test/multi_layers.ok b/src/ppl/test/multi_layers.ok index 82c5acad5f0..06a73e8db0d 100644 --- a/src/ppl/test/multi_layers.ok +++ b/src/ppl/test/multi_layers.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 3930 diff --git a/src/ppl/test/multiple_calls.ok b/src/ppl/test/multiple_calls.ok index d133ee818c5..22d7b0a411a 100644 --- a/src/ppl/test/multiple_calls.ok +++ b/src/ppl/test/multiple_calls.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/no_instance_pins.ok b/src/ppl/test/no_instance_pins.ok index 26c1b29d4b1..180e8808667 100644 --- a/src/ppl/test/no_instance_pins.ok +++ b/src/ppl/test/no_instance_pins.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: no_instance_pins.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 10 pins. [INFO ODB-0133] Created 10 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: no_instance_pins.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/no_pins.ok b/src/ppl/test/no_pins.ok index 73b3c7392c7..f816f06089f 100644 --- a/src/ppl/test/no_pins.ok +++ b/src/ppl/test/no_pins.ok @@ -3,9 +3,7 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: no_pins.def [INFO ODB-0128] Design: gcd -[INFO ODB-0134] Finished DEF file: no_pins.def Found 0 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/no_pins.tcl b/src/ppl/test/no_pins.tcl index aac5f3bf935..70b753ffc7b 100644 --- a/src/ppl/test/no_pins.tcl +++ b/src/ppl/test/no_pins.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # design without IO pins read_lef Nangate45/Nangate45.lef read_def no_pins.def diff --git a/src/ppl/test/no_tracks.tcl b/src/ppl/test/no_tracks.tcl index 41de616dadc..19f851ce5bc 100644 --- a/src/ppl/test/no_tracks.tcl +++ b/src/ppl/test/no_tracks.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # design without routing tracks read_lef Nangate45/Nangate45.lef read_lib Nangate45/Nangate45_typ.lib diff --git a/src/ppl/test/on_grid.ok b/src/ppl/test/on_grid.ok index c48f45ad020..e9da2950e76 100644 --- a/src/ppl/test/on_grid.ok +++ b/src/ppl/test/on_grid.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130_fd_sc_hd_merged.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130_fd_sc_hd_merged.lef -[INFO ODB-0127] Reading DEF file: on_grid.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 190 components and 1097 component-terminals. [INFO ODB-0133] Created 54 nets and 143 connections. -[INFO ODB-0134] Finished DEF file: on_grid.def Found 0 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/pin_extension.ok b/src/ppl/test/pin_extension.ok index d783a23fa5e..873cd286f8f 100644 --- a/src/ppl/test/pin_extension.ok +++ b/src/ppl/test/pin_extension.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/pin_length.ok b/src/ppl/test/pin_length.ok index d783a23fa5e..873cd286f8f 100644 --- a/src/ppl/test/pin_length.ok +++ b/src/ppl/test/pin_length.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2494 diff --git a/src/ppl/test/pin_thick_multiplier.ok b/src/ppl/test/pin_thick_multiplier.ok index c08ced3285b..e7490de9d7e 100644 --- a/src/ppl/test/pin_thick_multiplier.ok +++ b/src/ppl/test/pin_thick_multiplier.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. [INFO PPL-0001] Number of slots 2490 diff --git a/src/ppl/test/place_pin1.ok b/src/ppl/test/place_pin1.ok index 0336ffcf8ff..4ce83719b93 100644 --- a/src/ppl/test/place_pin1.ok +++ b/src/ppl/test/place_pin1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0070] Pin clk placed at (40um, 30um). Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/place_pin2.ok b/src/ppl/test/place_pin2.ok index cfd21ca8368..b34d8a37e96 100644 --- a/src/ppl/test/place_pin2.ok +++ b/src/ppl/test/place_pin2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0070] Pin clk placed at (40um, 30um). [INFO PPL-0070] Pin resp_val placed at (12um, 50um). [INFO PPL-0070] Pin req_msg[0] placed at (25um, 70um). diff --git a/src/ppl/test/place_pin3.ok b/src/ppl/test/place_pin3.ok index 0495c149e58..ffea9785c07 100644 --- a/src/ppl/test/place_pin3.ok +++ b/src/ppl/test/place_pin3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0070] Pin clk placed at (0um, 29um). Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/place_pin4.ok b/src/ppl/test/place_pin4.ok index 8ca61829855..01c927f070d 100644 --- a/src/ppl/test/place_pin4.ok +++ b/src/ppl/test/place_pin4.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0070] Pin clk placed at (0um, 29um). [INFO PPL-0070] Pin resp_val placed at (11um, 1um). [INFO PPL-0070] Pin req_msg[0] placed at (24um, 98um). diff --git a/src/ppl/test/place_pin5.ok b/src/ppl/test/place_pin5.ok index 68edd532ffc..6fd5feeb58c 100644 --- a/src/ppl/test/place_pin5.ok +++ b/src/ppl/test/place_pin5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0070] Pin clk placed at (0um, 29um). [INFO PPL-0070] Pin resp_val placed at (0um, 32um). [INFO PPL-0070] Pin req_val placed at (0um, 26um). diff --git a/src/ppl/test/place_pin_error1.ok b/src/ppl/test/place_pin_error1.ok index 07858c897ef..b4d00a8dc06 100644 --- a/src/ppl/test/place_pin_error1.ok +++ b/src/ppl/test/place_pin_error1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [WARNING STA-0337] port 'qq' not found. [ERROR PPL-0061] Pins for place_pin command were not found. PPL-0061 diff --git a/src/ppl/test/place_pin_error2.ok b/src/ppl/test/place_pin_error2.ok index fd8ba0156fe..9fc12158377 100644 --- a/src/ppl/test/place_pin_error2.ok +++ b/src/ppl/test/place_pin_error2.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [ERROR PPL-0071] Command place_pin should receive only one pin name. PPL-0071 diff --git a/src/ppl/test/place_pin_error3.ok b/src/ppl/test/place_pin_error3.ok index a18cbbef8fc..041977f5979 100644 --- a/src/ppl/test/place_pin_error3.ok +++ b/src/ppl/test/place_pin_error3.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [ERROR PPL-0034] Pin clk has dimension 0.35u which is less than the min width 0.4u of layer metal7. PPL-0034 diff --git a/src/ppl/test/random1.ok b/src/ppl/test/random1.ok index 1d38ef64c3f..56c0861cfd1 100644 --- a/src/ppl/test/random1.ok +++ b/src/ppl/test/random1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/random2.ok b/src/ppl/test/random2.ok index 1d38ef64c3f..56c0861cfd1 100644 --- a/src/ppl/test/random2.ok +++ b/src/ppl/test/random2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/random3.ok b/src/ppl/test/random3.ok index 038d1b5eea7..1555ceeee7e 100644 --- a/src/ppl/test/random3.ok +++ b/src/ppl/test/random3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.13u, in the top edge. [INFO PPL-0049] Restrict OUTPUT pins to region 0.0u-100.13u, in the bottom edge. Found 0 macro blocks. diff --git a/src/ppl/test/random4.ok b/src/ppl/test/random4.ok index c3862489706..66de9d16036 100644 --- a/src/ppl/test/random4.ok +++ b/src/ppl/test/random4.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0048] Restrict pins [resp_val resp_rdy req_rdy req_val] to region 0.0u-100.13u at the bottom edge. [INFO PPL-0048] Restrict pins [req_msg[15] req_msg[14] resp_msg[15] resp_msg[14]] to region 0.0u-100.13u at the top edge. Found 0 macro blocks. diff --git a/src/ppl/test/random5.ok b/src/ppl/test/random5.ok index 5aca4a5f100..ad8a5d4d6ae 100644 --- a/src/ppl/test/random5.ok +++ b/src/ppl/test/random5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0060] Restrict pins [clk resp_val req_val resp_rdy reset req_rdy] to region (0.095u, 0.07u)-(90.0u, 90.0u) at routing layer metal10. Found 0 macro blocks. Using 1u default distance from corners. diff --git a/src/ppl/test/random6.ok b/src/ppl/test/random6.ok index 5909ef9e20c..67d80d6df31 100644 --- a/src/ppl/test/random6.ok +++ b/src/ppl/test/random6.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0060] Restrict pins [*] to region (0.095u, 0.07u)-(90.0u, 90.0u) at routing layer metal10. Found 0 macro blocks. Using 1u default distance from corners. diff --git a/src/ppl/test/random7.ok b/src/ppl/test/random7.ok index 20840dd3699..1f1e6f0ba09 100644 --- a/src/ppl/test/random7.ok +++ b/src/ppl/test/random7.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def Found 0 macro blocks. Using 1u default distance from corners. Using 2 tracks default min distance between IO pins. diff --git a/src/ppl/test/random8.ok b/src/ppl/test/random8.ok index d0f33856c12..f26066f0b65 100644 --- a/src/ppl/test/random8.ok +++ b/src/ppl/test/random8.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0049] Restrict INPUT pins to region 0.0u-100.13u, in the top edge. [INFO PPL-0049] Restrict OUTPUT pins to region 0.0u-100.13u, in the bottom edge. [INFO PPL-0048] Restrict pins [req_msg[14] req_msg[15] req_msg[16] req_msg[17]] to region 0.0u-100.8u at the left edge. diff --git a/src/ppl/test/top_layer1.ok b/src/ppl/test/top_layer1.ok index 8c413a1d95d..2ed35f41890 100644 --- a/src/ppl/test/top_layer1.ok +++ b/src/ppl/test/top_layer1.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: blocked_region.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: blocked_region.lef -[INFO ODB-0127] Reading DEF file: blocked_region.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 253 components and 1357 component-terminals. [INFO ODB-0133] Created 54 nets and 155 connections. -[INFO ODB-0134] Finished DEF file: blocked_region.def [INFO PPL-0060] Restrict pins [clk resp_val req_val resp_rdy reset req_rdy] to region (0.0u, 0.0u)-(279.96u, 279.96u) at routing layer met5. Found 1 macro blocks. Using 1u default distance from corners. diff --git a/src/ppl/test/top_layer2.ok b/src/ppl/test/top_layer2.ok index e17ffdea1ac..fb4abce52d3 100644 --- a/src/ppl/test/top_layer2.ok +++ b/src/ppl/test/top_layer2.ok @@ -8,12 +8,10 @@ [INFO ODB-0222] Reading LEF file: blocked_region.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: blocked_region.lef -[INFO ODB-0127] Reading DEF file: blocked_region.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 253 components and 1357 component-terminals. [INFO ODB-0133] Created 54 nets and 155 connections. -[INFO ODB-0134] Finished DEF file: blocked_region.def [INFO PPL-0060] Restrict pins [clk resp_val req_val resp_rdy reset req_rdy] to region (170.0u, 200.0u)-(250.0u, 250.0u) at routing layer met5. Found 1 macro blocks. Using 1u default distance from corners. diff --git a/src/ppl/test/top_layer3.ok b/src/ppl/test/top_layer3.ok index 679b41b711f..d52f1fb86cf 100644 --- a/src/ppl/test/top_layer3.ok +++ b/src/ppl/test/top_layer3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0060] Restrict pins [clk resp_val req_val resp_rdy reset req_rdy] to region (70.0u, 50.0u)-(95.0u, 95.0u) at routing layer metal10. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/top_layer4.ok b/src/ppl/test/top_layer4.ok index a8a840eb0b3..72d269e294d 100644 --- a/src/ppl/test/top_layer4.ok +++ b/src/ppl/test/top_layer4.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0060] Restrict pins [*] to region (0.095u, 0.07u)-(90.0u, 90.0u) at routing layer metal10. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/top_layer5.ok b/src/ppl/test/top_layer5.ok index 7134321586f..2e3b926df99 100644 --- a/src/ppl/test/top_layer5.ok +++ b/src/ppl/test/top_layer5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0060] Restrict pins [*_msg] to region (0.095u, 0.07u)-(90.0u, 90.0u) at routing layer metal10. Found 0 macro blocks. [INFO PPL-0010] Tentative 0 to set up sections. diff --git a/src/ppl/test/top_layer6.ok b/src/ppl/test/top_layer6.ok index 3fd4e6c1680..718a428e821 100644 --- a/src/ppl/test/top_layer6.ok +++ b/src/ppl/test/top_layer6.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0070] Pin clk placed at (4um, 4um). [INFO PPL-0060] Restrict pins [*] to region (0.0u, 0.0u)-(100.13u, 100.13u) at routing layer metal10. Found 0 macro blocks. diff --git a/src/ppl/test/top_layer7.ok b/src/ppl/test/top_layer7.ok index bcd9e4cdf74..3b6fd47bf53 100644 --- a/src/ppl/test/top_layer7.ok +++ b/src/ppl/test/top_layer7.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_obs.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0132] Created 2 special nets and 0 connections. -[INFO ODB-0134] Finished DEF file: gcd_obs.def [INFO PPL-0060] Restrict pins [*] to region (0.0u, 0.0u)-(100.13u, 100.13u) at routing layer metal7. Found 0 macro blocks. Using 1u default distance from corners. diff --git a/src/ppl/test/top_layer_error.ok b/src/ppl/test/top_layer_error.ok index 9333ebcc104..cdfa0d0646c 100644 --- a/src/ppl/test/top_layer_error.ok +++ b/src/ppl/test/top_layer_error.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 88 components and 422 component-terminals. [INFO ODB-0133] Created 54 nets and 88 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PPL-0060] Restrict pins [qq] to region (70.0u, 50.0u)-(95.0u, 95.0u) at routing layer metal10. [WARNING STA-0337] port 'qq' not found. [ERROR PPL-0061] Pins for set_io_pin_constraint command were not found. diff --git a/src/psm/test/aes_test_vdd.ok b/src/psm/test/aes_test_vdd.ok index d72ea2ff066..dbabd1bbbaa 100644 --- a/src/psm/test/aes_test_vdd.ok +++ b/src/psm/test/aes_test_vdd.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: aes.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 388 pins. [INFO ODB-0131] Created 19835 components and 101835 component-terminals. [INFO ODB-0132] Created 2 special nets and 39670 connections. [INFO ODB-0133] Created 18908 nets and 62165 connections. -[INFO ODB-0134] Finished DEF file: aes.def [INFO PSM-0001] Reading voltage source file: Vsrc_aes_vdd.loc. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_aes_vdd.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. diff --git a/src/psm/test/aes_test_vdd.tcl b/src/psm/test/aes_test_vdd.tcl index 6689bb08c1b..5ea4255648c 100644 --- a/src/psm/test/aes_test_vdd.tcl +++ b/src/psm/test/aes_test_vdd.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45.lef read_def aes.def read_liberty NangateOpenCellLibrary_typical.lib diff --git a/src/psm/test/aes_test_vdd_set_node_density.ok b/src/psm/test/aes_test_vdd_set_node_density.ok index d72ea2ff066..dbabd1bbbaa 100644 --- a/src/psm/test/aes_test_vdd_set_node_density.ok +++ b/src/psm/test/aes_test_vdd_set_node_density.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: aes.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 388 pins. [INFO ODB-0131] Created 19835 components and 101835 component-terminals. [INFO ODB-0132] Created 2 special nets and 39670 connections. [INFO ODB-0133] Created 18908 nets and 62165 connections. -[INFO ODB-0134] Finished DEF file: aes.def [INFO PSM-0001] Reading voltage source file: Vsrc_aes_vdd.loc. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_aes_vdd.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. diff --git a/src/psm/test/aes_test_vdd_set_node_density.tcl b/src/psm/test/aes_test_vdd_set_node_density.tcl index ca473c4672a..7c2182aac87 100644 --- a/src/psm/test/aes_test_vdd_set_node_density.tcl +++ b/src/psm/test/aes_test_vdd_set_node_density.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45.lef read_def aes.def read_liberty NangateOpenCellLibrary_typical.lib diff --git a/src/psm/test/aes_test_vdd_set_node_density_fact.ok b/src/psm/test/aes_test_vdd_set_node_density_fact.ok index 9d25d699f15..94ab4032afa 100644 --- a/src/psm/test/aes_test_vdd_set_node_density_fact.ok +++ b/src/psm/test/aes_test_vdd_set_node_density_fact.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: aes.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 388 pins. [INFO ODB-0131] Created 19835 components and 101835 component-terminals. [INFO ODB-0132] Created 2 special nets and 39670 connections. [INFO ODB-0133] Created 18908 nets and 62165 connections. -[INFO ODB-0134] Finished DEF file: aes.def [INFO PSM-0001] Reading voltage source file: Vsrc_aes_vdd.loc. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_aes_vdd.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 3. diff --git a/src/psm/test/aes_test_vdd_set_node_density_fact.tcl b/src/psm/test/aes_test_vdd_set_node_density_fact.tcl index 512c0478f22..dec5db51338 100644 --- a/src/psm/test/aes_test_vdd_set_node_density_fact.tcl +++ b/src/psm/test/aes_test_vdd_set_node_density_fact.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45.lef read_def aes.def read_liberty NangateOpenCellLibrary_typical.lib diff --git a/src/psm/test/aes_test_vss.ok b/src/psm/test/aes_test_vss.ok index 6f4425045a6..4d02a654112 100644 --- a/src/psm/test/aes_test_vss.ok +++ b/src/psm/test/aes_test_vss.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: aes.def [INFO ODB-0128] Design: aes_cipher_top [INFO ODB-0130] Created 388 pins. [INFO ODB-0131] Created 19835 components and 101835 component-terminals. [INFO ODB-0132] Created 2 special nets and 39670 connections. [INFO ODB-0133] Created 18908 nets and 62165 connections. -[INFO ODB-0134] Finished DEF file: aes.def [INFO PSM-0001] Reading voltage source file: Vsrc_aes_vss.loc. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_aes_vss.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. diff --git a/src/psm/test/aes_test_vss.tcl b/src/psm/test/aes_test_vss.tcl index 02182dbc140..1677c07671a 100644 --- a/src/psm/test/aes_test_vss.tcl +++ b/src/psm/test/aes_test_vss.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef Nangate45.lef read_def aes.def read_liberty NangateOpenCellLibrary_typical.lib diff --git a/src/psm/test/gcd_all_vss.ok b/src/psm/test/gcd_all_vss.ok index 173150e9df9..52a74185400 100644 --- a/src/psm/test/gcd_all_vss.ok +++ b/src/psm/test/gcd_all_vss.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 624 components and 2752 component-terminals. [INFO ODB-0132] Created 2 special nets and 1248 connections. [INFO ODB-0133] Created 581 nets and 1504 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area. [WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um. [WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um. @@ -23,9 +21,7 @@ [INFO PSM-0064] Number of voltage sources = 1. [INFO PSM-0040] All PDN stripes on net VSS are connected. [INFO PSM-0001] Reading voltage source file: Vsrc_gcd_vss.loc. -[INFO PSM-0002] Output voltage file is specified as: ./results/gcd_voltage_vss.rpt. [INFO PSM-0004] EM calculation is enabled. -[INFO PSM-0003] Output current file specified ./results/gcd_em_vss.rpt. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_gcd_vss.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [INFO PSM-0031] Number of PDN nodes on net VSS = 507. @@ -42,12 +38,10 @@ Average current: 1.96e-06 A Number of resistors: 506 ###################################### [INFO PSM-0001] Reading voltage source file: Vsrc_gcd_vss.loc. -[INFO PSM-0005] Output spice file is specified as: ./results/gcd_spice_vss.sp. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_gcd_vss.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [INFO PSM-0031] Number of PDN nodes on net VSS = 507. [INFO PSM-0064] Number of voltage sources = 1. [INFO PSM-0040] All PDN stripes on net VSS are connected. -[INFO PSM-0006] SPICE file is written at: ./results/gcd_spice_vss.sp. No differences found. No differences found. diff --git a/src/psm/test/gcd_em_test_vdd.ok b/src/psm/test/gcd_em_test_vdd.ok index cd0ebe307f3..e42d0ffd140 100644 --- a/src/psm/test/gcd_em_test_vdd.ok +++ b/src/psm/test/gcd_em_test_vdd.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 624 components and 2752 component-terminals. [INFO ODB-0132] Created 2 special nets and 1248 connections. [INFO ODB-0133] Created 581 nets and 1504 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area. [WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um. [WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um. @@ -24,7 +22,6 @@ [INFO PSM-0040] All PDN stripes on net VDD are connected. [INFO PSM-0001] Reading voltage source file: Vsrc_gcd_vdd.loc. [INFO PSM-0004] EM calculation is enabled. -[INFO PSM-0003] Output current file specified ./results/gcd_em_vdd.rpt. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_gcd_vdd.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [WARNING PSM-0030] VSRC location at (50.000um, 50.000um) and size 20.000um, is not located on an existing power stripe node. Moving to closest node at (68.070um, 53.115um). diff --git a/src/psm/test/gcd_no_vsrc.ok b/src/psm/test/gcd_no_vsrc.ok index 5327b3a8c78..1956de6342f 100644 --- a/src/psm/test/gcd_no_vsrc.ok +++ b/src/psm/test/gcd_no_vsrc.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 624 components and 2752 component-terminals. [INFO ODB-0132] Created 2 special nets and 1248 connections. [INFO ODB-0133] Created 581 nets and 1504 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area. [WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um. [WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um. diff --git a/src/psm/test/gcd_sky130_vdd.ok b/src/psm/test/gcd_sky130_vdd.ok index af097a66e36..3de86b3e4cd 100644 --- a/src/psm/test/gcd_sky130_vdd.ok +++ b/src/psm/test/gcd_sky130_vdd.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130_data/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130_data/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: sky130_data/gcd_sky130hd_floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1143 components and 3273 component-terminals. [INFO ODB-0132] Created 2 special nets and 2286 connections. [INFO ODB-0133] Created 306 nets and 987 connections. -[INFO ODB-0134] Finished DEF file: sky130_data/gcd_sky130hd_floorplan.def [WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area. [WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um. [WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um. diff --git a/src/psm/test/gcd_sky130_vdd.tcl b/src/psm/test/gcd_sky130_vdd.tcl index 019529ae13f..b83d62a1f5f 100644 --- a/src/psm/test/gcd_sky130_vdd.tcl +++ b/src/psm/test/gcd_sky130_vdd.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_lef sky130_data/sky130hd.tlef read_lef sky130_data/sky130hd_std_cell.lef read_def sky130_data/gcd_sky130hd_floorplan.def diff --git a/src/psm/test/gcd_test_vdd.ok b/src/psm/test/gcd_test_vdd.ok index 26b63831442..37af9de6a7c 100644 --- a/src/psm/test/gcd_test_vdd.ok +++ b/src/psm/test/gcd_test_vdd.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 624 components and 2752 component-terminals. [INFO ODB-0132] Created 2 special nets and 1248 connections. [INFO ODB-0133] Created 581 nets and 1504 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area. [WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um. [WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um. @@ -23,7 +21,6 @@ [INFO PSM-0064] Number of voltage sources = 1. [INFO PSM-0040] All PDN stripes on net VDD are connected. [INFO PSM-0001] Reading voltage source file: Vsrc_gcd_vdd.loc. -[INFO PSM-0002] Output voltage file is specified as: ./results/gcd_voltage_vdd.rpt. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_gcd_vdd.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [WARNING PSM-0030] VSRC location at (50.000um, 50.000um) and size 20.000um, is not located on an existing power stripe node. Moving to closest node at (68.070um, 53.115um). diff --git a/src/psm/test/gcd_vss_no_vsrc.ok b/src/psm/test/gcd_vss_no_vsrc.ok index e36a60917d5..4b93aeea434 100644 --- a/src/psm/test/gcd_vss_no_vsrc.ok +++ b/src/psm/test/gcd_vss_no_vsrc.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 624 components and 2752 component-terminals. [INFO ODB-0132] Created 2 special nets and 1248 connections. [INFO ODB-0133] Created 581 nets and 1504 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area. [WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um. [WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um. diff --git a/src/psm/test/gcd_write_sp_test_vdd.ok b/src/psm/test/gcd_write_sp_test_vdd.ok index 828a282ddee..31286869207 100644 --- a/src/psm/test/gcd_write_sp_test_vdd.ok +++ b/src/psm/test/gcd_write_sp_test_vdd.ok @@ -3,20 +3,16 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 134 library cells [INFO ODB-0226] Finished LEF file: Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 624 components and 2752 component-terminals. [INFO ODB-0132] Created 2 special nets and 1248 connections. [INFO ODB-0133] Created 581 nets and 1504 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO PSM-0001] Reading voltage source file: Vsrc_gcd_vdd.loc. -[INFO PSM-0005] Output spice file is specified as: ./results/gcd_spice_vdd.sp. [INFO PSM-0015] Reading location of VDD and VSS sources from Vsrc_gcd_vdd.loc. [INFO PSM-0076] Setting metal node density to be standard cell height times 5. [WARNING PSM-0030] VSRC location at (50.000um, 50.000um) and size 20.000um, is not located on an existing power stripe node. Moving to closest node at (68.070um, 53.115um). [INFO PSM-0031] Number of PDN nodes on net VDD = 604. [INFO PSM-0064] Number of voltage sources = 1. [INFO PSM-0040] All PDN stripes on net VDD are connected. -[INFO PSM-0006] SPICE file is written at: ./results/gcd_spice_vdd.sp. No differences found. diff --git a/src/psm/test/set_resistance.tcl b/src/psm/test/set_resistance.tcl index ced09a21349..d2bc0d057a8 100644 --- a/src/psm/test/set_resistance.tcl +++ b/src/psm/test/set_resistance.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" ################################################################### set tech [ord::get_db_tech] diff --git a/src/rcx/test/45_gcd.ok b/src/rcx/test/45_gcd.ok index 69c2272d0c3..d49905458d5 100644 --- a/src/rcx/test/45_gcd.ok +++ b/src/rcx/test/45_gcd.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: 45_gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 1820 components and 4618 component-terminals. [INFO ODB-0132] Created 2 special nets and 3640 connections. [INFO ODB-0133] Created 350 nets and 978 connections. -[INFO ODB-0134] Finished DEF file: 45_gcd.def [INFO RCX-0431] Defined process_corner X with ext_model_index 0 [INFO RCX-0029] Defined extraction corner X [INFO RCX-0008] extracting parasitics of gcd ... diff --git a/src/rcx/test/45_via_resistance.tcl b/src/rcx/test/45_via_resistance.tcl index 6ced043102b..2ca175e8370 100644 --- a/src/rcx/test/45_via_resistance.tcl +++ b/src/rcx/test/45_via_resistance.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" ################################################################### set tech [ord::get_db_tech] diff --git a/src/rcx/test/ext_pattern.ok b/src/rcx/test/ext_pattern.ok index 6cf4fd33db0..f9943fa1239 100644 --- a/src/rcx/test/ext_pattern.ok +++ b/src/rcx/test/ext_pattern.ok @@ -2,11 +2,9 @@ [INFO ODB-0223] Created 13 technology layers [INFO ODB-0224] Created 25 technology vias [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs.tlef -[INFO ODB-0127] Reading DEF file: generate_pattern.defok [INFO ODB-0128] Design: blk [INFO ODB-0130] Created 141104 pins. [INFO ODB-0133] Created 70552 nets and 0 connections. -[INFO ODB-0134] Finished DEF file: generate_pattern.defok [INFO RCX-0431] Defined process_corner X with ext_model_index 0 [INFO RCX-0029] Defined extraction corner X [INFO RCX-0008] extracting parasitics of blk ... diff --git a/src/rcx/test/gcd.ok b/src/rcx/test/gcd.ok index 01efbe43a99..963b2597157 100644 --- a/src/rcx/test/gcd.ok +++ b/src/rcx/test/gcd.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 8171 components and 33894 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 411 nets and 1210 connections. -[INFO ODB-0134] Finished DEF file: gcd.def [INFO RCX-0431] Defined process_corner X with ext_model_index 0 [INFO RCX-0029] Defined extraction corner X [INFO RCX-0008] extracting parasitics of gcd ... diff --git a/src/rmp/test/blif_reader.ok b/src/rmp/test/blif_reader.ok index 55923ac388e..e0e31c44b28 100644 --- a/src/rmp/test/blif_reader.ok +++ b/src/rmp/test/blif_reader.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_in_out.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 10 pins. [INFO ODB-0131] Created 8 components and 40 component-terminals. [INFO ODB-0133] Created 17 nets and 24 connections. -[INFO ODB-0134] Finished DEF file: ./design_in_out.def [INFO RMP-0005] Blif parsed successfully, will destroy 8 existing instances. [INFO RMP-0006] Found 4 inputs, 1 outputs, 0 clocks, 3 combinational gates, 0 registers after parsing the blif file. [INFO RMP-0007] Inserting 3 new instances. diff --git a/src/rmp/test/blif_reader_const.ok b/src/rmp/test/blif_reader_const.ok index 1f5488eb044..ba1b2d5f02b 100644 --- a/src/rmp/test/blif_reader_const.ok +++ b/src/rmp/test/blif_reader_const.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_in_out.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 10 pins. [INFO ODB-0131] Created 8 components and 40 component-terminals. [INFO ODB-0133] Created 17 nets and 24 connections. -[INFO ODB-0134] Finished DEF file: ./design_in_out.def [INFO RMP-0005] Blif parsed successfully, will destroy 8 existing instances. [INFO RMP-0006] Found 2 inputs, 1 outputs, 0 clocks, 5 combinational gates, 0 registers after parsing the blif file. [INFO RMP-0007] Inserting 5 new instances. diff --git a/src/rmp/test/blif_reader_sequential.ok b/src/rmp/test/blif_reader_sequential.ok index f48d35d5dc8..3840b0d34c7 100644 --- a/src/rmp/test/blif_reader_sequential.ok +++ b/src/rmp/test/blif_reader_sequential.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_in_out.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 10 pins. [INFO ODB-0131] Created 8 components and 40 component-terminals. [INFO ODB-0133] Created 17 nets and 24 connections. -[INFO ODB-0134] Finished DEF file: ./design_in_out.def [INFO RMP-0005] Blif parsed successfully, will destroy 8 existing instances. [INFO RMP-0006] Found 4 inputs, 1 outputs, 1 clocks, 3 combinational gates, 1 registers after parsing the blif file. [INFO RMP-0007] Inserting 4 new instances. diff --git a/src/rmp/test/blif_writer.ok b/src/rmp/test/blif_writer.ok index eed9210acdc..7359e303a08 100644 --- a/src/rmp/test/blif_writer.ok +++ b/src/rmp/test/blif_writer.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 5 pins. [INFO ODB-0131] Created 3 components and 15 component-terminals. [INFO ODB-0133] Created 7 nets and 9 connections. -[INFO ODB-0134] Finished DEF file: ./design.def [INFO RMP-0002] Blif writer successfully dumped file with 3 instances. No differences found. diff --git a/src/rmp/test/blif_writer_consts.ok b/src/rmp/test/blif_writer_consts.ok index 8ebd4fafc99..a0ada6cf3d6 100644 --- a/src/rmp/test/blif_writer_consts.ok +++ b/src/rmp/test/blif_writer_consts.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_const.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 5 components and 21 component-terminals. [INFO ODB-0133] Created 7 nets and 11 connections. -[INFO ODB-0134] Finished DEF file: ./design_const.def [INFO RMP-0002] Blif writer successfully dumped file with 3 instances. No differences found. diff --git a/src/rmp/test/blif_writer_hanging.ok b/src/rmp/test/blif_writer_hanging.ok index 3116fec08be..45dc5c9019b 100644 --- a/src/rmp/test/blif_writer_hanging.ok +++ b/src/rmp/test/blif_writer_hanging.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_hanging.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 5 pins. [INFO ODB-0131] Created 3 components and 15 component-terminals. [INFO ODB-0133] Created 6 nets and 8 connections. -[INFO ODB-0134] Finished DEF file: ./design_hanging.def [INFO RMP-0002] Blif writer successfully dumped file with 3 instances. No differences found. diff --git a/src/rmp/test/blif_writer_input_output.ok b/src/rmp/test/blif_writer_input_output.ok index e78546ea11c..db842c88532 100644 --- a/src/rmp/test/blif_writer_input_output.ok +++ b/src/rmp/test/blif_writer_input_output.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_in_out.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 10 pins. [INFO ODB-0131] Created 8 components and 40 component-terminals. [INFO ODB-0133] Created 17 nets and 24 connections. -[INFO ODB-0134] Finished DEF file: ./design_in_out.def [INFO RMP-0002] Blif writer successfully dumped file with 3 instances. No differences found. diff --git a/src/rmp/test/blif_writer_sequential.ok b/src/rmp/test/blif_writer_sequential.ok index 5a1621329cc..1552de7c6d1 100644 --- a/src/rmp/test/blif_writer_sequential.ok +++ b/src/rmp/test/blif_writer_sequential.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: ./Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./design_sequential.def [INFO ODB-0128] Design: counter [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 4 components and 21 component-terminals. [INFO ODB-0133] Created 9 nets and 12 connections. -[INFO ODB-0134] Finished DEF file: ./design_sequential.def [INFO RMP-0002] Blif writer successfully dumped file with 4 instances. No differences found. diff --git a/src/rmp/test/const_cell_removal.ok b/src/rmp/test/const_cell_removal.ok index e978b8c96d2..8ce6a8dbdf1 100644 --- a/src/rmp/test/const_cell_removal.ok +++ b/src/rmp/test/const_cell_removal.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: rcon.def [INFO ODB-0128] Design: aes_rcon [INFO ODB-0130] Created 34 pins. [INFO ODB-0131] Created 82 components and 406 component-terminals. [INFO ODB-0133] Created 103 nets and 242 connections. -[INFO ODB-0134] Finished DEF file: rcon.def Design area 128 u^2 100% utilization. Removed 27 instances with constant outputs. Number of paths for restructure are 32 diff --git a/src/rmp/test/const_cell_removal.tcl b/src/rmp/test/const_cell_removal.tcl index 18b19b3b5f2..77271026c9d 100644 --- a/src/rmp/test/const_cell_removal.tcl +++ b/src/rmp/test/const_cell_removal.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef read_def rcon.def diff --git a/src/rmp/test/gcd_restructure.ok b/src/rmp/test/gcd_restructure.ok index e7d67367414..b55ff805e73 100644 --- a/src/rmp/test/gcd_restructure.ok +++ b/src/rmp/test/gcd_restructure.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_placed.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 571 components and 2554 component-terminals. [INFO ODB-0132] Created 5 special nets and 1142 connections. [INFO ODB-0133] Created 528 nets and 1412 connections. -[INFO ODB-0134] Finished DEF file: gcd_placed.def [WARNING STA-0354] set_input_delay relative to a clock defined on the same port/pin not allowed. worst slack 1.29 Design area 670 u^2 10% utilization. diff --git a/src/rmp/test/gcd_restructure.tcl b/src/rmp/test/gcd_restructure.tcl index 0a8937ccf56..cef4c070302 100644 --- a/src/rmp/test/gcd_restructure.tcl +++ b/src/rmp/test/gcd_restructure.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef read_def gcd_placed.def diff --git a/src/rsz/test/buffer_ports1.ok b/src/rsz/test/buffer_ports1.ok index 865917640c9..ab89907a928 100644 --- a/src/rsz/test/buffer_ports1.ok +++ b/src/rsz/test/buffer_ports1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: buffer_ports1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 8 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 12 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: buffer_ports1.def [INFO RSZ-0027] Inserted 2 input buffers. [INFO RSZ-0028] Inserted 1 output buffers. No differences found. diff --git a/src/rsz/test/buffer_ports3.ok b/src/rsz/test/buffer_ports3.ok index b1f4b976445..1968a0739a2 100644 --- a/src/rsz/test/buffer_ports3.ok +++ b/src/rsz/test/buffer_ports3.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: bus1.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: bus1.lef -[INFO ODB-0127] Reading DEF file: bus1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 8 pins. [INFO ODB-0131] Created 1 components and 10 component-terminals. [INFO ODB-0133] Created 8 nets and 8 connections. -[INFO ODB-0134] Finished DEF file: bus1.def [INFO RSZ-0027] Inserted 4 input buffers. [INFO RSZ-0028] Inserted 4 output buffers. diff --git a/src/rsz/test/buffer_ports3.tcl b/src/rsz/test/buffer_ports3.tcl index cb0fe10e455..917ae2dbe52 100644 --- a/src/rsz/test/buffer_ports3.tcl +++ b/src/rsz/test/buffer_ports3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # buffer_ports lef macro bus pins read_liberty Nangate45/Nangate45_typ.lib read_liberty bus1.lib diff --git a/src/rsz/test/buffer_ports4.ok b/src/rsz/test/buffer_ports4.ok index 26eb3fed2f2..0ffcae5ba3e 100644 --- a/src/rsz/test/buffer_ports4.ok +++ b/src/rsz/test/buffer_ports4.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/buffer_ports4.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 250 components and 2000 component-terminals. [INFO ODB-0132] Created 2 special nets and 500 connections. [INFO ODB-0133] Created 2 nets and 500 connections. -[INFO ODB-0134] Finished DEF file: ./results/buffer_ports4.def [INFO RSZ-0027] Inserted 1 input buffers. max slew diff --git a/src/rsz/test/buffer_ports5.ok b/src/rsz/test/buffer_ports5.ok index 7a4b9d39d97..7966a0ce1b3 100644 --- a/src/rsz/test/buffer_ports5.ok +++ b/src/rsz/test/buffer_ports5.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg2.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg2.def [INFO RSZ-0027] Inserted 2 input buffers. [INFO RSZ-0028] Inserted 1 output buffers. diff --git a/src/rsz/test/buffer_ports5.tcl b/src/rsz/test/buffer_ports5.tcl index 66b85222d20..0a4ab1d6099 100644 --- a/src/rsz/test/buffer_ports5.tcl +++ b/src/rsz/test/buffer_ports5.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # read_lef before read_liberty read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/rsz/test/buffer_ports6.ok b/src/rsz/test/buffer_ports6.ok index 3248b9902fb..be9ffc6c69b 100644 --- a/src/rsz/test/buffer_ports6.ok +++ b/src/rsz/test/buffer_ports6.ok @@ -3,9 +3,7 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: buffer_ports6.def [INFO ODB-0128] Design: buffer_ports6 [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 7 component-terminals. [INFO ODB-0132] Created 4 special nets and 4 connections. -[INFO ODB-0134] Finished DEF file: buffer_ports6.def diff --git a/src/rsz/test/buffer_ports7.ok b/src/rsz/test/buffer_ports7.ok index ce7e7c02077..38dd7c919a0 100644 --- a/src/rsz/test/buffer_ports7.ok +++ b/src/rsz/test/buffer_ports7.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: buffer_ports7.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 2 components and 13 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 4 nets and 5 connections. -[INFO ODB-0134] Finished DEF file: buffer_ports7.def No differences found. diff --git a/src/rsz/test/fanin_fanout1.ok b/src/rsz/test/fanin_fanout1.ok index 012942166b9..0ee19670890 100644 --- a/src/rsz/test/fanin_fanout1.ok +++ b/src/rsz/test/fanin_fanout1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: fanin_fanout1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 9 components and 45 component-terminals. [INFO ODB-0132] Created 2 special nets and 18 connections. [INFO ODB-0133] Created 10 nets and 22 connections. -[INFO ODB-0134] Finished DEF file: fanin_fanout1.def u1/A u1/Z u2/A1 diff --git a/src/rsz/test/fanin_fanout1.tcl b/src/rsz/test/fanin_fanout1.tcl index 9a2499c2198..ead9a326f0b 100644 --- a/src/rsz/test/fanin_fanout1.tcl +++ b/src/rsz/test/fanin_fanout1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # find_fanin_fanouts (API for logic resynthesis) read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/gcd_resize.ok b/src/rsz/test/gcd_resize.ok index e0eb93c6e77..fa902c7ab4e 100644 --- a/src/rsz/test/gcd_resize.ok +++ b/src/rsz/test/gcd_resize.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_nangate45_placed.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 571 components and 2554 component-terminals. [INFO ODB-0132] Created 5 special nets and 1142 connections. [INFO ODB-0133] Created 528 nets and 1412 connections. -[INFO ODB-0134] Finished DEF file: gcd_nangate45_placed.def worst slack 1.33 [INFO RSZ-0027] Inserted 35 input buffers. [INFO RSZ-0028] Inserted 18 output buffers. diff --git a/src/rsz/test/gcd_resize.tcl b/src/rsz/test/gcd_resize.tcl index d5f85447dbb..c7d690d13d5 100644 --- a/src/rsz/test/gcd_resize.tcl +++ b/src/rsz/test/gcd_resize.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # gcd full meal deal read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/hi_fanout.tcl b/src/rsz/test/hi_fanout.tcl index 921ef0fe00e..0cbef8ba424 100644 --- a/src/rsz/test/hi_fanout.tcl +++ b/src/rsz/test/hi_fanout.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # write_hi_fanout def set header {VERSION 5.8 ; diff --git a/src/rsz/test/make_parasitics1.ok b/src/rsz/test/make_parasitics1.ok index d57d764e6e2..036d45f1261 100644 --- a/src/rsz/test/make_parasitics1.ok +++ b/src/rsz/test/make_parasitics1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg3.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 8 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg3.def Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/make_parasitics1.tcl b/src/rsz/test/make_parasitics1.tcl index 401d33e1a5c..b55f50d6404 100644 --- a/src/rsz/test/make_parasitics1.tcl +++ b/src/rsz/test/make_parasitics1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # estimate_parasitics read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/rsz/test/make_parasitics2.ok b/src/rsz/test/make_parasitics2.ok index 4df21c40354..0a2e1d7fa24 100644 --- a/src/rsz/test/make_parasitics2.ok +++ b/src/rsz/test/make_parasitics2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg3.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 8 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg3.def Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/make_parasitics2.tcl b/src/rsz/test/make_parasitics2.tcl index a4aed09bc1a..b6696af9e6c 100644 --- a/src/rsz/test/make_parasitics2.tcl +++ b/src/rsz/test/make_parasitics2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # set_wire_rc -layer read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/rsz/test/make_parasitics3.ok b/src/rsz/test/make_parasitics3.ok index edf0b920715..4c5370842c1 100644 --- a/src/rsz/test/make_parasitics3.ok +++ b/src/rsz/test/make_parasitics3.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg6.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 8 components and 39 component-terminals. [INFO ODB-0132] Created 2 special nets and 16 connections. [INFO ODB-0133] Created 10 nets and 20 connections. -[INFO ODB-0134] Finished DEF file: reg6.def Startpoint: r2 (rising edge-triggered flip-flop clocked by clk) Endpoint: r3 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/make_parasitics3.tcl b/src/rsz/test/make_parasitics3.tcl index 92071d50a8c..772d938d1de 100644 --- a/src/rsz/test/make_parasitics3.tcl +++ b/src/rsz/test/make_parasitics3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # estimate_parasitics propagated clock read_lef Nangate45/Nangate45.lef read_liberty Nangate45/Nangate45_typ.lib diff --git a/src/rsz/test/make_parasitics4.ok b/src/rsz/test/make_parasitics4.ok index 04a48125f6d..75482c7c367 100644 --- a/src/rsz/test/make_parasitics4.ok +++ b/src/rsz/test/make_parasitics4.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: make_parasitics4.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 16 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: make_parasitics4.def Net in1 Pin capacitance: 2.20 Wire capacitance: 0.00 diff --git a/src/rsz/test/make_parasitics4.tcl b/src/rsz/test/make_parasitics4.tcl index 1c8dcb5df97..44242b34544 100644 --- a/src/rsz/test/make_parasitics4.tcl +++ b/src/rsz/test/make_parasitics4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # estimate_parasitics input/output pads read_liberty Nangate45/Nangate45_typ.lib read_liberty pad.lib diff --git a/src/rsz/test/make_parasitics5.ok b/src/rsz/test/make_parasitics5.ok index 103c43fb832..8a5ca3255f1 100644 --- a/src/rsz/test/make_parasitics5.ok +++ b/src/rsz/test/make_parasitics5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg6.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 8 components and 39 component-terminals. [INFO ODB-0132] Created 2 special nets and 16 connections. [INFO ODB-0133] Created 10 nets and 20 connections. -[INFO ODB-0134] Finished DEF file: reg6.def Net r1q Pin capacitance: 0.92-0.92 Wire capacitance: 9.76-9.76 diff --git a/src/rsz/test/make_parasitics5.tcl b/src/rsz/test/make_parasitics5.tcl index 4aec03915aa..288c81b32a8 100644 --- a/src/rsz/test/make_parasitics5.tcl +++ b/src/rsz/test/make_parasitics5.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # 2 corners with set_wire_rc define_corners ss ff read_liberty -corner ss Nangate45/Nangate45_slow.lib diff --git a/src/rsz/test/make_parasitics6.ok b/src/rsz/test/make_parasitics6.ok index 103c43fb832..8a5ca3255f1 100644 --- a/src/rsz/test/make_parasitics6.ok +++ b/src/rsz/test/make_parasitics6.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg6.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 8 components and 39 component-terminals. [INFO ODB-0132] Created 2 special nets and 16 connections. [INFO ODB-0133] Created 10 nets and 20 connections. -[INFO ODB-0134] Finished DEF file: reg6.def Net r1q Pin capacitance: 0.92-0.92 Wire capacitance: 9.76-9.76 diff --git a/src/rsz/test/make_parasitics6.tcl b/src/rsz/test/make_parasitics6.tcl index d81e5a59666..f901ccf3499 100644 --- a/src/rsz/test/make_parasitics6.tcl +++ b/src/rsz/test/make_parasitics6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # 2 corners with set_layer_rc define_corners ss ff read_liberty -corner ss Nangate45/Nangate45_slow.lib diff --git a/src/rsz/test/remove_buffers1.ok b/src/rsz/test/remove_buffers1.ok index 58fc0c9fefc..05fc9aa0875 100644 --- a/src/rsz/test/remove_buffers1.ok +++ b/src/rsz/test/remove_buffers1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: remove_buffers1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 4 components and 16 component-terminals. [INFO ODB-0132] Created 2 special nets and 8 connections. [INFO ODB-0133] Created 5 nets and 8 connections. -[INFO ODB-0134] Finished DEF file: remove_buffers1.def Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/remove_buffers2.ok b/src/rsz/test/remove_buffers2.ok index 3004c104f90..13f2e800b4c 100644 --- a/src/rsz/test/remove_buffers2.ok +++ b/src/rsz/test/remove_buffers2.ok @@ -3,14 +3,12 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: remove_buffers2.def [INFO ODB-0128] Design: top [WARNING ODB-0100] error: netlist component-pin (i1, Z) is not defined [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 5 connections. -[INFO ODB-0134] Finished DEF file: remove_buffers2.def Startpoint: b1/A (internal pin) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/repair_cap1.ok b/src/rsz/test/repair_cap1.ok index 102e04bf112..8dbe6debe84 100644 --- a/src/rsz/test/repair_cap1.ok +++ b/src/rsz/test/repair_cap1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_cap1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 61 components and 366 component-terminals. [INFO ODB-0132] Created 2 special nets and 122 connections. [INFO ODB-0133] Created 2 nets and 122 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_cap1.def max capacitance Pin Limit Cap Slack diff --git a/src/rsz/test/repair_cap2.ok b/src/rsz/test/repair_cap2.ok index f9a6686504c..8dbe6debe84 100644 --- a/src/rsz/test/repair_cap2.ok +++ b/src/rsz/test/repair_cap2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_cap2.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 61 components and 366 component-terminals. [INFO ODB-0132] Created 2 special nets and 122 connections. [INFO ODB-0133] Created 2 nets and 122 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_cap2.def max capacitance Pin Limit Cap Slack diff --git a/src/rsz/test/repair_cap3.ok b/src/rsz/test/repair_cap3.ok index 8b67613dd52..3171c94134a 100644 --- a/src/rsz/test/repair_cap3.ok +++ b/src/rsz/test/repair_cap3.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 105 components and 526 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 105 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew1.def Found 105 slew violations Found 1 cap violations [INFO RSZ-0058] Using max wire length 2393um. diff --git a/src/rsz/test/repair_cap3.tcl b/src/rsz/test/repair_cap3.tcl index a2c08fd3861..56168137fed 100644 --- a/src/rsz/test/repair_cap3.tcl +++ b/src/rsz/test/repair_cap3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design -max_cap_margin source "max_slew_cap.tcl" diff --git a/src/rsz/test/repair_clk_inverters1.ok b/src/rsz/test/repair_clk_inverters1.ok index 481f5c4dcc8..a14bdcb3da8 100644 --- a/src/rsz/test/repair_clk_inverters1.ok +++ b/src/rsz/test/repair_clk_inverters1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_clk_inverters1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 6 components and 31 component-terminals. [INFO ODB-0132] Created 2 special nets and 12 connections. [INFO ODB-0133] Created 8 nets and 16 connections. -[INFO ODB-0134] Finished DEF file: repair_clk_inverters1.def Net clk1 Pin capacitance: 3.96-4.35 Wire capacitance: 1.15-1.15 diff --git a/src/rsz/test/repair_clk_inverters1.tcl b/src/rsz/test/repair_clk_inverters1.tcl index 3db43f80358..b2ddd98621f 100644 --- a/src/rsz/test/repair_clk_inverters1.tcl +++ b/src/rsz/test/repair_clk_inverters1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_clock_inverters read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_clk_nets1.ok b/src/rsz/test/repair_clk_nets1.ok index e03dd49656f..132dfccd4c1 100644 --- a/src/rsz/test/repair_clk_nets1.ok +++ b/src/rsz/test/repair_clk_nets1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire1.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire1.def [WARNING RSZ-0065] max wire length less than 720u increases wire delays. [INFO RSZ-0047] Found 1 long wires. [INFO RSZ-0048] Inserted 3 buffers in 1 nets. diff --git a/src/rsz/test/repair_clk_nets1.tcl b/src/rsz/test/repair_clk_nets1.tcl index b1f0d8eacf8..f5a84db6e94 100644 --- a/src/rsz/test/repair_clk_nets1.tcl +++ b/src/rsz/test/repair_clk_nets1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_clock_nets 1 wire read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_design1.ok b/src/rsz/test/repair_design1.ok index 70573652ebc..a889c5bc597 100644 --- a/src/rsz/test/repair_design1.ok +++ b/src/rsz/test/repair_design1.ok @@ -4,13 +4,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 11 components and 66 component-terminals. [INFO ODB-0132] Created 2 special nets and 22 connections. [INFO ODB-0133] Created 2 nets and 22 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew1.def [INFO RSZ-0058] Using max wire length 850um. [INFO RSZ-0034] Found 1 slew violations. max slew diff --git a/src/rsz/test/repair_design2.ok b/src/rsz/test/repair_design2.ok index 1fcb5620c8a..52c10b4695c 100644 --- a/src/rsz/test/repair_design2.ok +++ b/src/rsz/test/repair_design2.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_design2.def [INFO ODB-0128] Design: shorted_outputs [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 3 components and 14 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_design2.def [INFO RSZ-0058] Using max wire length 2393um. [INFO RSZ-0039] Resized 3 instances. diff --git a/src/rsz/test/repair_design3.ok b/src/rsz/test/repair_design3.ok index f6ef0a4503c..9e1f67e6774 100644 --- a/src/rsz/test/repair_design3.ok +++ b/src/rsz/test/repair_design3.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_design3.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 1001 components and 5004 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 1001 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_design3.def [INFO RSZ-0058] Using max wire length 2393um. [INFO RSZ-0039] Resized 1000 instances. diff --git a/src/rsz/test/repair_design4.ok b/src/rsz/test/repair_design4.ok index 62e227797bf..c831f1287b1 100644 --- a/src/rsz/test/repair_design4.ok +++ b/src/rsz/test/repair_design4.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_fanout1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 36 components and 216 component-terminals. [INFO ODB-0132] Created 2 special nets and 72 connections. [INFO ODB-0133] Created 2 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_fanout1.def max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_design5.ok b/src/rsz/test/repair_design5.ok index 02b14f60f2f..765534b88a8 100644 --- a/src/rsz/test/repair_design5.ok +++ b/src/rsz/test/repair_design5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_fanout1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 36 components and 216 component-terminals. [INFO ODB-0132] Created 2 special nets and 72 connections. [INFO ODB-0133] Created 2 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_fanout1.def [INFO RSZ-0058] Using max wire length 544um. [INFO RSZ-0035] Found 1 fanout violations. [INFO RSZ-0038] Inserted 4 buffers in 1 nets. diff --git a/src/rsz/test/repair_fanout1.ok b/src/rsz/test/repair_fanout1.ok index df38773f886..6b1e137beb9 100644 --- a/src/rsz/test/repair_fanout1.ok +++ b/src/rsz/test/repair_fanout1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_fanout1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 36 components and 216 component-terminals. [INFO ODB-0132] Created 2 special nets and 72 connections. [INFO ODB-0133] Created 2 nets and 72 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_fanout1.def max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_fanout2.ok b/src/rsz/test/repair_fanout2.ok index 171a78c6ef4..29b13e4f8cb 100644 --- a/src/rsz/test/repair_fanout2.ok +++ b/src/rsz/test/repair_fanout2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_fanout2.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 15 components and 105 component-terminals. [INFO ODB-0132] Created 3 special nets and 45 connections. -[INFO ODB-0134] Finished DEF file: repair_fanout2.def [WARNING RSZ-0021] no estimated parasitics. Using wire load models. Net RESET Driver pins diff --git a/src/rsz/test/repair_fanout3.ok b/src/rsz/test/repair_fanout3.ok index 3d779dd6201..f982cfbb197 100644 --- a/src/rsz/test/repair_fanout3.ok +++ b/src/rsz/test/repair_fanout3.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: repair_fanout3.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: repair_fanout3.lef -[INFO ODB-0127] Reading DEF file: repair_fanout3.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 13 components and 78 component-terminals. [INFO ODB-0132] Created 2 special nets and 26 connections. [INFO ODB-0133] Created 2 nets and 26 connections. -[INFO ODB-0134] Finished DEF file: repair_fanout3.def max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_fanout4.ok b/src/rsz/test/repair_fanout4.ok index c04399514ce..f42598a1f60 100644 --- a/src/rsz/test/repair_fanout4.ok +++ b/src/rsz/test/repair_fanout4.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_fanout4.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 35 components and 140 component-terminals. [INFO ODB-0132] Created 2 special nets and 70 connections. [INFO ODB-0133] Created 2 nets and 36 connections. -[INFO ODB-0134] Finished DEF file: repair_fanout4.def max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_fanout5.ok b/src/rsz/test/repair_fanout5.ok index f1b24ce603b..ede60d386e0 100644 --- a/src/rsz/test/repair_fanout5.ok +++ b/src/rsz/test/repair_fanout5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_fanout4.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 35 components and 140 component-terminals. [INFO ODB-0132] Created 2 special nets and 70 connections. [INFO ODB-0133] Created 2 nets and 36 connections. -[INFO ODB-0134] Finished DEF file: repair_fanout4.def max fanout Pin Limit Fanout Slack diff --git a/src/rsz/test/repair_fanout6.ok b/src/rsz/test/repair_fanout6.ok index b84f42e3208..a07b33ea0bb 100644 --- a/src/rsz/test/repair_fanout6.ok +++ b/src/rsz/test/repair_fanout6.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_fanout6.def [INFO ODB-0128] Design: test [INFO ODB-0130] Created 8002 pins. [INFO ODB-0131] Created 8001 components and 40005 component-terminals. [INFO ODB-0133] Created 8003 nets and 24003 connections. -[INFO ODB-0134] Finished DEF file: repair_fanout6.def [INFO RSZ-0035] Found 1 fanout violations. [INFO RSZ-0038] Inserted 508 buffers in 1 nets. [INFO RSZ-0039] Resized 509 instances. diff --git a/src/rsz/test/repair_fanout6.tcl b/src/rsz/test/repair_fanout6.tcl index ba4920618a7..5d416ecedf2 100644 --- a/src/rsz/test/repair_fanout6.tcl +++ b/src/rsz/test/repair_fanout6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # fanout 8000 max_fanout 20 stress test # modified to use large default max_transition, max_capacitance read_liberty repair_fanout6.lib diff --git a/src/rsz/test/repair_hold1.ok b/src/rsz/test/repair_hold1.ok index d176a46df99..e0c5fc012f6 100644 --- a/src/rsz/test/repair_hold1.ok +++ b/src/rsz/test/repair_hold1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_hold1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 13 components and 59 component-terminals. [INFO ODB-0133] Created 16 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold1.def (clk ^) r -0.03:1.91 f -0.04:1.91 [INFO RSZ-0046] Found 1 endpoints with hold violations. [INFO RSZ-0032] Inserted 2 hold buffers. diff --git a/src/rsz/test/repair_hold10.ok b/src/rsz/test/repair_hold10.ok index c67888b4ec4..4175f5c36b7 100644 --- a/src/rsz/test/repair_hold10.ok +++ b/src/rsz/test/repair_hold10.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_hold10.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 15 components and 68 component-terminals. [INFO ODB-0133] Created 13 nets and 29 connections. -[INFO ODB-0134] Finished DEF file: repair_hold10.def worst slack -3.23 [INFO RSZ-0046] Found 2 endpoints with hold violations. [INFO RSZ-0032] Inserted 6 hold buffers. diff --git a/src/rsz/test/repair_hold11.ok b/src/rsz/test/repair_hold11.ok index 508faddd56d..38ea98e2584 100644 --- a/src/rsz/test/repair_hold11.ok +++ b/src/rsz/test/repair_hold11.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_hold1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 13 components and 59 component-terminals. [INFO ODB-0133] Created 16 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold1.def worst slack -0.26 worst slack 1.27 [INFO RSZ-0046] Found 3 endpoints with hold violations. diff --git a/src/rsz/test/repair_hold12.ok b/src/rsz/test/repair_hold12.ok index 869aeb9a1e9..309ce899324 100644 --- a/src/rsz/test/repair_hold12.ok +++ b/src/rsz/test/repair_hold12.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_hold1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 13 components and 59 component-terminals. [INFO ODB-0133] Created 16 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold1.def (clk ^) r -0.04:INF f -0.04:INF [INFO RSZ-0046] Found 2 endpoints with hold violations. [INFO RSZ-0032] Inserted 4 hold buffers. diff --git a/src/rsz/test/repair_hold2.ok b/src/rsz/test/repair_hold2.ok index 7fc671935aa..0b5716da053 100644 --- a/src/rsz/test/repair_hold2.ok +++ b/src/rsz/test/repair_hold2.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_hold1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 13 components and 59 component-terminals. [INFO ODB-0133] Created 16 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold1.def Startpoint: in2 (input port clocked by clk) Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/repair_hold3.ok b/src/rsz/test/repair_hold3.ok index 021c601373d..0270355b2d0 100644 --- a/src/rsz/test/repair_hold3.ok +++ b/src/rsz/test/repair_hold3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_hold3.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 13 components and 60 component-terminals. [INFO ODB-0133] Created 11 nets and 26 connections. -[INFO ODB-0134] Finished DEF file: repair_hold3.def worst slack -0.03 worst slack 1.95 [INFO RSZ-0046] Found 2 endpoints with hold violations. diff --git a/src/rsz/test/repair_hold4.ok b/src/rsz/test/repair_hold4.ok index 4acdfaa8a9b..94654e0e084 100644 --- a/src/rsz/test/repair_hold4.ok +++ b/src/rsz/test/repair_hold4.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_hold4.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 15 components and 98 component-terminals. [INFO ODB-0133] Created 13 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold4.def worst slack -0.14 worst slack 1.79 [INFO RSZ-0046] Found 2 endpoints with hold violations. diff --git a/src/rsz/test/repair_hold5.ok b/src/rsz/test/repair_hold5.ok index 984c82737a2..3853376f40b 100644 --- a/src/rsz/test/repair_hold5.ok +++ b/src/rsz/test/repair_hold5.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_hold4.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 15 components and 98 component-terminals. [INFO ODB-0133] Created 13 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold4.def (clk ^) r -0.14:2.03 f -0.05:2.01 (clk ^) r -0.07:-0.22 f 0.02:-0.26 (clk ^) r 0.05:1.85 f 0.16:1.79 diff --git a/src/rsz/test/repair_hold6.ok b/src/rsz/test/repair_hold6.ok index 62e6844656a..00444c3be12 100644 --- a/src/rsz/test/repair_hold6.ok +++ b/src/rsz/test/repair_hold6.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_hold4.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 15 components and 98 component-terminals. [INFO ODB-0133] Created 13 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold4.def (clk ^) r -0.14:2.03 f -0.05:2.01 (clk ^) r -0.07:1.96 f 0.02:1.93 (clk ^) r 0.05:1.85 f 0.16:1.79 diff --git a/src/rsz/test/repair_hold7.ok b/src/rsz/test/repair_hold7.ok index f276b1a5ac8..0b2f9ca2a5a 100644 --- a/src/rsz/test/repair_hold7.ok +++ b/src/rsz/test/repair_hold7.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_nangate45_placed.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 571 components and 2554 component-terminals. [INFO ODB-0132] Created 5 special nets and 1142 connections. [INFO ODB-0133] Created 528 nets and 1412 connections. -[INFO ODB-0134] Finished DEF file: gcd_nangate45_placed.def Design area 670 u^2 10% utilization. worst slack 0.15 worst slack 1.33 diff --git a/src/rsz/test/repair_hold7.tcl b/src/rsz/test/repair_hold7.tcl index 9c38e912d1b..ca47e568542 100644 --- a/src/rsz/test/repair_hold7.tcl +++ b/src/rsz/test/repair_hold7.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_timing -hold -max_utilization read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_hold8.ok b/src/rsz/test/repair_hold8.ok index d20ed5cabe0..3765b259ed6 100644 --- a/src/rsz/test/repair_hold8.ok +++ b/src/rsz/test/repair_hold8.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_hold1.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 13 components and 59 component-terminals. [INFO ODB-0133] Created 16 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_hold1.def worst slack -0.09 worst slack 1.84 [INFO RSZ-0046] Found 4 endpoints with hold violations. diff --git a/src/rsz/test/repair_hold9.ok b/src/rsz/test/repair_hold9.ok index 94ce5f96cc8..5de4e4d3e89 100644 --- a/src/rsz/test/repair_hold9.ok +++ b/src/rsz/test/repair_hold9.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_nangate45_placed.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 571 components and 2554 component-terminals. [INFO ODB-0132] Created 5 special nets and 1142 connections. [INFO ODB-0133] Created 528 nets and 1412 connections. -[INFO ODB-0134] Finished DEF file: gcd_nangate45_placed.def Design area 670 u^2 10% utilization. [INFO RSZ-0046] Found 35 endpoints with hold violations. [WARNING RSZ-0064] Unable to repair all hold checks within margin. diff --git a/src/rsz/test/repair_hold9.tcl b/src/rsz/test/repair_hold9.tcl index 1aee9b74a45..8badcfd59bb 100644 --- a/src/rsz/test/repair_hold9.tcl +++ b/src/rsz/test/repair_hold9.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_timing -hold -max_buffer_percent read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_setup1.ok b/src/rsz/test/repair_setup1.ok index cdb29e36fbd..cb83373010a 100644 --- a/src/rsz/test/repair_setup1.ok +++ b/src/rsz/test/repair_setup1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_setup1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 17 components and 92 component-terminals. [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_setup1.def Startpoint: r1 (rising edge-triggered flip-flop clocked by clk) Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/repair_setup1.tcl b/src/rsz/test/repair_setup1.tcl index a3e320d15d0..2cf8036cb02 100644 --- a/src/rsz/test/repair_setup1.tcl +++ b/src/rsz/test/repair_setup1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_timing -setup r1/Q 5 loads read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_setup2.ok b/src/rsz/test/repair_setup2.ok index 95a2aeaed95..d58f9aa6082 100644 --- a/src/rsz/test/repair_setup2.ok +++ b/src/rsz/test/repair_setup2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_setup2.def [INFO ODB-0128] Design: td1 [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 3 components and 15 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 7 nets and 9 connections. -[INFO ODB-0134] Finished DEF file: repair_setup2.def worst slack -0.28 [INFO RSZ-0058] Using max wire length 720um. [INFO RSZ-0037] Found 3 long wires. diff --git a/src/rsz/test/repair_setup2.tcl b/src/rsz/test/repair_setup2.tcl index 2c431915e61..b80e8a20256 100644 --- a/src/rsz/test/repair_setup2.tcl +++ b/src/rsz/test/repair_setup2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_timing -setup combinational path read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_setup3.ok b/src/rsz/test/repair_setup3.ok index f28fe7333f1..578beb740f1 100644 --- a/src/rsz/test/repair_setup3.ok +++ b/src/rsz/test/repair_setup3.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_setup3.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 6 components and 29 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 6 nets and 13 connections. -[INFO ODB-0134] Finished DEF file: repair_setup3.def [INFO RSZ-0041] Resized 2 instances. [WARNING RSZ-0062] Unable to repair all setup violations. diff --git a/src/rsz/test/repair_setup4.ok b/src/rsz/test/repair_setup4.ok index 35fad19a7db..b11ec73fbf6 100644 --- a/src/rsz/test/repair_setup4.ok +++ b/src/rsz/test/repair_setup4.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_setup1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 17 components and 92 component-terminals. [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_setup1.def Startpoint: r1 (rising edge-triggered flip-flop clocked by clk) Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/repair_setup4.tcl b/src/rsz/test/repair_setup4.tcl index 0d90861d321..20f303af418 100644 --- a/src/rsz/test/repair_setup4.tcl +++ b/src/rsz/test/repair_setup4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_timing -setup 2 corners define_corners fast slow read_liberty -corner slow Nangate45/Nangate45_slow.lib diff --git a/src/rsz/test/repair_setup5.ok b/src/rsz/test/repair_setup5.ok index 37777564c95..66b0be900f1 100644 --- a/src/rsz/test/repair_setup5.ok +++ b/src/rsz/test/repair_setup5.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_setup5.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 5 components and 20 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 6 nets and 10 connections. -[INFO ODB-0134] Finished DEF file: repair_setup5.def worst slack -1.88 [INFO RSZ-0041] Resized 15 instances. worst slack 0.09 diff --git a/src/rsz/test/repair_setup5.tcl b/src/rsz/test/repair_setup5.tcl index b266122c627..8e6a2ea770a 100644 --- a/src/rsz/test/repair_setup5.tcl +++ b/src/rsz/test/repair_setup5.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # buffer chain with set_max_delay read_liberty sky130hd/sky130hd_tt.lib read_lef sky130hd/sky130hd.tlef diff --git a/src/rsz/test/repair_setup6.ok b/src/rsz/test/repair_setup6.ok index a389a43fa28..68e2977a123 100644 --- a/src/rsz/test/repair_setup6.ok +++ b/src/rsz/test/repair_setup6.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_setup1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 17 components and 92 component-terminals. [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_setup1.def [INFO IFP-0001] Added 857 rows of 210 sites. Placement Analysis --------------------------------- diff --git a/src/rsz/test/repair_setup6.tcl b/src/rsz/test/repair_setup6.tcl index d53147eebfb..6b07a15685b 100644 --- a/src/rsz/test/repair_setup6.tcl +++ b/src/rsz/test/repair_setup6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_timing -setup with global route parasitics read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_slew1.ok b/src/rsz/test/repair_slew1.ok index 9a0a31d5037..b14f7311889 100644 --- a/src/rsz/test/repair_slew1.ok +++ b/src/rsz/test/repair_slew1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 21 components and 126 component-terminals. [INFO ODB-0132] Created 2 special nets and 42 connections. [INFO ODB-0133] Created 2 nets and 42 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew1.def Found 21 violations [INFO RSZ-0058] Using max wire length 720um. [INFO RSZ-0039] Resized 1 instances. diff --git a/src/rsz/test/repair_slew10.ok b/src/rsz/test/repair_slew10.ok index d7411b620b9..b178f3c591a 100644 --- a/src/rsz/test/repair_slew10.ok +++ b/src/rsz/test/repair_slew10.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_slew10.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 12 components and 48 component-terminals. [INFO ODB-0132] Created 2 special nets and 24 connections. [INFO ODB-0133] Created 4 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: repair_slew10.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew10.tcl b/src/rsz/test/repair_slew10.tcl index 2dfa0c0d8f7..0c3be8d3499 100644 --- a/src/rsz/test/repair_slew10.tcl +++ b/src/rsz/test/repair_slew10.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design max slew, wire RC -> load slew violation, wire under max length # BUF_X1 cell with max_transition on input read_liberty repair_slew10.lib diff --git a/src/rsz/test/repair_slew11.ok b/src/rsz/test/repair_slew11.ok index 13aba60772b..dcb1a872833 100644 --- a/src/rsz/test/repair_slew11.ok +++ b/src/rsz/test/repair_slew11.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire7.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire7.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew11.tcl b/src/rsz/test/repair_slew11.tcl index 74f182ad4ad..5ff3d664c96 100644 --- a/src/rsz/test/repair_slew11.tcl +++ b/src/rsz/test/repair_slew11.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design max_slew on input port with set_driving_cell read_liberty repair_slew10.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_slew12.ok b/src/rsz/test/repair_slew12.ok index 729fd91d285..f965377b1e8 100644 --- a/src/rsz/test/repair_slew12.ok +++ b/src/rsz/test/repair_slew12.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_slew12.def [INFO ODB-0128] Design: overlapping_pins [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_slew12.def [INFO RSZ-0058] Using max wire length 720um. [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 2 buffers in 1 nets. diff --git a/src/rsz/test/repair_slew13.ok b/src/rsz/test/repair_slew13.ok index bb1789896bf..5f4bc6a9a36 100644 --- a/src/rsz/test/repair_slew13.ok +++ b/src/rsz/test/repair_slew13.ok @@ -8,13 +8,11 @@ [INFO ODB-0222] Reading LEF file: repair_slew13.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: repair_slew13.lef -[INFO ODB-0127] Reading DEF file: repair_slew13.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 8 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 3 nets and 4 connections. -[INFO ODB-0134] Finished DEF file: repair_slew13.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew13.tcl b/src/rsz/test/repair_slew13.tcl index 7e293c36ca8..81894ef1184 100644 --- a/src/rsz/test/repair_slew13.tcl +++ b/src/rsz/test/repair_slew13.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design impossibly small liberty input pin max_transition (ala fakeram) # in1--u1---------u2-out1 read_liberty sky130hd/sky130hd_tt.lib diff --git a/src/rsz/test/repair_slew14.ok b/src/rsz/test/repair_slew14.ok index 68a02de064d..3e1005fc458 100644 --- a/src/rsz/test/repair_slew14.ok +++ b/src/rsz/test/repair_slew14.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: repair_slew14.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 10 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 3 connections. -[INFO ODB-0134] Finished DEF file: repair_slew14.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew14.tcl b/src/rsz/test/repair_slew14.tcl index 00b00ebb65e..65ef0bd71dd 100644 --- a/src/rsz/test/repair_slew14.tcl +++ b/src/rsz/test/repair_slew14.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design max load slew with long wire to output # in1--u1--------------------------out1 # 500 |--u2 2000 diff --git a/src/rsz/test/repair_slew15.ok b/src/rsz/test/repair_slew15.ok index 60d8463f006..900ef0607f9 100644 --- a/src/rsz/test/repair_slew15.ok +++ b/src/rsz/test/repair_slew15.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_slew10.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 12 components and 48 component-terminals. [INFO ODB-0132] Created 2 special nets and 24 connections. [INFO ODB-0133] Created 4 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: repair_slew10.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew15.tcl b/src/rsz/test/repair_slew15.tcl index ee81d9553ab..bf9a8ef5674 100644 --- a/src/rsz/test/repair_slew15.tcl +++ b/src/rsz/test/repair_slew15.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_slew10 with set_max_transition design read_liberty repair_slew10.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_slew16.ok b/src/rsz/test/repair_slew16.ok index 356454be4df..755cc8097e2 100644 --- a/src/rsz/test/repair_slew16.ok +++ b/src/rsz/test/repair_slew16.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 21 components and 126 component-terminals. [INFO ODB-0132] Created 2 special nets and 42 connections. [INFO ODB-0133] Created 2 nets and 42 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew1.def [INFO IFP-0001] Added 62 rows of 463 sites. Placement Analysis --------------------------------- diff --git a/src/rsz/test/repair_slew2.ok b/src/rsz/test/repair_slew2.ok index 5c94e15d70d..6ce17937cfa 100644 --- a/src/rsz/test/repair_slew2.ok +++ b/src/rsz/test/repair_slew2.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: repair_slew2.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: repair_slew2.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew2.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 21 components and 126 component-terminals. [INFO ODB-0132] Created 2 special nets and 42 connections. [INFO ODB-0133] Created 2 nets and 42 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew2.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew3.ok b/src/rsz/test/repair_slew3.ok index ae491b2ac40..a868f7aa0f6 100644 --- a/src/rsz/test/repair_slew3.ok +++ b/src/rsz/test/repair_slew3.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_slew3.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_slew3.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew3.tcl b/src/rsz/test/repair_slew3.tcl index ca2ea2c440b..8d6853e4654 100644 --- a/src/rsz/test/repair_slew3.tcl +++ b/src/rsz/test/repair_slew3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design slow driver into wire < max_length -> slew violation read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_slew4.ok b/src/rsz/test/repair_slew4.ok index 35e9d559f02..0357c9c2bea 100644 --- a/src/rsz/test/repair_slew4.ok +++ b/src/rsz/test/repair_slew4.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: repair_slew4.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: repair_slew4.lef -[INFO ODB-0127] Reading DEF file: repair_slew4.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 5 components and 20 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 3 nets and 7 connections. -[INFO ODB-0134] Finished DEF file: repair_slew4.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew4.tcl b/src/rsz/test/repair_slew4.tcl index b90a8756ee1..9ca726733e4 100644 --- a/src/rsz/test/repair_slew4.tcl +++ b/src/rsz/test/repair_slew4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design load max_slew << driver max_slew, no cap violation read_liberty Nangate45/Nangate45_typ.lib read_liberty repair_slew4.lib diff --git a/src/rsz/test/repair_slew5.ok b/src/rsz/test/repair_slew5.ok index 4ebe78b029c..f5ee24d2611 100644 --- a/src/rsz/test/repair_slew5.ok +++ b/src/rsz/test/repair_slew5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_slew5.def [INFO ODB-0128] Design: repair_slew5 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 13 components and 73 component-terminals. [INFO ODB-0132] Created 2 special nets and 26 connections. [INFO ODB-0133] Created 10 nets and 22 connections. -[INFO ODB-0134] Finished DEF file: repair_slew5.def Net u1zn Pin capacitance: 9.02-9.92 Wire capacitance: 0.42 diff --git a/src/rsz/test/repair_slew6.ok b/src/rsz/test/repair_slew6.ok index 9978fe2bbb4..6263c5597ef 100644 --- a/src/rsz/test/repair_slew6.ok +++ b/src/rsz/test/repair_slew6.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew6.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 51 components and 256 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 51 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew6.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew7.ok b/src/rsz/test/repair_slew7.ok index 197bf14b183..3cdd73336b9 100644 --- a/src/rsz/test/repair_slew7.ok +++ b/src/rsz/test/repair_slew7.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_slew5.def [INFO ODB-0128] Design: repair_slew5 [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 13 components and 73 component-terminals. [INFO ODB-0132] Created 2 special nets and 26 connections. [INFO ODB-0133] Created 10 nets and 22 connections. -[INFO ODB-0134] Finished DEF file: repair_slew5.def Startpoint: u1/A4 (internal pin) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/repair_slew8.ok b/src/rsz/test/repair_slew8.ok index aea13be02eb..9342d2e4c4f 100644 --- a/src/rsz/test/repair_slew8.ok +++ b/src/rsz/test/repair_slew8.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew8.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 250 components and 1500 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 500 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew8.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_slew9.ok b/src/rsz/test/repair_slew9.ok index 8b67613dd52..3171c94134a 100644 --- a/src/rsz/test/repair_slew9.ok +++ b/src/rsz/test/repair_slew9.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hd/sky130hd_std_cell.lef [INFO ODB-0225] Created 437 library cells [INFO ODB-0226] Finished LEF file: sky130hd/sky130hd_std_cell.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_slew1.def [INFO ODB-0128] Design: hi_fanout [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 105 components and 526 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 2 nets and 105 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_slew1.def Found 105 slew violations Found 1 cap violations [INFO RSZ-0058] Using max wire length 2393um. diff --git a/src/rsz/test/repair_slew9.tcl b/src/rsz/test/repair_slew9.tcl index 082f67caf29..ab3241fbd39 100644 --- a/src/rsz/test/repair_slew9.tcl +++ b/src/rsz/test/repair_slew9.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design -slew_margin source "max_slew_cap.tcl" repair_design -slew_margin 5 diff --git a/src/rsz/test/repair_tie1.ok b/src/rsz/test/repair_tie1.ok index c9c3efdcd08..42808b2ff86 100644 --- a/src/rsz/test/repair_tie1.ok +++ b/src/rsz/test/repair_tie1.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_tie1.def [INFO ODB-0128] Design: top [INFO ODB-0131] Created 6 components and 23 component-terminals. [INFO ODB-0133] Created 1 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_tie1.def [INFO RSZ-0042] Inserted 5 tie LOGIC1_X1 instances. 10.1 10.6 10.1 20.6 diff --git a/src/rsz/test/repair_tie2.ok b/src/rsz/test/repair_tie2.ok index f4cb5997058..e1990007969 100644 --- a/src/rsz/test/repair_tie2.ok +++ b/src/rsz/test/repair_tie2.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_tie2.def [INFO ODB-0128] Design: top [INFO ODB-0131] Created 5 components and 19 component-terminals. [INFO ODB-0133] Created 1 nets and 5 connections. -[INFO ODB-0134] Finished DEF file: repair_tie2.def [INFO RSZ-0042] Inserted 4 tie LOGIC1_X1 instances. 8.1 10.6 8.1 20.6 diff --git a/src/rsz/test/repair_tie3.ok b/src/rsz/test/repair_tie3.ok index a63207d2a6a..577f27c4be5 100644 --- a/src/rsz/test/repair_tie3.ok +++ b/src/rsz/test/repair_tie3.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: repair_tie3.def [INFO ODB-0128] Design: top [INFO ODB-0131] Created 8 components and 35 component-terminals. [INFO ODB-0133] Created 1 nets and 8 connections. -[INFO ODB-0134] Finished DEF file: repair_tie3.def [INFO RSZ-0042] Inserted 7 tie LOGIC1_X1 instances. 10.1 10.6 10.1 20.6 diff --git a/src/rsz/test/repair_tie4.ok b/src/rsz/test/repair_tie4.ok index 9cbb8b7c7ee..1008d1aecab 100644 --- a/src/rsz/test/repair_tie4.ok +++ b/src/rsz/test/repair_tie4.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: ./results/repair_tie4.def [INFO ODB-0128] Design: top [INFO ODB-0131] Created 11 components and 43 component-terminals. [INFO ODB-0133] Created 1 nets and 11 connections. -[INFO ODB-0134] Finished DEF file: ./results/repair_tie4.def [WARNING RSZ-0021] no estimated parasitics. Using wire load models. [INFO RSZ-0042] Inserted 10 tie LOGIC1_X1 instances. 10.1 10.6 diff --git a/src/rsz/test/repair_tie5.ok b/src/rsz/test/repair_tie5.ok index 622ca1df500..6657da75c8f 100644 --- a/src/rsz/test/repair_tie5.ok +++ b/src/rsz/test/repair_tie5.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: repair_tie5.def [INFO ODB-0128] Design: top [INFO ODB-0131] Created 5 components and 23 component-terminals. [INFO ODB-0133] Created 1 nets and 5 connections. -[INFO ODB-0134] Finished DEF file: repair_tie5.def [INFO RSZ-0042] Inserted 4 tie LOGIC1_X1 instances. 2.1 0.8 4.1 0.8 diff --git a/src/rsz/test/repair_tie6.ok b/src/rsz/test/repair_tie6.ok index 5b9af784e34..952fd4cfe59 100644 --- a/src/rsz/test/repair_tie6.ok +++ b/src/rsz/test/repair_tie6.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_tie6.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 2 components and 7 component-terminals. [INFO ODB-0133] Created 1 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: repair_tie6.def [INFO RSZ-0042] Inserted 2 tie LOGIC1_X1 instances. 1.1 1.1 10.1 10.6 diff --git a/src/rsz/test/repair_tie7.ok b/src/rsz/test/repair_tie7.ok index bd4b0f0d330..f528e2bd71c 100644 --- a/src/rsz/test/repair_tie7.ok +++ b/src/rsz/test/repair_tie7.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: repair_tie7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: repair_tie7.lef -[INFO ODB-0127] Reading DEF file: repair_tie7.def [INFO ODB-0128] Design: top [INFO ODB-0131] Created 6 components and 24 component-terminals. [INFO ODB-0133] Created 2 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_tie7.def [INFO RSZ-0042] Inserted 2 tie TIE_X1 instances. [INFO RSZ-0042] Inserted 2 tie TIE_X1 instances. 10.1 10.6 diff --git a/src/rsz/test/repair_wire1.ok b/src/rsz/test/repair_wire1.ok index 66e5c421943..13802910aba 100644 --- a/src/rsz/test/repair_wire1.ok +++ b/src/rsz/test/repair_wire1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire1.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire1.def Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/repair_wire1.tcl b/src/rsz/test/repair_wire1.tcl index c3f32991c3d..8714be7ccc5 100644 --- a/src/rsz/test/repair_wire1.tcl +++ b/src/rsz/test/repair_wire1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design 1 wire # in1--u1--u2--------u3-out1 # 2000u diff --git a/src/rsz/test/repair_wire10.ok b/src/rsz/test/repair_wire10.ok index 2bf1ea53412..882f2090895 100644 --- a/src/rsz/test/repair_wire10.ok +++ b/src/rsz/test/repair_wire10.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire1.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire1.def [INFO IFP-0001] Added 142 rows of 11052 sites. Placement Analysis --------------------------------- diff --git a/src/rsz/test/repair_wire11.ok b/src/rsz/test/repair_wire11.ok index 01854a82d0b..a4b864f2de3 100644 --- a/src/rsz/test/repair_wire11.ok +++ b/src/rsz/test/repair_wire11.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: repair_wire11.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 2 components and 10 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 3 connections. -[INFO ODB-0134] Finished DEF file: repair_wire11.def [WARNING IFP-0028] Core area lower left (10.000, 10.000) snapped to (10.070, 11.200). [INFO IFP-0001] Added 270 rows of 1999 sites. max slew diff --git a/src/rsz/test/repair_wire2.ok b/src/rsz/test/repair_wire2.ok index be6d54ddbf2..f9f6989aec5 100644 --- a/src/rsz/test/repair_wire2.ok +++ b/src/rsz/test/repair_wire2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire2.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 4 components and 16 component-terminals. [INFO ODB-0132] Created 2 special nets and 8 connections. [INFO ODB-0133] Created 5 nets and 8 connections. -[INFO ODB-0134] Finished DEF file: repair_wire2.def Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/repair_wire2.tcl b/src/rsz/test/repair_wire2.tcl index 004c04de24f..e00af3392f1 100644 --- a/src/rsz/test/repair_wire2.tcl +++ b/src/rsz/test/repair_wire2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design 2 loads in L shape wire # # u4-out2 diff --git a/src/rsz/test/repair_wire3.ok b/src/rsz/test/repair_wire3.ok index b1b892df032..926f8892f53 100644 --- a/src/rsz/test/repair_wire3.ok +++ b/src/rsz/test/repair_wire3.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire1.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire1.def [WARNING RSZ-0010] Signal/clock wire resistance is 0. [WARNING RSZ-0011] Signal/clock wire capacitance is 0. [WARNING RSZ-0014] wire capacitance for corner default is zero. Use the set_wire_rc command to set wire resistance and capacitance. diff --git a/src/rsz/test/repair_wire3.tcl b/src/rsz/test/repair_wire3.tcl index 338fca103f1..c759ed6d9a5 100644 --- a/src/rsz/test/repair_wire3.tcl +++ b/src/rsz/test/repair_wire3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design missing wire rc read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/repair_wire4.ok b/src/rsz/test/repair_wire4.ok index e8c40303573..7bc9c11c254 100644 --- a/src/rsz/test/repair_wire4.ok +++ b/src/rsz/test/repair_wire4.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire4.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 3 pins. [INFO ODB-0131] Created 4 components and 16 component-terminals. [INFO ODB-0132] Created 2 special nets and 8 connections. [INFO ODB-0133] Created 5 nets and 8 connections. -[INFO ODB-0134] Finished DEF file: repair_wire4.def Driver length delay u2/Z manhtn 1500.4 steiner 1500.4 0.30 u3/Z manhtn 1.1 steiner 1.1 0.00 diff --git a/src/rsz/test/repair_wire4.tcl b/src/rsz/test/repair_wire4.tcl index ae4ccfb03a3..d2a90711eff 100644 --- a/src/rsz/test/repair_wire4.tcl +++ b/src/rsz/test/repair_wire4.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design 2 loads driven from middle # # u4-out2 diff --git a/src/rsz/test/repair_wire5.ok b/src/rsz/test/repair_wire5.ok index c1e41f1e04d..556128cd1bb 100644 --- a/src/rsz/test/repair_wire5.ok +++ b/src/rsz/test/repair_wire5.ok @@ -6,13 +6,11 @@ [INFO ODB-0222] Reading LEF file: pad.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: pad.lef -[INFO ODB-0127] Reading DEF file: repair_wire5.def [INFO ODB-0128] Design: RocketTile [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 2 components and 10 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 3 connections. -[INFO ODB-0134] Finished DEF file: repair_wire5.def max slew Pin Limit Slew Slack diff --git a/src/rsz/test/repair_wire6.ok b/src/rsz/test/repair_wire6.ok index eefa99b32e7..0c0bcd29ef9 100644 --- a/src/rsz/test/repair_wire6.ok +++ b/src/rsz/test/repair_wire6.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire6.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 2 components and 8 component-terminals. [INFO ODB-0132] Created 2 special nets and 4 connections. [INFO ODB-0133] Created 3 nets and 4 connections. -[INFO ODB-0134] Finished DEF file: repair_wire6.def Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/repair_wire6.tcl b/src/rsz/test/repair_wire6.tcl index 3463a19d3f6..b6aaf6f5df7 100644 --- a/src/rsz/test/repair_wire6.tcl +++ b/src/rsz/test/repair_wire6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design log wire to output port # in1--u1--u2---------out1 # 1500u diff --git a/src/rsz/test/repair_wire7.ok b/src/rsz/test/repair_wire7.ok index 6a3c0aa5566..041f6905bca 100644 --- a/src/rsz/test/repair_wire7.ok +++ b/src/rsz/test/repair_wire7.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire7.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire7.def Startpoint: in1 (input port) Endpoint: out1 (output port) Path Group: (none) diff --git a/src/rsz/test/repair_wire7.tcl b/src/rsz/test/repair_wire7.tcl index 99fd2d88278..8dfd420aabf 100644 --- a/src/rsz/test/repair_wire7.tcl +++ b/src/rsz/test/repair_wire7.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_design long wire from input port # in1-----------u1--u2--out1 # 1500u diff --git a/src/rsz/test/repair_wire8.ok b/src/rsz/test/repair_wire8.ok index 0f775bd42da..d226a43ac0d 100644 --- a/src/rsz/test/repair_wire8.ok +++ b/src/rsz/test/repair_wire8.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire1.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 3 components and 12 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 4 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: repair_wire1.def [INFO RSZ-0058] Using max wire length 1258um. [INFO RSZ-0037] Found 1 long wires. [INFO RSZ-0038] Inserted 1 buffers in 1 nets. diff --git a/src/rsz/test/repair_wire8.tcl b/src/rsz/test/repair_wire8.tcl index 18c335ea893..91d5fce246a 100644 --- a/src/rsz/test/repair_wire8.tcl +++ b/src/rsz/test/repair_wire8.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # repair_wire1 with fast/slow corners # in1--u1--u2--------u3-out1 # 2000u diff --git a/src/rsz/test/repair_wire9.ok b/src/rsz/test/repair_wire9.ok index d6ff81bf215..ad3b670a491 100644 --- a/src/rsz/test/repair_wire9.ok +++ b/src/rsz/test/repair_wire9.ok @@ -3,10 +3,8 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_wire9.def [INFO ODB-0128] Design: long_wire [INFO ODB-0130] Created 2 pins. [INFO ODB-0131] Created 1 components and 4 component-terminals. [INFO ODB-0132] Created 2 special nets and 2 connections. [INFO ODB-0133] Created 2 nets and 2 connections. -[INFO ODB-0134] Finished DEF file: repair_wire9.def diff --git a/src/rsz/test/repair_wire9.tcl b/src/rsz/test/repair_wire9.tcl index bd5985b983f..fd232f2065f 100644 --- a/src/rsz/test/repair_wire9.tcl +++ b/src/rsz/test/repair_wire9.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # estimate_parasitics driver/load pins in same location read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/report_floating_nets1.tcl b/src/rsz/test/report_floating_nets1.tcl index a4a5c648709..960d7f88187 100644 --- a/src/rsz/test/report_floating_nets1.tcl +++ b/src/rsz/test/report_floating_nets1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # report_floating_nets read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/resize1.ok b/src/rsz/test/resize1.ok index ec8811f5060..ca20d953eee 100644 --- a/src/rsz/test/resize1.ok +++ b/src/rsz/test/resize1.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg2.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg2.def Instance r1 Cell: DFF_X2 Library: Nangate45 diff --git a/src/rsz/test/resize1.tcl b/src/rsz/test/resize1.tcl index 53bfddb699c..fc2d255c10f 100644 --- a/src/rsz/test/resize1.tcl +++ b/src/rsz/test/resize1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # resize to target_slew read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/resize4.ok b/src/rsz/test/resize4.ok index 52dd3cb4383..00062e56e3c 100644 --- a/src/rsz/test/resize4.ok +++ b/src/rsz/test/resize4.ok @@ -5,13 +5,11 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: resize4.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 3 components and 22 component-terminals. [INFO ODB-0132] Created 2 special nets and 0 connections. [INFO ODB-0133] Created 3 nets and 6 connections. -[INFO ODB-0134] Finished DEF file: resize4.def Startpoint: r1 (rising edge-triggered flip-flop clocked by clk) Endpoint: r2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk diff --git a/src/rsz/test/resize5.ok b/src/rsz/test/resize5.ok index 90b782b25c6..b6b92357d8b 100644 --- a/src/rsz/test/resize5.ok +++ b/src/rsz/test/resize5.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: resize5.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 3 components and 18 component-terminals. [INFO ODB-0132] Created 2 special nets and 6 connections. [INFO ODB-0133] Created 3 nets and 7 connections. -[INFO ODB-0134] Finished DEF file: resize5.def Instance r1 Cell: DFF_X2 Library: Nangate45 diff --git a/src/rsz/test/resize6.ok b/src/rsz/test/resize6.ok index 797772f08df..4ce4095d2cf 100644 --- a/src/rsz/test/resize6.ok +++ b/src/rsz/test/resize6.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: reg3.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 4 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0132] Created 2 special nets and 10 connections. [INFO ODB-0133] Created 8 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: reg3.def [INFO RSZ-0028] Inserted 1 output buffers. [INFO RSZ-0058] Using max wire length 720um. [INFO RSZ-0036] Found 1 capacitance violations. diff --git a/src/rsz/test/resize6.tcl b/src/rsz/test/resize6.tcl index 375cc0bd95b..529b4a7d45f 100644 --- a/src/rsz/test/resize6.tcl +++ b/src/rsz/test/resize6.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # resize with buffer outputs with external load read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/resize_slack1.ok b/src/rsz/test/resize_slack1.ok index 9d91d0ec38c..83b2694f63e 100644 --- a/src/rsz/test/resize_slack1.ok +++ b/src/rsz/test/resize_slack1.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_setup1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 17 components and 92 component-terminals. [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_setup1.def [INFO RSZ-0026] Removed 5 buffers. r1q 0.741 diff --git a/src/rsz/test/resize_slack1.tcl b/src/rsz/test/resize_slack1.tcl index ca8527bafbc..ad6750ce2e4 100644 --- a/src/rsz/test/resize_slack1.tcl +++ b/src/rsz/test/resize_slack1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # slack map api read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/resize_slack2.ok b/src/rsz/test/resize_slack2.ok index 7d18dc14e95..1ba5b6cc59a 100644 --- a/src/rsz/test/resize_slack2.ok +++ b/src/rsz/test/resize_slack2.ok @@ -3,13 +3,11 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: gcd_nangate45_placed.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 571 components and 2554 component-terminals. [INFO ODB-0132] Created 5 special nets and 1142 connections. [INFO ODB-0133] Created 528 nets and 1412 connections. -[INFO ODB-0134] Finished DEF file: gcd_nangate45_placed.def [INFO RSZ-0026] Removed 151 buffers. _081_ 1.338 _346_ 1.338 diff --git a/src/rsz/test/resize_slack2.tcl b/src/rsz/test/resize_slack2.tcl index ab4c39941c5..24558e90f5f 100644 --- a/src/rsz/test/resize_slack2.tcl +++ b/src/rsz/test/resize_slack2.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # slack map api read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/resize_slack3.ok b/src/rsz/test/resize_slack3.ok index 9d91d0ec38c..83b2694f63e 100644 --- a/src/rsz/test/resize_slack3.ok +++ b/src/rsz/test/resize_slack3.ok @@ -3,12 +3,10 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: repair_setup1.def [INFO ODB-0128] Design: reg1 [INFO ODB-0130] Created 1 pins. [INFO ODB-0131] Created 17 components and 92 component-terminals. [INFO ODB-0132] Created 2 special nets and 34 connections. [INFO ODB-0133] Created 7 nets and 30 connections. -[INFO ODB-0134] Finished DEF file: repair_setup1.def [INFO RSZ-0026] Removed 5 buffers. r1q 0.741 diff --git a/src/rsz/test/resize_slack3.tcl b/src/rsz/test/resize_slack3.tcl index aac2962ec1f..5636f357208 100644 --- a/src/rsz/test/resize_slack3.tcl +++ b/src/rsz/test/resize_slack3.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # slack map api no set_wire_rr read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/resizer_helpers.tcl b/src/rsz/test/resizer_helpers.tcl index 783da09d537..0f00ab12e79 100644 --- a/src/rsz/test/resizer_helpers.tcl +++ b/src/rsz/test/resizer_helpers.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # Make sure instances are inside the core. proc check_in_core {} { set core [ord::get_db_core] diff --git a/src/rsz/test/set_layer_rc1.tcl b/src/rsz/test/set_layer_rc1.tcl index e947fe2d9be..93bcd20f261 100644 --- a/src/rsz/test/set_layer_rc1.tcl +++ b/src/rsz/test/set_layer_rc1.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" # set_layer_rc read_liberty Nangate45/Nangate45_typ.lib read_lef Nangate45/Nangate45.lef diff --git a/src/rsz/test/set_loc.tcl b/src/rsz/test/set_loc.tcl index a56e8e2d585..c5032f78ab4 100644 --- a/src/rsz/test/set_loc.tcl +++ b/src/rsz/test/set_loc.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" proc set_inst_loc { inst_name x y } { set inst [get_cell $inst_name] [sta::sta_to_db_inst $inst] setOrigin [ord::microns_to_dbu $x] [ord::microns_to_dbu $y] diff --git a/src/rsz/test/tie_fanout.tcl b/src/rsz/test/tie_fanout.tcl index 45def2213a3..efa5a70357e 100644 --- a/src/rsz/test/tie_fanout.tcl +++ b/src/rsz/test/tie_fanout.tcl @@ -1,3 +1,4 @@ +source "helpers.tcl" proc write_tie_hi_fanout_def { filename tie_port load_port fanout } { set stream [open $filename "w"] diff --git a/src/tap/test/avoid_overlap.ok b/src/tap/test/avoid_overlap.ok index a8ffdf407dc..9fd7e7003af 100644 --- a/src/tap/test/avoid_overlap.ok +++ b/src/tap/test/avoid_overlap.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130hs_floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 366 components and 2656 component-terminals. [INFO ODB-0133] Created 402 nets and 1192 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130hs_floorplan.def [INFO TAP-0004] Inserted 168 endcaps. [INFO TAP-0005] Inserted 817 tapcells. No differences found. diff --git a/src/tap/test/boundary_macros.ok b/src/tap/test/boundary_macros.ok index f53141d57de..293bae36eb9 100644 --- a/src/tap/test/boundary_macros.ok +++ b/src/tap/test/boundary_macros.ok @@ -8,11 +8,9 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: boundary_macros.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 5 components and 160 component-terminals. -[INFO ODB-0134] Finished DEF file: boundary_macros.def [INFO ODB-0303] The initial 57 rows (24054 sites) were cut with 5 shapes for a total of 13 rows (577 sites). [INFO TAP-0004] Inserted 26 endcaps. [INFO TAP-0006] Inserted 89 top/bottom cells. diff --git a/src/tap/test/gcd_fakeram.ok b/src/tap/test/gcd_fakeram.ok index bc9d5e0f7e8..f0cf91da472 100644 --- a/src/tap/test/gcd_fakeram.ok +++ b/src/tap/test/gcd_fakeram.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: gcd_fakeram.def [INFO ODB-0128] Design: gcd_mem1 [INFO ODB-0130] Created 61 pins. [INFO ODB-0131] Created 1 components and 32 component-terminals. -[INFO ODB-0134] Finished DEF file: gcd_fakeram.def [INFO ODB-0303] The initial 30 rows (6960 sites) were cut with 1 shapes for a total of 30 rows (4935 sites). [INFO TAP-0004] Inserted 60 endcaps. [INFO TAP-0005] Inserted 19 tapcells. diff --git a/src/tap/test/gcd_nangate45.ok b/src/tap/test/gcd_nangate45.ok index a9efc84af26..e3fe84c2dd1 100644 --- a/src/tap/test/gcd_nangate45.ok +++ b/src/tap/test/gcd_nangate45.ok @@ -5,10 +5,8 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: gcd_nangate45.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. -[INFO ODB-0134] Finished DEF file: gcd_nangate45.def [INFO TAP-0004] Inserted 114 endcaps. [INFO TAP-0005] Inserted 118 tapcells. No differences found. diff --git a/src/tap/test/gcd_prefix.ok b/src/tap/test/gcd_prefix.ok index a293fa031b0..e3fe84c2dd1 100644 --- a/src/tap/test/gcd_prefix.ok +++ b/src/tap/test/gcd_prefix.ok @@ -5,10 +5,8 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: gcd_prefix.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. -[INFO ODB-0134] Finished DEF file: gcd_prefix.def [INFO TAP-0004] Inserted 114 endcaps. [INFO TAP-0005] Inserted 118 tapcells. No differences found. diff --git a/src/tap/test/gcd_ripup.ok b/src/tap/test/gcd_ripup.ok index 1aa7c224465..75863295d5f 100644 --- a/src/tap/test/gcd_ripup.ok +++ b/src/tap/test/gcd_ripup.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: gcd_ripup.def [INFO ODB-0128] Design: gcd_mem1 [INFO ODB-0130] Created 61 pins. [INFO ODB-0131] Created 1 components and 32 component-terminals. -[INFO ODB-0134] Finished DEF file: gcd_ripup.def [INFO ODB-0303] The initial 30 rows (6960 sites) were cut with 1 shapes for a total of 30 rows (4935 sites). [INFO TAP-0004] Inserted 60 endcaps. [INFO TAP-0005] Inserted 19 tapcells. diff --git a/src/tap/test/gcd_sky130.ok b/src/tap/test/gcd_sky130.ok index 6476ff1c896..c69011ff2c9 100644 --- a/src/tap/test/gcd_sky130.ok +++ b/src/tap/test/gcd_sky130.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130hs_floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 366 components and 2656 component-terminals. [INFO ODB-0133] Created 402 nets and 1192 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130hs_floorplan.def [INFO TAP-0004] Inserted 168 endcaps. [INFO TAP-0005] Inserted 774 tapcells. No differences found. diff --git a/src/tap/test/invalid_cells.ok b/src/tap/test/invalid_cells.ok index 125d3c8adf2..ba6a003065a 100644 --- a/src/tap/test/invalid_cells.ok +++ b/src/tap/test/invalid_cells.ok @@ -5,8 +5,6 @@ [INFO ODB-0222] Reading LEF file: Nangate45/Nangate45_stdcell.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45_stdcell.lef -[INFO ODB-0127] Reading DEF file: invalid_cells.def [INFO ODB-0128] Design: gcd -[INFO ODB-0134] Finished DEF file: invalid_cells.def [ERROR TAP-0010] Master TAPCELL_X1x not found. TAP-0010 diff --git a/src/tap/test/multiple_calls.ok b/src/tap/test/multiple_calls.ok index 020ef504a93..2e2e5d1786d 100644 --- a/src/tap/test/multiple_calls.ok +++ b/src/tap/test/multiple_calls.ok @@ -6,11 +6,9 @@ [INFO ODB-0222] Reading LEF file: Nangate45/fakeram45_64x7.lef [INFO ODB-0225] Created 1 library cells [INFO ODB-0226] Finished LEF file: Nangate45/fakeram45_64x7.lef -[INFO ODB-0127] Reading DEF file: gcd_ripup.def [INFO ODB-0128] Design: gcd_mem1 [INFO ODB-0130] Created 61 pins. [INFO ODB-0131] Created 1 components and 32 component-terminals. -[INFO ODB-0134] Finished DEF file: gcd_ripup.def [INFO ODB-0303] The initial 30 rows (6960 sites) were cut with 1 shapes for a total of 30 rows (4935 sites). [INFO TAP-0004] Inserted 60 endcaps. [INFO TAP-0005] Inserted 19 tapcells. diff --git a/src/tap/test/no_endcap.ok b/src/tap/test/no_endcap.ok index dd88d3c7316..bcf7bfb3e5d 100644 --- a/src/tap/test/no_endcap.ok +++ b/src/tap/test/no_endcap.ok @@ -5,11 +5,9 @@ [INFO ODB-0222] Reading LEF file: sky130hs/sky130hs_std_cell.lef [INFO ODB-0225] Created 390 library cells [INFO ODB-0226] Finished LEF file: sky130hs/sky130hs_std_cell.lef -[INFO ODB-0127] Reading DEF file: gcd_sky130hs_floorplan.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 366 components and 2656 component-terminals. [INFO ODB-0133] Created 402 nets and 1192 connections. -[INFO ODB-0134] Finished DEF file: gcd_sky130hs_floorplan.def [INFO TAP-0005] Inserted 774 tapcells. No differences found. diff --git a/src/tap/test/symmetry.ok b/src/tap/test/symmetry.ok index 02ee01e993f..da7753aa0e3 100644 --- a/src/tap/test/symmetry.ok +++ b/src/tap/test/symmetry.ok @@ -5,12 +5,10 @@ [INFO ODB-0222] Reading LEF file: symmetry.lef [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: symmetry.lef -[INFO ODB-0127] Reading DEF file: symmetry.def [INFO ODB-0128] Design: gcd [INFO ODB-0130] Created 54 pins. [INFO ODB-0131] Created 344 components and 1833 component-terminals. [INFO ODB-0133] Created 415 nets and 1145 connections. -[INFO ODB-0134] Finished DEF file: symmetry.def [INFO TAP-0004] Inserted 56 endcaps. [INFO TAP-0005] Inserted 0 tapcells. No differences found. diff --git a/src/utl/include/utl/Logger.h b/src/utl/include/utl/Logger.h index de27099ce36..28e55061b1f 100644 --- a/src/utl/include/utl/Logger.h +++ b/src/utl/include/utl/Logger.h @@ -204,6 +204,8 @@ class Logger return (it != groups.end() && level <= it->second); } + void suppressMessage(ToolId tool, int id); + void addSink(spdlog::sink_ptr sink); void removeSink(spdlog::sink_ptr sink); void addMetricsSink(const char *metrics_filename); diff --git a/src/utl/src/Logger.cpp b/src/utl/src/Logger.cpp index be99dabb9cd..db5f1de6bcf 100644 --- a/src/utl/src/Logger.cpp +++ b/src/utl/src/Logger.cpp @@ -176,4 +176,9 @@ void Logger::finalizeMetrics() { } } +void Logger::suppressMessage(ToolId tool, int id) +{ + message_counters_[tool][id] = max_message_print + 1; +} + } // namespace diff --git a/src/utl/src/Logger.i b/src/utl/src/Logger.i index 3cef475aa60..e7a6ce04181 100644 --- a/src/utl/src/Logger.i +++ b/src/utl/src/Logger.i @@ -157,6 +157,12 @@ const std::string pop_metrics_stage(){ return logger->popMetricsStage(); } +void suppress_message(utl::ToolId tool, int id) +{ + Logger* logger = getLogger(); + logger->suppressMessage(tool, id); +} + } // namespace %} // inline diff --git a/test/flow_metrics.tcl b/test/flow_metrics.tcl index 4ef1d62d408..3669d08cf24 100644 --- a/test/flow_metrics.tcl +++ b/test/flow_metrics.tcl @@ -138,11 +138,11 @@ define_metric "DRT::clock_period" "" "" 0 "%5.2f" "<=" {$value} # Used by regression.tcl to check pass/fail metrics test. # Returns "pass" or failing metric comparison string. -proc check_test_metrics { test } { +proc check_test_metrics { test lang } { # Don't require json until it is really needed. package require json - set metrics_file [test_metrics_result_file $test] + set metrics_file [test_metrics_result_file $test $lang] set metrics_limits_file [test_metrics_limits_file $test] if { ![file exists $metrics_file] } { return "missing metrics file" @@ -202,7 +202,7 @@ proc fail { msg } { ################################################################ proc report_flow_metrics_main {} { - global argc argv test_groups + global argc argv test_groups test_langs if { $argc == 0 } { set tests $test_groups(flow) } else { @@ -211,7 +211,7 @@ proc report_flow_metrics_main {} { report_metrics_header foreach test $tests { - report_test_metrics $test + report_test_metrics $test $test_langs($test) } } @@ -247,11 +247,11 @@ proc report_metrics_header {} { puts "" } -proc report_test_metrics { test } { +proc report_test_metrics { test $lang } { # Don't require json until it is really needed. package require json - set metrics_result_file [test_metrics_result_file $test] + set metrics_result_file [test_metrics_result_file $test $lang] if { [file exists $metrics_result_file] } { set stream [open $metrics_result_file r] set json_string [read $stream] @@ -337,7 +337,7 @@ proc report_test_metric_limits { test } { ################################################################ proc compare_flow_metrics_main {} { - global argc argv test_groups + global argc argv test_groups test_langs if { $argv == "help" || $argv == "-help" } { puts {Usage: save_flow_metrics [test1]...} } else { @@ -355,17 +355,17 @@ proc compare_flow_metrics_main {} { report_metrics_header foreach test $tests { - compare_test_metrics $test $relative + compare_test_metrics $test $relative $test_langs($test) } } } -proc compare_test_metrics { test relative } { +proc compare_test_metrics { test relative lang } { # Don't require json until it is really needed. package require json set metrics_file [test_metrics_file $test] - set result_file [test_metrics_result_file $test] + set result_file [test_metrics_result_file $test $lang] if { [file exists $metrics_file] \ && [file exists $result_file] } { set metrics_stream [open $metrics_file r] @@ -428,7 +428,8 @@ proc save_metrics { test } { if { [lsearch [group_tests "all"] $test] == -1 } { puts "Error: test $test not found." } else { - set metrics_result_file [test_metrics_result_file $test] + set metrics_result_file [test_metrics_result_file $test \ + [result_lang $test]] set metrics_file [test_metrics_file $test] file copy -force $metrics_result_file $metrics_file } @@ -453,11 +454,12 @@ proc save_flow_metric_limits_main {} { } } -proc save_metric_limits { test } { +proc save_metric_limits { test lang } { + global test_langs # Don't require json until it is really needed. package require json - set metrics_file [test_metrics_result_file $test] + set metrics_file [test_metrics_result_file $test $test_langs($test)] set metrics_limits [test_metrics_limits_file $test] if { ! [file exists $metrics_file] } { puts "Error: metrics file $metrics_file not found." @@ -512,9 +514,9 @@ proc test_metrics_file { test } { return [file join $test_dir "$test.metrics"] } -proc test_metrics_result_file { test } { +proc test_metrics_result_file { test lang } { global test_dir - return [file join $test_dir "results" "$test.metrics"] + return [file join $test_dir "results" "$test-$lang.metrics"] } proc test_metrics_limits_file { test } { diff --git a/test/get_core_die_areas.ok b/test/get_core_die_areas.ok index e80320ff3a8..da5f8c11cf4 100644 --- a/test/get_core_die_areas.ok +++ b/test/get_core_die_areas.ok @@ -3,11 +3,9 @@ [INFO ODB-0224] Created 27 technology vias [INFO ODB-0225] Created 135 library cells [INFO ODB-0226] Finished LEF file: Nangate45/Nangate45.lef -[INFO ODB-0127] Reading DEF file: get_core_die_areas.def [INFO ODB-0128] Design: top [INFO ODB-0130] Created 6 pins. [INFO ODB-0131] Created 5 components and 27 component-terminals. [INFO ODB-0133] Created 10 nets and 14 connections. -[INFO ODB-0134] Finished DEF file: get_core_die_areas.def 0.0 0.0 510.14 255.07 199.88 99.4 210.14 105.0 diff --git a/test/helpers.py b/test/helpers.py new file mode 100644 index 00000000000..a855642111f --- /dev/null +++ b/test/helpers.py @@ -0,0 +1,41 @@ +import odb +import os + +def make_rect(design, xl, yl, xh, yh): + xl = design.micronToDBU(xl) + yl = design.micronToDBU(yl) + xh = design.micronToDBU(xh) + yh = design.micronToDBU(yh) + return odb.Rect(xl, yl, xh, yh) + +def make_result_file(filename): + result_dir = os.path.join(os.getcwd(), 'results') + if not os.path.exists(result_dir): + os.mkdir(result_dir) + + root_ext = os.path.splitext(filename) + filename = "{}-py{}".format(*root_ext) + return os.path.join(result_dir, filename) + +def diff_files(file1, file2): + with open(file1, 'r') as f: + lines1 = f.readlines() + + with open(file2, 'r') as f: + lines2 = f.readlines() + + num_lines1 = len(lines1) + num_lines2 = len(lines2) + for i in range(min(num_lines1, num_lines2)): + if lines1[i] != lines2[i]: + print(f"Differences found at line {i}") + print(lines1[i]) + print(lines2[i]) + return 1 + + if num_lines1 != num_lines2: + print(f"Number of lines differs {num_lines1} vs {num_lines2}.") + return 1 + + print("No differences found.") + return 0 diff --git a/test/helpers.tcl b/test/helpers.tcl index afbb699e4f5..74002e72758 100644 --- a/test/helpers.tcl +++ b/test/helpers.tcl @@ -8,6 +8,9 @@ proc make_result_file { filename } { if { ![file exists $result_dir] } { file mkdir $result_dir } + set root [file rootname $filename] + set ext [file extension $filename] + set filename "$root-tcl$ext" return [file join $result_dir $filename] } @@ -50,3 +53,16 @@ proc diff_files { file1 file2 } { return 0 } } + +# Output voltage file is specified as ... +suppress_message PSM 2 +# Output current file specified ... +suppress_message PSM 3 +# Output spice file is specified as +suppress_message PSM 5 +# SPICE file is written at +suppress_message PSM 6 +# Reading DEF file +suppress_message ODB 127 +# Finished DEF file +suppress_message ODB 134 diff --git a/test/regression.tcl b/test/regression.tcl index c328b093822..0c1a01f0e44 100755 --- a/test/regression.tcl +++ b/test/regression.tcl @@ -165,18 +165,31 @@ proc run_tests {} { } proc run_test { test } { + global test_langs + + set langs $test_langs($test) + if {[llength $langs] == 0} { + puts "$test *NO CMD FILE*" + incr errors(no_cmd) + } + foreach lang $langs { + run_test_lang $test $lang + } +} + +proc run_test_lang { test lang } { global result_dir diff_file errors diff_options - set cmd_file [test_cmd_file $test] + set cmd_file [test_cmd_file $test $lang] if [file exists $cmd_file] { set ok_file [test_ok_file $test] - set log_file [test_log_file $test] - foreach file [glob -nocomplain [file join $result_dir $test.*]] { + set log_file [test_log_file $test $lang] + foreach file [glob -nocomplain [file join $result_dir $test-$lang.*]] { file delete -force $file } - puts -nonewline $test + puts -nonewline "$test ($lang)" flush stdout - set test_errors [run_test_app $test $cmd_file $log_file] + set test_errors [run_test_app $test $cmd_file $log_file $lang] if { [lindex $test_errors 0] == "ERROR" } { puts " *ERROR* [lrange $test_errors 1 end]" append_failure $test @@ -239,7 +252,7 @@ proc run_test { test } { } } check_metrics { - set error_msg [check_test_metrics $test] + set error_msg [check_test_metrics $test $lang] if { $error_msg != "pass" } { puts " *FAIL* $error_msg" append_failure $test @@ -251,7 +264,7 @@ proc run_test { test } { } } } else { - puts "$test *NO CMD FILE*" + puts "$test ($lang) *NO CMD FILE*" incr errors(no_cmd) } } @@ -281,16 +294,16 @@ proc append_failure { test } { } # Return error. -proc run_test_app { test cmd_file log_file } { +proc run_test_app { test cmd_file log_file lang } { global app_path errorCode use_valgrind if { $use_valgrind } { - return [run_test_valgrind $test $cmd_file $log_file] + return [run_test_valgrind $test $cmd_file $log_file $lang] } else { - return [run_test_plain $test $cmd_file $log_file] + return [run_test_plain $test $cmd_file $log_file $lang] } } -proc run_test_plain { test cmd_file log_file } { +proc run_test_plain { test cmd_file log_file lang } { global app_path app_options result_dir errorCode if { ![file exists $app_path] } { @@ -300,7 +313,9 @@ proc run_test_plain { test cmd_file log_file } { } else { set save_dir [pwd] cd [file dirname $cmd_file] - if { [catch [concat exec $app_path $app_options -metrics [test_metrics_result_file $test]\ + if { [catch [concat exec $app_path $app_options \ + [lang_flag $lang] \ + -metrics [test_metrics_result_file $test $lang]\ [file tail $cmd_file] >& $log_file]] } { cd $save_dir set signal [lindex $errorCode 2] @@ -312,7 +327,7 @@ proc run_test_plain { test cmd_file log_file } { set pid [lindex $errorCode 1] set sys_corefile [test_sys_core_file $test $pid] if { [file exists $sys_corefile] } { - file copy $sys_corefile [test_core_file $test] + file copy $sys_corefile [test_core_file $test $lang] } } cleanse_logfile $test $log_file @@ -324,24 +339,25 @@ proc run_test_plain { test cmd_file log_file } { } } -proc run_test_valgrind { test cmd_file log_file } { +proc run_test_valgrind { test cmd_file log_file lang } { global app_path app_options valgrind_options result_dir errorCode - set vg_cmd_file [test_valgrind_cmd_file $test] + set vg_cmd_file [test_valgrind_cmd_file $test $lang] set vg_stream [open $vg_cmd_file "w"] puts $vg_stream "cd [file dirname $cmd_file]" puts $vg_stream "source [file tail $cmd_file]" close $vg_stream set cmd [concat exec valgrind $valgrind_options \ - $app_path $app_options $vg_cmd_file >& $log_file] + $app_path [lang_flag $lang] $app_options \ + $vg_cmd_file >& $log_file] set error_msg "" if { [catch $cmd] } { set error_msg "ERROR [lindex $errorCode 3]" } file delete $vg_cmd_file cleanse_logfile $test $log_file - lappend error_msg [cleanse_valgrind_logfile $test $log_file] + lappend error_msg [cleanse_valgrind_logfile $test $log_file $lang] return $error_msg } @@ -369,13 +385,13 @@ set valgrind_shared_lib_failure_regexp "No malloc'd blocks -- no leaks are possi # Scan the log file to separate valgrind notifications and check for # valgrind errors. -proc cleanse_valgrind_logfile { test log_file } { +proc cleanse_valgrind_logfile { test log_file lang } { global valgrind_mem_regexp valgrind_leak_regexp global valgrind_shared_lib_failure_regexp global valgrind_shared_lib_failure set tmp_file [test_tmp_file $test] - set valgrind_log_file [test_valgrind_file $test] + set valgrind_log_file [test_valgrind_file $test $lang] file copy -force $log_file $tmp_file set tmp [open $tmp_file "r"] set log [open $log_file "w"] @@ -505,7 +521,7 @@ proc failed_tests {} { proc save_ok { test } { set ok_file [test_ok_file $test] - set log_file [test_log_file $test] + set log_file [test_log_file $test [result_lang $test]] if { ! [file exists $log_file] } { puts "Error: log file $log_file not found." } else { @@ -537,7 +553,7 @@ proc save_defok_main {} { proc save_defok { test } { set defok_file [test_defok_file $test] - set def_file [test_def_result_file $test] + set def_file [test_def_result_file $test [result_lang $test]] if { [file exists $def_file] } { file copy -force $def_file $defok_file } @@ -545,6 +561,15 @@ proc save_defok { test } { ################################################################ +proc result_lang { test } { + global test_langs + + if {[lsearch $test_langs($test) tcl]} { + return tcl + } + return [lindex $test_langs($test) 0] +} + proc test_cmd_dir { test } { global cmd_dirs @@ -555,8 +580,8 @@ proc test_cmd_dir { test } { } } -proc test_cmd_file { test } { - return [file join [test_cmd_dir $test] "$test.tcl"] +proc test_cmd_file { test lang } { + return [file join [test_cmd_dir $test] "$test.$lang"] } proc test_ok_file { test } { @@ -569,14 +594,21 @@ proc test_defok_file { test } { return [file join $test_dir "$test.defok"] } -proc test_log_file { test } { +proc test_log_file { test lang } { global result_dir - return [file join $result_dir "$test.log"] + return [file join $result_dir "$test-$lang.log"] } -proc test_def_result_file { test } { +proc test_def_result_file { test lang } { global result_dir - return [file join $result_dir "$test.def"] + return [file join $result_dir "$test-$lang.def"] +} + +proc lang_flag { lang } { + if {$lang == "py"} { + return "-python" + } + return "" } proc test_tmp_file { test } { @@ -584,19 +616,19 @@ proc test_tmp_file { test } { return [file join $result_dir $test.tmp] } -proc test_valgrind_cmd_file { test } { +proc test_valgrind_cmd_file { test lang } { global result_dir - return [file join $result_dir $test.vg_cmd] + return [file join $result_dir $test-$lang.vg_cmd] } -proc test_valgrind_file { test } { +proc test_valgrind_file { test lang } { global result_dir - return [file join $result_dir $test.valgrind] + return [file join $result_dir $test-$lang.valgrind] } -proc test_core_file { test } { +proc test_core_file { test lang } { global result_dir - return [file join $result_dir $test.core] + return [file join $result_dir $test-$lang.core] } proc test_sys_core_file { test pid } { diff --git a/test/regression_vars.tcl b/test/regression_vars.tcl index 53a3baa797e..df50f826c8c 100644 --- a/test/regression_vars.tcl +++ b/test/regression_vars.tcl @@ -74,10 +74,18 @@ proc record_tests1 { tests cmp_logfile } { # Record a test in the regression suite. proc record_test { test cmd_dir pass_criteria } { - global cmd_dirs test_groups test_pass_criteria + global cmd_dirs test_groups test_pass_criteria test_langs set cmd_dirs($test) $cmd_dir lappend test_groups(all) $test set test_pass_criteria($test) $pass_criteria + set test_langs($test) [list] + if {[file exists [file join $cmd_dir "$test.tcl"]]} { + lappend test_langs($test) tcl + } + + if {[file exists [file join $cmd_dir "$test.py"]]} { + lappend test_langs($test) py + } return $test }