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Add tests for new template validation
Signed-off-by: Travis Collins <travis.collins@analog.com>
1 parent 899b237 commit 1d83710

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‎test/ad9081/__init__.py‎

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# AD9081 test module

‎test/ad9081/configs/vpk180_config.json‎

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{
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"converter": {
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"type": "ad9081"
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},
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"clock": {
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"vcxo": 100000000,
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"vco": 3000000000,
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"output_clocks": {
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"AD9081_ref_clk": {"divider": 6},
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"adc_sysref": {"divider": 256},
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"dac_sysref": {"divider": 256},
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"adc_fpga_ref_clk": {"divider": 8},
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"adc_fpga_link_out_clk": {"divider": 8},
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"dac_fpga_ref_clk": {"divider": 8},
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"dac_fpga_link_out_clk": {"divider": 8}
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}
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},
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"fpga_adc": {
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"sys_clk_select": "XCVR_QPLL0",
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"out_clk_select": "XCVR_REFCLK_DIV2"
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},
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"fpga_dac": {
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"sys_clk_select": "XCVR_QPLL0",
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"out_clk_select": "XCVR_REFCLK_DIV2"
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},
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"jesd_adc": {
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"M": 8,
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"L": 4,
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"S": 1,
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"F": 2,
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"K": 32,
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"Np": 16,
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"CS": 0,
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"HD": 1,
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"jesd_mode": 9,
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"jesd_class": "jesd204b",
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"converter_clock": 4000000000,
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"sample_clock": 250000000
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},
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"jesd_dac": {
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"M": 8,
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"L": 4,
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"S": 1,
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"F": 4,
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"K": 32,
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"Np": 16,
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"CS": 0,
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"HD": 0,
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"jesd_mode": 10,
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"jesd_class": "jesd204b",
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"converter_clock": 12000000000,
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"sample_clock": 500000000
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},
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"datapath_adc": {
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"cddc": {
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"enabled": [true, true, true, true],
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"decimations": [4, 4, 4, 4],
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"nco_frequencies": [0, 0, 0, 0]
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},
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"fddc": {
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"enabled": [true, true, true, true, true, true, true, true],
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"decimations": [1, 1, 1, 1, 1, 1, 1, 1],
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"nco_frequencies": [0, 0, 0, 0, 0, 0, 0, 0]
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}
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},
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"datapath_dac": {
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"cduc": {
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"enabled": [true, true, true, true],
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"interpolation": 6,
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"sources": [[0, 1], [2, 3], [4, 5], [6, 7]],
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"nco_frequencies": [0, 0, 0, 0]
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},
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"fduc": {
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"enabled": [true, true, true, true, true, true, true, true],
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"interpolation": 4,
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"nco_frequencies": [0, 0, 0, 0, 0, 0, 0, 0]
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}
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}
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}

‎test/ad9081/configs/zc706_config.json‎

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{
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"converter": {
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"type": "ad9081"
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},
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"clock": {
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"vcxo": 100000000,
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"vco": 3000000000,
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"output_clocks": {
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"AD9081_ref_clk": {"divider": 6},
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"adc_sysref": {"divider": 256},
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"dac_sysref": {"divider": 256},
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"adc_fpga_ref_clk": {"divider": 8},
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"adc_fpga_link_out_clk": {"divider": 8},
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"dac_fpga_ref_clk": {"divider": 8},
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"dac_fpga_link_out_clk": {"divider": 8}
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}
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},
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"fpga_adc": {
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"sys_clk_select": "XCVR_QPLL",
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"out_clk_select": "XCVR_REFCLK_DIV2"
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},
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"fpga_dac": {
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"sys_clk_select": "XCVR_QPLL",
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"out_clk_select": "XCVR_REFCLK_DIV2"
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},
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"jesd_adc": {
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"M": 8,
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"L": 4,
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"S": 1,
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"F": 2,
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"K": 32,
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"Np": 16,
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"CS": 0,
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"HD": 1,
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"jesd_mode": 9,
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"jesd_class": "jesd204b",
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"converter_clock": 4000000000,
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"sample_clock": 250000000
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},
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"jesd_dac": {
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"M": 8,
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"L": 4,
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"S": 1,
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"F": 4,
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"K": 32,
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"Np": 16,
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"CS": 0,
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"HD": 0,
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"jesd_mode": 10,
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"jesd_class": "jesd204b",
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"converter_clock": 12000000000,
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"sample_clock": 500000000
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},
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"datapath_adc": {
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"cddc": {
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"enabled": [true, true, true, true],
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"decimations": [4, 4, 4, 4],
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"nco_frequencies": [0, 0, 0, 0]
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},
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"fddc": {
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"enabled": [true, true, true, true, true, true, true, true],
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"decimations": [1, 1, 1, 1, 1, 1, 1, 1],
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"nco_frequencies": [0, 0, 0, 0, 0, 0, 0, 0]
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}
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},
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"datapath_dac": {
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"cduc": {
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"enabled": [true, true, true, true],
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"interpolation": 6,
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"sources": [[0, 1], [2, 3], [4, 5], [6, 7]],
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"nco_frequencies": [0, 0, 0, 0]
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},
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"fduc": {
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"enabled": [true, true, true, true, true, true, true, true],
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"interpolation": 4,
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"nco_frequencies": [0, 0, 0, 0, 0, 0, 0, 0]
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}
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}
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}

‎test/ad9081/configs/zcu102_config.json‎

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{
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"converter": {
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"type": "ad9081"
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},
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"clock": {
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"vcxo": 100000000,
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"vco": 3000000000,
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"output_clocks": {
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"AD9081_ref_clk": {"divider": 6},
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"adc_sysref": {"divider": 256},
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"dac_sysref": {"divider": 256},
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"adc_fpga_ref_clk": {"divider": 8},
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"adc_fpga_link_out_clk": {"divider": 8},
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"dac_fpga_ref_clk": {"divider": 8},
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"dac_fpga_link_out_clk": {"divider": 8}
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}
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},
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"fpga_adc": {
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"sys_clk_select": "XCVR_QPLL",
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"out_clk_select": "XCVR_REFCLK_DIV2"
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},
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"fpga_dac": {
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"sys_clk_select": "XCVR_QPLL",
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"out_clk_select": "XCVR_REFCLK_DIV2"
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},
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"jesd_adc": {
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"M": 8,
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"L": 4,
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"S": 1,
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"F": 2,
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"K": 32,
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"Np": 16,
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"CS": 0,
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"HD": 1,
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"jesd_mode": 9,
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"jesd_class": "jesd204b",
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"converter_clock": 4000000000,
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"sample_clock": 250000000
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},
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"jesd_dac": {
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"M": 8,
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"L": 4,
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"S": 1,
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"F": 4,
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"K": 32,
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"Np": 16,
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"CS": 0,
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"HD": 0,
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"jesd_mode": 10,
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"jesd_class": "jesd204b",
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"converter_clock": 12000000000,
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"sample_clock": 500000000
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},
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"datapath_adc": {
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"cddc": {
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"enabled": [true, true, true, true],
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"decimations": [4, 4, 4, 4],
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"nco_frequencies": [0, 0, 0, 0]
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},
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"fddc": {
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"enabled": [true, true, true, true, true, true, true, true],
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"decimations": [1, 1, 1, 1, 1, 1, 1, 1],
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"nco_frequencies": [0, 0, 0, 0, 0, 0, 0, 0]
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}
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},
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"datapath_dac": {
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"cduc": {
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"enabled": [true, true, true, true],
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"interpolation": 6,
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"sources": [[0, 1], [2, 3], [4, 5], [6, 7]],
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"nco_frequencies": [0, 0, 0, 0]
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},
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"fduc": {
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"enabled": [true, true, true, true, true, true, true, true],
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"interpolation": 4,
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"nco_frequencies": [0, 0, 0, 0, 0, 0, 0, 0]
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}
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}
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}

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