Add AD9084 VCU118 hardware test with adijif profile-driven DTS generation

- Add vcu118 (MicroBlaze) platform support to ad9084_fmc board class
- Add ad9084_fmc_vcu118.tmpl: profile-specific macro defines + base DTS include
- Update test to use adijif to parse Apollo profiles, solve clock/JESD config,
  generate a per-profile DTS, and build/deploy the resulting simpleImage
- Each profile yields a vcu118_ad9084_{profile}.dts placed in the kernel tree
  before the MicroBlaze simpleImage build

Author: tfcollins

adidt/boards/ad9084_fmc.py

@@ -55,6 +55,19 @@ class ad9084_fmc(layout):
             "spi_bus": "spi0",
             "output_dir": "generated_dts",
         },
+        "vcu118": {
+            "template_filename": "ad9084_fmc_vcu118.tmpl",
+            # base_dts_file is None: VCU118 DTS is placed directly in the kernel tree
+            # The generated DTS includes the existing hardware base DTS from the kernel
+            "base_dts_file": None,
+            "base_dts_include": "vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.dts",
+            "arch": "microblaze",
+            "jesd_phy": "GTY",
+            "default_fpga_adc_pll": "XCVR_QPLL1",
+            "default_fpga_dac_pll": "XCVR_QPLL1",
+            "spi_bus": "axi_spi_2",
+            "output_dir": None,  # Set directly via output_filename in tests
+        },
     }
 
     template_filename = "ad9084_fmc_vpk180.tmpl"
@@ -85,9 +98,12 @@ def __init__(self, platform="vpk180", kernel_path=None):
         # Set template and output based on platform
         self.template_filename = self.platform_config["template_filename"]
         base_name = f"ad9084_fmc_{platform}.dts"
-        self.output_filename = os.path.join(
-            self.platform_config["output_dir"], base_name
-        )
+        output_dir = self.platform_config["output_dir"]
+        if output_dir is not None:
+            self.output_filename = os.path.join(output_dir, base_name)
+        else:
+            # No default output dir (e.g. VCU118): caller must set output_filename
+            self.output_filename = base_name
 
         # Store original kernel_path argument to determine validation strategy
         self._kernel_path_explicit = kernel_path is not None
@@ -147,6 +163,11 @@ def _validate_kernel_path(self):
                 f"  3. Clone kernel source to {self.DEFAULT_KERNEL_PATH}"
             )
 
+        # Skip base DTS validation if not specified (e.g. VCU118 where the
+        # generated DTS is placed directly in the kernel tree)
+        if self.platform_config["base_dts_file"] is None:
+            return
+
         base_dts_path = os.path.join(
             self.kernel_path, self.platform_config["base_dts_file"]
         )

adidt/templates/ad9084_fmc_vcu118.tmpl

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+// AUTOGENERATED BY PYADI-DT {{ date }}
+/*
+ * Analog Devices AD9084-FMCA-EBZ
+ * Platform: VCU118 (MicroBlaze)
+ * Profile: {{ profile_name }}
+ * Generated from: {{ config_source }}
+ *
+ * hdl_project: <ad9084_fmc/vcu118>
+ * Copyright (C) 2025 Analog Devices Inc.
+ */
+
+/* --- Profile-specific configuration (generated by adijif) --- */
+
+#ifndef DEVICE_PROFILE_NAME
+#define DEVICE_PROFILE_NAME	"{{ profile_name }}.bin"
+#endif
+
+/* RX JESD204C path */
+#ifndef AD9084_RX_LANERATE_KHZ
+#define AD9084_RX_LANERATE_KHZ	{{ rx_lanerate_khz | int }}
+#endif
+#ifndef AD9084_RX_LINK_CLK
+#define AD9084_RX_LINK_CLK	{{ rx_link_clk | int }}
+#endif
+
+/* TX JESD204C path */
+#ifndef AD9084_TX_LANERATE_KHZ
+#define AD9084_TX_LANERATE_KHZ	{{ tx_lanerate_khz | int }}
+#endif
+#ifndef AD9084_TX_LINK_CLK
+#define AD9084_TX_LINK_CLK	{{ tx_link_clk | int }}
+#endif
+
+/* SYSREF from ADF4030 */
+#ifndef SYSREF_CLK_HZ
+#define SYSREF_CLK_HZ	{{ sysref_hz | int }}
+#endif
+
+/* JESD204C parameters */
+#define AD9084_JESD_M	{{ jesd_m | int }}
+#define AD9084_JESD_L	{{ jesd_l | int }}
+#define AD9084_JESD_S	{{ jesd_s | int }}
+#define AD9084_JESD_NP	{{ jesd_np | int }}
+#define AD9084_JESD_F	{{ jesd_f | int }}
+
+/* ADF4382 device clock: {{ device_clock_hz | int }} Hz */
+
+/* Include base VCU118 AD9084 FMC hardware description.
+ * This file contains the MicroBlaze processor, AXI peripherals,
+ * JESD204 cores, DMA engines, and SPI device nodes.
+ * The macros above parameterise the profile-specific settings. */
+#include "{{ base_dts_include }}"

test/ad9084/2023_R2.yaml

@@ -0,0 +1,24 @@
+# ADI Linux Kernel Build Configuration for ad9084 development branch
+# This configuration supports building the ADI Linux kernel for Microblaze
+
+project: linux
+repository: https://github.com/analogdevicesinc/linux.git
+tag: staging/xlnx/main-next-ad9084-dev
+
+build:
+  parallel_jobs: 4
+  clean_before: false
+  output_dir: ./build
+
+platforms:
+  microblaze:
+    arch: microblaze
+    cross_compile: microblazeel-xilinx-linux-gnu-
+    defconfig: adi_mb_apollo_defconfig
+    kernel_target: simpleImage.vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.strip
+    simpleimage_targets:
+      - simpleImage.vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4
+    dtbs: []
+
+    toolchain:
+      preferred: vivado