|
| 1 | +from .layout import layout |
| 2 | +from ..parts.adrv9009 import parse_profile |
| 3 | +import numpy as np |
| 4 | +import os |
| 5 | + |
| 6 | + |
| 7 | +class adrv9009_zu11eg(layout): |
| 8 | + """ADRV9009-ZU11EG SOM board layout map for clocks and DSP""" |
| 9 | + |
| 10 | + clock = "HMC7044" |
| 11 | + |
| 12 | + adc = "adrv9009_rx" |
| 13 | + dac = "adrv9009_tx" |
| 14 | + |
| 15 | + template_filename = "adrv9009_zu11eg.dts" |
| 16 | + output_filename = "adrv9009_zu11eg_out.dts" |
| 17 | + |
| 18 | + profile = None |
| 19 | + |
| 20 | + def make_ints(self, cfg, keys): |
| 21 | + """Convert keys in a dict to integers. |
| 22 | +
|
| 23 | + Args: |
| 24 | + cfg (dict): Configuration. |
| 25 | + keys (list): Keys to convert. |
| 26 | +
|
| 27 | + Returns: |
| 28 | + dict: Configuration with keys converted to integers. |
| 29 | + """ |
| 30 | + for key in keys: |
| 31 | + if isinstance(cfg[key], float) and cfg[key].is_integer(): |
| 32 | + cfg[key] = int(cfg[key]) |
| 33 | + return cfg |
| 34 | + |
| 35 | + def map_jesd_structs(self, cfg): |
| 36 | + """Map JIF configuration to integer structs. |
| 37 | +
|
| 38 | + Args: |
| 39 | + cfg (dict): JIF configuration. |
| 40 | +
|
| 41 | + Returns: |
| 42 | + dict: ADC JESD structs. |
| 43 | + dict: DAC JESD structs. |
| 44 | + """ |
| 45 | + adc = cfg["converter"] |
| 46 | + adc["jesd"] = cfg["jesd_adc"] |
| 47 | + adc["jesd"]["jesd_class_int"] = self.map_jesd_subclass( |
| 48 | + adc["jesd"]["jesd_class"] |
| 49 | + ) |
| 50 | + dac = cfg["converter"].copy() |
| 51 | + dac["jesd"] = cfg["jesd_dac"] |
| 52 | + dac["jesd"]["jesd_class_int"] = self.map_jesd_subclass( |
| 53 | + dac["jesd"]["jesd_class"] |
| 54 | + ) |
| 55 | + |
| 56 | + adc["jesd"] = self.make_ints(adc["jesd"], ["converter_clock", "sample_clock"]) |
| 57 | + dac["jesd"] = self.make_ints(dac["jesd"], ["converter_clock", "sample_clock"]) |
| 58 | + |
| 59 | + adc["datapath"] = cfg["datapath_adc"] |
| 60 | + dac["datapath"] = cfg["datapath_dac"] |
| 61 | + |
| 62 | + return adc, dac |
| 63 | + |
| 64 | + def map_clocks_to_board_layout(self, cfg): |
| 65 | + """Map JIF configuration to board clock connection layout. |
| 66 | +
|
| 67 | + Args: |
| 68 | + cfg (dict): JIF configuration. |
| 69 | +
|
| 70 | + Returns: |
| 71 | + dict: Board clock connection layout. |
| 72 | + """ |
| 73 | + # Fix ups |
| 74 | + for key in ["vco", "vcxo"]: |
| 75 | + if isinstance(cfg["clock"][key], float) and cfg["clock"][key].is_integer(): |
| 76 | + cfg["clock"][key] = int(cfg["clock"][key]) |
| 77 | + |
| 78 | + map = {} |
| 79 | + clk = cfg["clock"]["output_clocks"] |
| 80 | + |
| 81 | + # Common |
| 82 | + map["DEV_REFCLK"] = { |
| 83 | + "source_port": 2, |
| 84 | + "divider": clk["AD9081_ref_clk"]["divider"], |
| 85 | + } |
| 86 | + map["DEV_SYSREF"] = { |
| 87 | + "source_port": 3, |
| 88 | + "divider": np.max( |
| 89 | + [clk["adc_sysref"]["divider"], clk["dac_sysref"]["divider"]] |
| 90 | + ), |
| 91 | + } |
| 92 | + map["FPGA_SYSREF"] = { |
| 93 | + "source_port": 13, |
| 94 | + "divider": np.max( |
| 95 | + [clk["adc_fpga_ref_clk"]["divider"], clk["dac_fpga_ref_clk"]["divider"]] |
| 96 | + ), |
| 97 | + } |
| 98 | + |
| 99 | + # RX side |
| 100 | + map["CORE_CLK_RX"] = { |
| 101 | + "source_port": 0, |
| 102 | + "divider": clk["adc_fpga_ref_clk"]["divider"], |
| 103 | + } |
| 104 | + map["CORE_CLK_RX_ALT"] = { |
| 105 | + "source_port": 10, |
| 106 | + "divider": clk["adc_fpga_ref_clk"]["divider"] * 2, |
| 107 | + } |
| 108 | + map["FPGA_REFCLK1"] = { |
| 109 | + "source_port": 8, |
| 110 | + "divider": clk["adc_fpga_ref_clk"]["divider"], |
| 111 | + } |
| 112 | + |
| 113 | + # Tx side |
| 114 | + map["CORE_CLK_TX"] = { |
| 115 | + "source_port": 6, |
| 116 | + "divider": clk["dac_fpga_ref_clk"]["divider"], |
| 117 | + } |
| 118 | + map["FPGA_REFCLK2"] = { |
| 119 | + "source_port": 12, |
| 120 | + "divider": clk["dac_fpga_ref_clk"]["divider"], |
| 121 | + } |
| 122 | + |
| 123 | + ccfg = {"map": map, "clock": cfg["clock"]} |
| 124 | + |
| 125 | + fpga = {} |
| 126 | + fpga["fpga_adc"] = cfg["fpga_adc"] |
| 127 | + fpga["fpga_dac"] = cfg["fpga_dac"] |
| 128 | + |
| 129 | + # Check all clocks are mapped |
| 130 | + # FIXME |
| 131 | + |
| 132 | + # Check no source_port is mapped to more than one clock |
| 133 | + # FIXME |
| 134 | + adc, dac = self.map_jesd_structs(cfg) |
| 135 | + |
| 136 | + return ccfg, adc, dac, fpga |
| 137 | + |
| 138 | + def parse_profile(self, filename): |
| 139 | + """Parse a profile file. |
| 140 | +
|
| 141 | + Args: |
| 142 | + filename (str): Profile file name. |
| 143 | +
|
| 144 | + Returns: |
| 145 | + dict: Profile configuration. |
| 146 | + """ |
| 147 | + if not os.path.exists(filename): |
| 148 | + raise Exception(f"Profile file not found: {filename}") |
| 149 | + self.profile = parse_profile(filename) |
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