diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index b9d7bd31fad12..dab316ca967b3 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -129,6 +129,7 @@ config ARCH_CHIP_ESP32C3 select ARCH_HAVE_RAMFUNCS select ONESHOT_COUNT if ONESHOT select ONESHOT_FAST_DIVISION if ONESHOT + select ARCH_MINIMAL_VECTORTABLE ---help--- ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory @@ -162,6 +163,7 @@ config ARCH_CHIP_ESP32C6 select ARCH_HAVE_RAMFUNCS select ONESHOT_COUNT if ONESHOT select ONESHOT_FAST_DIVISION if ONESHOT + select ARCH_MINIMAL_VECTORTABLE ---help--- Espressif ESP32-C6 (RV32IMAC). @@ -194,6 +196,7 @@ config ARCH_CHIP_ESP32H2 select ARCH_HAVE_RAMFUNCS select ONESHOT_COUNT if ONESHOT select ONESHOT_FAST_DIVISION if ONESHOT + select ARCH_MINIMAL_VECTORTABLE ---help--- Espressif ESP32-H2 (RV32IMC). diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig index cb4940cc65415..443a06ce3733e 100644 --- a/arch/risc-v/src/common/espressif/Kconfig +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -130,6 +130,63 @@ config ESPRESSIF_SOC_RTC_MEM_SUPPORTED bool default n +menu "Espressif Log Level" + visible if DEBUG_FEATURES + +config ESPRESSIF_LOG_LEVEL_NONE + bool "NONE" + depends on !DEBUG_FEATURES && !DEBUG_ERROR && !DEBUG_WARN && !DEBUG_INFO + default y + ---help--- + No log output from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_ERROR + bool "ERROR" + depends on DEBUG_ERROR + default y + ---help--- + Display critical errors from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_WARN + bool "WARN" + depends on DEBUG_WARN + default y + ---help--- + Display warning messages from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_INFO + bool "INFO" + depends on DEBUG_INFO + default y + ---help--- + Display information messages from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_DEBUG + bool "DEBUG" + depends on DEBUG_INFO + default n + ---help--- + Display extra information from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_VERBOSE + bool "VERBOSE" + depends on DEBUG_INFO + default n + ---help--- + Display bigger chunks of debugging information, or frequent messages + which can potentially flood the output from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL + int + default 5 if ESPRESSIF_LOG_LEVEL_VERBOSE + default 4 if ESPRESSIF_LOG_LEVEL_DEBUG + default 3 if ESPRESSIF_LOG_LEVEL_INFO + default 2 if ESPRESSIF_LOG_LEVEL_WARN + default 1 if ESPRESSIF_LOG_LEVEL_ERROR + default 0 if ESPRESSIF_LOG_LEVEL_NONE + +endmenu # Espressif Log Level + menu "Bootloader and Image Configuration" config ESPRESSIF_SIMPLE_BOOT @@ -921,7 +978,7 @@ config ESPRESSIF_GPIO_IRQ config ESPRESSIF_RTCIO_IRQ bool "RTC IO interrupts" default n - depends on !ARCH_CHIP_ESP32H2 && !ARCH_CHIP_ESP32C6 + depends on ARCH_CHIP_ESP32C3 ---help--- Enable support for RTC peripherals interrupts. @@ -1205,7 +1262,7 @@ config ESPRESSIF_TEMP ---help--- A built-in sensor used to measure the chip's internal temperature. -config ESP_WIRELESS +config ESPRESSIF_WIRELESS bool default n select NET @@ -1218,7 +1275,7 @@ config ESPRESSIF_WIFI bool "Wi-Fi" depends on ARCH_CHIP_ESP32C3 || ARCH_CHIP_ESP32C6 default n - select ESP_WIRELESS + select ESPRESSIF_WIRELESS ---help--- Enable Wi-Fi support @@ -1226,7 +1283,7 @@ config ESPRESSIF_BLE bool "BLE" depends on ARCH_CHIP_ESP32C3 default n - select ESP_WIRELESS + select ESPRESSIF_WIRELESS ---help--- Enable BLE support diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs index 3811cf92ef33c..2a7bdb6647c27 100644 --- a/arch/risc-v/src/common/espressif/Make.defs +++ b/arch/risc-v/src/common/espressif/Make.defs @@ -69,10 +69,6 @@ ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y) CHIP_CSRCS += esp_hr_timer.c esp_ets_timer_legacy.c endif -ifeq ($(CONFIG_ESPRESSIF_DMA),y) - CHIP_CSRCS += esp_dma.c -endif - ifeq ($(CONFIG_ESPRESSIF_EFUSE),y) CHIP_CSRCS += esp_efuse.c endif @@ -150,7 +146,7 @@ ifeq ($(CONFIG_ESPRESSIF_SPIFLASH),y) endif endif -ifeq ($(CONFIG_ESP_WIRELESS),y) +ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y) ifeq ($(CONFIG_ESPRESSIF_WIFI),y) CHIP_CSRCS += esp_wifi_event_handler.c CHIP_CSRCS += esp_wifi_api.c @@ -207,7 +203,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = bb255ca422f4b4d60c9f4f74dbdf51316dc2b669 + ESP_HAL_3RDPARTY_VERSION = a85ce2f1bad9f745090146eb30a18d91b8ddd309 endif ifndef ESP_HAL_3RDPARTY_URL @@ -247,11 +243,14 @@ chip/$(ESP_HAL_3RDPARTY_REPO): $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" $(Q) $(call CLONE_ESP_HAL_3RDPARTY_REPO) ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y) + $(Q) echo "Espressif HAL for 3rd Party Platforms: cleaning current repository..." + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) clean -ffdx + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) reset --quiet --hard --recurse-submodules || true $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls endif -ifeq ($(CONFIG_ESP_WIRELESS),y) +ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y) ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y) $(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..." $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32c3_family components/esp_coex/lib @@ -265,7 +264,7 @@ include common$(DELIM)espressif$(DELIM)Bootloader.mk # Silent preprocessor warnings -CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion +CFLAGS += -Wno-shadow -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations # Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration @@ -273,7 +272,7 @@ CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) include chip/hal_${CHIP_SERIES}.mk -ifeq ($(CONFIG_ESP_WIRELESS),y) +ifeq ($(CONFIG_ESPRESSIF_WIRELESS),y) include common$(DELIM)espressif$(DELIM)Wireless.mk endif diff --git a/arch/risc-v/src/common/espressif/Wireless.mk b/arch/risc-v/src/common/espressif/Wireless.mk index 33f886a0e3c63..a30f6527c6dc2 100644 --- a/arch/risc-v/src/common/espressif/Wireless.mk +++ b/arch/risc-v/src/common/espressif/Wireless.mk @@ -22,6 +22,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)$(DELIM)wifi_apps$(DELIM)roaming_app$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi @@ -43,15 +44,20 @@ endif VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls ### Define Espressif's configs for mbedTLS CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="" +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src + CHIP_CSRCS += aes.c CHIP_CSRCS += aria.c CHIP_CSRCS += bignum_core.c @@ -88,16 +94,42 @@ CHIP_CSRCS += hmac_drbg.c CHIP_CSRCS += rsa_alt_helpers.c CHIP_CSRCS += ecdh.c CHIP_CSRCS += pk_ecc.c +CHIP_CSRCS += pk_rsa.c +CHIP_CSRCS += psa_util.c +CHIP_CSRCS += psa_crypto_ffdh.c +CHIP_CSRCS += psa_crypto_ecp.c +CHIP_CSRCS += psa_crypto_rsa.c +CHIP_CSRCS += psa_crypto_cipher.c +CHIP_CSRCS += psa_crypto_mac.c +CHIP_CSRCS += psa_crypto_hash.c + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core + +CHIP_CSRCS += psa_crypto_client.c +CHIP_CSRCS += psa_crypto_driver_wrappers_no_static.c +CHIP_CSRCS += psa_crypto_slot_management.c +CHIP_CSRCS += psa_crypto_storage.c +CHIP_CSRCS += psa_crypto.c +CHIP_CSRCS += psa_its_file.c +CHIP_CSRCS += tf_psa_crypto_config.c +CHIP_CSRCS += tf_psa_crypto_version.c VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port +CHIP_CSRCS += esp_psa_crypto_init.c CHIP_CSRCS += esp_hardware.c CHIP_CSRCS += esp_mem.c CHIP_CSRCS += esp_timing.c -VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md +# Ensure PSA crypto initialization is included in the build + +LDFLAGS += -u mbedtls_psa_crypto_init_include_impl + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_mac +CHIP_CSRCS += psa_crypto_driver_esp_hmac_opaque.c -CHIP_CSRCS += esp_md.c +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_md +CHIP_CSRCS += psa_crypto_driver_esp_md5.c ## WPA Supplicant @@ -110,6 +142,7 @@ CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1 +CFLAGS += $(DEFINE_PREFIX)TF_PSA_CRYPTO_USER_CONFIG_FILE=\"mbedtls/esp_config.h\" CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL @@ -174,7 +207,6 @@ VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto CHIP_CSRCS += aes-ccm.c CHIP_CSRCS += aes-gcm.c -CHIP_CSRCS += aes-omac1.c CHIP_CSRCS += aes-unwrap.c CHIP_CSRCS += aes-wrap.c CHIP_CSRCS += ccmp.c diff --git a/arch/risc-v/src/common/espressif/chip.h b/arch/risc-v/src/common/espressif/chip.h index c86b62ea367b0..48868482f617f 100644 --- a/arch/risc-v/src/common/espressif/chip.h +++ b/arch/risc-v/src/common/espressif/chip.h @@ -31,6 +31,9 @@ #include "esp_memorymap.h" +#include "riscv_internal.h" +#include "riscv_percpu.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/risc-v/src/common/espressif/esp_adc.c b/arch/risc-v/src/common/espressif/esp_adc.c index 308b35920a210..72123bf071c15 100644 --- a/arch/risc-v/src/common/espressif/esp_adc.c +++ b/arch/risc-v/src/common/espressif/esp_adc.c @@ -46,7 +46,7 @@ #include "hal/adc_oneshot_hal.h" #include "hal/adc_ll.h" #include "hal/sar_ctrl_ll.h" -#include "soc/adc_periph.h" +#include "hal/adc_periph.h" #include "soc/periph_defs.h" #include "esp_clk_tree.h" @@ -436,6 +436,7 @@ static int esp_adc_oneshot_read(struct adc_dev_s *dev) adc_set_hw_calibration_code(priv->unit, atten); } + adc_oneshot_ll_disable_all_unit(); ret = adc_oneshot_hal_convert(hal, &raw_value); if (!ret) { @@ -737,6 +738,9 @@ struct adc_dev_s *esp_adc_initialize(int adc_num, #ifdef CONFIG_ESPRESSIF_ADC_1 dev = &g_adcdev1; priv = &g_adcpriv1; +# ifdef CONFIG_ARCH_CHIP_ESP32C3 + adc_ll_enable_calibration_ref(ADC_UNIT_1, false); +# endif break; #endif } diff --git a/arch/risc-v/src/common/espressif/esp_dedic_gpio.c b/arch/risc-v/src/common/espressif/esp_dedic_gpio.c index d31101898c08e..9898038c42ec9 100644 --- a/arch/risc-v/src/common/espressif/esp_dedic_gpio.c +++ b/arch/risc-v/src/common/espressif/esp_dedic_gpio.c @@ -38,7 +38,8 @@ #include "riscv_internal.h" #include "esp_dedic_gpio.h" #include "esp_gpio.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" +#include "hal/dedic_gpio_caps.h" #include "hal/dedic_gpio_cpu_ll.h" /**************************************************************************** @@ -259,9 +260,9 @@ struct file *esp_dedic_gpio_new_bundle( flags = spin_lock_irqsave(&dedic_gpio_common.spinlock); dedic_gpio_common.out_occupied_mask = - UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1); + UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1); dedic_gpio_common.in_occupied_mask = - UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1); + UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1); spin_unlock_irqrestore(&dedic_gpio_common.spinlock, flags); } @@ -278,11 +279,12 @@ struct file *esp_dedic_gpio_new_bundle( out_offset = 0; if (config->flags->output_enable) { - if (config->array_size > SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) + if (config->array_size > DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) { gpioerr("ERROR: array size(%d) exceeds maximum supported out\ channels(%d)\n", - config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM); + config->array_size, + DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)); free(priv); return NULL; } @@ -290,7 +292,8 @@ struct file *esp_dedic_gpio_new_bundle( flags = spin_lock_irqsave(&dedic_gpio_common.spinlock); for (int i = 0; - i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size; + i <= DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - \ + config->array_size; i++) { if ((dedic_gpio_common.out_occupied_mask & (pattern << i)) @@ -322,11 +325,12 @@ struct file *esp_dedic_gpio_new_bundle( if (config->flags->input_enable) { - if (config->array_size > SOC_DEDIC_GPIO_IN_CHANNELS_NUM) + if (config->array_size > DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) { gpioerr("ERROR: array size(%d) exceeds maximum supported in\ channels(%d)\n", - config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM); + config->array_size, + DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)); free(priv); return NULL; } @@ -334,7 +338,8 @@ struct file *esp_dedic_gpio_new_bundle( flags = spin_lock_irqsave(&dedic_gpio_common.spinlock); for (int i = 0; - i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size; + i <= DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - \ + config->array_size; i++) { if ((dedic_gpio_common.in_occupied_mask & (pattern << i)) == 0) diff --git a/arch/risc-v/src/common/espressif/esp_dma.c b/arch/risc-v/src/common/espressif/esp_dma.c deleted file mode 100644 index ec76a1c5bca83..0000000000000 --- a/arch/risc-v/src/common/espressif/esp_dma.c +++ /dev/null @@ -1,527 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/common/espressif/esp_dma.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "riscv_internal.h" -#include "esp_dma.h" - -#include "soc/gdma_periph.h" -#include "hal/gdma_hal.h" -#include "hal/gdma_hal_ahb.h" -#include "hal/gdma_types.h" -#include "hal/gdma_ll.h" -#include "periph_ctrl.h" -#include "hal/dma_types.h" - -/**************************************************************************** - * Pre-processor Macros - ****************************************************************************/ - -/* DMA channel number */ - -#define ESPRESSIF_DMA_CHAN_MAX (SOC_GDMA_PAIRS_PER_GROUP_MAX) - -#if !SOC_RCC_IS_INDEPENDENT -#define GDMA_RCC_ATOMIC() PERIPH_RCC_ATOMIC() -#else -#define GDMA_RCC_ATOMIC() -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static bool g_dma_chan_used[ESPRESSIF_DMA_CHAN_MAX]; -static mutex_t g_dma_lock = NXMUTEX_INITIALIZER; -static gdma_hal_context_t ctx; -static gdma_hal_config_t cfg = -{ - .group_id = 0 -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_dma_request - * - * Description: - * Request DMA channel and config it with given parameters. - * - * Input Parameters: - * periph - Peripheral for which the DMA channel request was made - * tx_prio - Interrupt priority - * rx_prio - Interrupt flags - * burst_en - Enable burst transmission - * - * Returned Value: - * DMA channel number (>=0) if success or -1 if fail. - * - ****************************************************************************/ - -int32_t esp_dma_request(enum esp_dma_periph_e periph, - uint32_t tx_prio, - uint32_t rx_prio, - bool burst_en) -{ - int chan; - - DEBUGASSERT((periph <= (int)ESPRESSIF_DMA_PERIPH_PARLIO)); - - DEBUGASSERT(tx_prio <= GDMA_LL_CHANNEL_MAX_PRIORITY); - DEBUGASSERT(rx_prio <= GDMA_LL_CHANNEL_MAX_PRIORITY); - - dmainfo("periph=%" PRIu32 " tx_prio=%" PRIu32 " rx_prio=%" PRIu32 "\n", - (uint32_t)periph, tx_prio, rx_prio); - - nxmutex_lock(&g_dma_lock); - - for (chan = 0; chan < ESPRESSIF_DMA_CHAN_MAX; chan++) - { - if (!g_dma_chan_used[chan]) - { - g_dma_chan_used[chan] = true; - break; - } - } - - if (chan == ESPRESSIF_DMA_CHAN_MAX) - { - dmaerr("No available GDMA channel for allocation\n"); - - nxmutex_unlock(&g_dma_lock); - return ERROR; - } - - dmainfo("Allocated channel=%d\n", chan); - - gdma_hal_connect_peri(&ctx, chan, GDMA_CHANNEL_DIRECTION_TX, - periph, periph); - gdma_hal_connect_peri(&ctx, chan, GDMA_CHANNEL_DIRECTION_RX, - periph, periph); - - if (burst_en) - { - /* Enable DMA TX/RX channels burst sending data */ - - /* Enable DMA TX/RX channels burst reading descriptor link */ - - gdma_hal_enable_burst(&ctx, chan, GDMA_CHANNEL_DIRECTION_TX, - true, true); - gdma_hal_enable_burst(&ctx, chan, GDMA_CHANNEL_DIRECTION_RX, - true, true); - } - - /* Set priority for DMA TX/RX channels */ - - gdma_hal_set_priority(&ctx, chan, GDMA_CHANNEL_DIRECTION_TX, tx_prio); - gdma_hal_set_priority(&ctx, chan, GDMA_CHANNEL_DIRECTION_RX, rx_prio); - - nxmutex_unlock(&g_dma_lock); - return chan; -} - -/**************************************************************************** - * Name: esp_dma_setup - * - * Description: - * Set up DMA descriptor with given parameters. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * dmadesc - DMA descriptor pointer - * num - DMA descriptor number - * pbuf - Buffer pointer - * len - Buffer length by byte - * - * Returned Value: - * Bind pbuf data bytes. - * - ****************************************************************************/ - -uint32_t esp_dma_setup(int chan, bool tx, - struct esp_dmadesc_s *dmadesc, uint32_t num, - uint8_t *pbuf, uint32_t len) -{ - int i; - uint32_t regval; - uint32_t bytes = len; - uint8_t *pdata = pbuf; - uint32_t data_len; - uint32_t buf_len; - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - dma_descriptor_t *dma_desc = (dma_descriptor_t *)dmadesc; - - DEBUGASSERT(chan >= 0); - DEBUGASSERT(dmadesc != NULL); - DEBUGASSERT(num > 0); - DEBUGASSERT(pbuf != NULL); - DEBUGASSERT(len > 0); - - for (i = 0; i < num; i++) - { - data_len = MIN(bytes, ESPRESSIF_DMA_BUFLEN_MAX); - - /* Buffer length must be rounded to next 32-bit boundary. */ - - buf_len = ALIGN_UP(data_len, sizeof(uintptr_t)); - - dma_desc[i].dw0.size = buf_len; - dma_desc[i].dw0.length = data_len; - dma_desc[i].dw0.owner = 1; - dma_desc[i].buffer = pdata; - - dmadesc[i].next = &dmadesc[i + 1]; - - bytes -= data_len; - if (bytes == 0) - { - break; - } - - pdata += data_len; - } - - dma_desc[i].dw0.suc_eof = 1; - dmadesc[i].next = NULL; - - gdma_hal_reset(&ctx, chan, dir); - - if (tx) - { - /* Set the descriptor link base address for TX channel */ - - gdma_ll_tx_set_desc_addr(ctx.dev, chan, (uint32_t)dmadesc); - } - else - { - /* Set the descriptor link base address for RX channel */ - - gdma_ll_rx_set_desc_addr(ctx.dev, chan, (uint32_t)dmadesc); - } - - return len - bytes; -} - -/**************************************************************************** - * Name: esp_dma_load - * - * Description: - * Load the address of the first DMA descriptor of an already bound - * inlink/outlink to the corresponding GDMA_LINK_ADDR_CHn register - * - * Input Parameters: - * dmadesc - Pointer of the previously bound inlink/outlink - * chan - DMA channel of the receiver/transmitter - * tx - true: TX mode (transmitter); false: RX mode (receiver) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp_dma_load(struct esp_dmadesc_s *dmadesc, int chan, bool tx) -{ - uint32_t regval; - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - - DEBUGASSERT(chan >= 0); - DEBUGASSERT(dmadesc != NULL); - - gdma_hal_reset(&ctx, chan, dir); - gdma_hal_start_with_desc(&ctx, chan, dir, (uint32_t)dmadesc); -} - -/**************************************************************************** - * Name: esp_dma_enable_interrupt - * - * Description: - * Enable/Disable DMA interrupt. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * mask - Interrupt mask to change - * en - true: enable; false: disable - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_enable_interrupt(int chan, bool tx, uint32_t mask, bool en) -{ - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - gdma_hal_enable_intr(&ctx, chan, dir, mask, en); -} - -/**************************************************************************** - * Name: esp_dma_get_interrupt - * - * Description: - * Gets DMA interrupt status. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * Interrupt status value. - * - ****************************************************************************/ - -int esp_dma_get_interrupt(int chan, bool tx) -{ - uint32_t intr_status = 0; - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - return gdma_hal_read_intr_status(&ctx, chan, dir, false); -} - -/**************************************************************************** - * Name: esp_dma_clear_interrupt - * - * Description: - * Clear DMA interrupt. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * mask - Interrupt mask to change - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_clear_interrupt(int chan, bool tx, uint32_t mask) -{ - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - gdma_hal_clear_intr(&ctx, chan, dir, mask); -} - -/**************************************************************************** - * Name: esp_dma_get_desc_addr - * - * Description: - * Gets desc addr of DMA interrupt. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * Desc addr. - * - ****************************************************************************/ - -int esp_dma_get_desc_addr(int chan, bool tx) -{ - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - return gdma_hal_get_eof_desc_addr(&ctx, chan, dir, true); -} - -/**************************************************************************** - * Name: esp_dma_enable - * - * Description: - * Enable DMA channel transmission. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_enable(int chan, bool tx) -{ - if (tx) - { - gdma_ll_tx_start(ctx.dev, chan); - } - else - { - gdma_ll_rx_start(ctx.dev, chan); - } -} - -/**************************************************************************** - * Name: esp_dma_disable - * - * Description: - * Disable DMA channel transmission. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_disable(int chan, bool tx) -{ - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - gdma_hal_stop(&ctx, chan, dir); -} - -/**************************************************************************** - * Name: esp_dma_wait_idle - * - * Description: - * Wait until transmission ends. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_wait_idle(int chan, bool tx) -{ - if (tx) - { - while (gdma_ll_tx_is_desc_fsm_idle(ctx.dev, chan) == 0); - } - else - { - while (gdma_ll_rx_is_desc_fsm_idle(ctx.dev, chan) == 0); - } -} - -/**************************************************************************** - * Name: esp_dma_reset_channel - * - * Description: - * Resets dma channel. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_reset_channel(int chan, bool tx) -{ - gdma_channel_direction_t dir = tx == true ? GDMA_CHANNEL_DIRECTION_TX : \ - GDMA_CHANNEL_DIRECTION_RX; - gdma_hal_reset(&ctx, chan, dir); -} - -/**************************************************************************** - * Name: esp_dma_init - * - * Description: - * Initialize DMA driver. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_init(void) -{ - periph_module_enable(PERIPH_GDMA_MODULE); - GDMA_RCC_ATOMIC() - { - gdma_ll_enable_bus_clock(0, true); - } - - gdma_ahb_hal_init(&ctx, &cfg); - gdma_ll_force_enable_reg_clock(ctx.dev, true); -} - -/**************************************************************************** - * Name: esp_dma_deinit - * - * Description: - * Deinitialize DMA driver. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_deinit(void) -{ - nxmutex_lock(&g_dma_lock); - - /* Disable DMA clock gating */ - - gdma_ll_force_enable_reg_clock(ctx.dev, false); - GDMA_RCC_ATOMIC() - { - gdma_ll_enable_bus_clock(0, false); - } - - /* Disable DMA module by gating the clock and asserting the reset - * signal. - */ - - periph_module_disable(PERIPH_GDMA_MODULE); - gdma_hal_deinit(&ctx); - - nxmutex_unlock(&g_dma_lock); -} diff --git a/arch/risc-v/src/common/espressif/esp_dma.h b/arch/risc-v/src/common/espressif/esp_dma.h deleted file mode 100644 index 57b2ded6b79d5..0000000000000 --- a/arch/risc-v/src/common/espressif/esp_dma.h +++ /dev/null @@ -1,330 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/common/espressif/esp_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_DMA_H -#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_DMA_H - -#include -#include -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Macros - ****************************************************************************/ - -/* DMA max data length */ - -#define ESPRESSIF_DMA_DATALEN_MAX (0x1000 - 4) - -/* DMA max buffer length */ - -#define ESPRESSIF_DMA_BUFLEN_MAX ESPRESSIF_DMA_DATALEN_MAX - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum esp_dma_periph_e -{ - ESPRESSIF_DMA_PERIPH_M2M, - ESPRESSIF_DMA_PERIPH_UHCI, - ESPRESSIF_DMA_PERIPH_SPI, - ESPRESSIF_DMA_PERIPH_I2S, - ESPRESSIF_DMA_PERIPH_AES, - ESPRESSIF_DMA_PERIPH_SHA, - ESPRESSIF_DMA_PERIPH_ADC, - ESPRESSIF_DMA_PERIPH_DAC, - ESPRESSIF_DMA_PERIPH_LCD, - ESPRESSIF_DMA_PERIPH_CAM, - ESPRESSIF_DMA_PERIPH_RMT, - ESPRESSIF_DMA_PERIPH_PARLIO, -}; - -/* DMA descriptor type */ - -struct esp_dmadesc_s -{ - uint32_t ctrl; /* DMA control block */ - const uint8_t *pbuf; /* DMA TX/RX buffer address */ - struct esp_dmadesc_s *next; /* Next DMA descriptor address */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_dma_request - * - * Description: - * Request DMA channel and config it with given parameters. - * - * Input Parameters: - * periph - Peripheral for which the DMA channel request was made - * tx_prio - Interrupt priority - * rx_prio - Interrupt flags - * - * Returned Value: - * DMA channel number (>=0) if success or -1 if fail. - * - ****************************************************************************/ - -int32_t esp_dma_request(enum esp_dma_periph_e periph, - uint32_t tx_prio, - uint32_t rx_prio, - bool burst_en); - -/**************************************************************************** - * Name: esp_dma_setup - * - * Description: - * Set up DMA descriptor with given parameters. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * dmadesc - DMA descriptor pointer - * num - DMA descriptor number - * pbuf - Buffer pointer - * len - Buffer length by byte - * - * Returned Value: - * Bind pbuf data bytes. - * - ****************************************************************************/ - -uint32_t esp_dma_setup(int chan, bool tx, - struct esp_dmadesc_s *dmadesc, uint32_t num, - uint8_t *pbuf, uint32_t len); - -/**************************************************************************** - * Name: esp_dma_load - * - * Description: - * Load the address of the first DMA descriptor of an already bound - * inlink/outlink to the corresponding GDMA_LINK_ADDR_CHn register - * - * Input Parameters: - * dmadesc - Pointer of the previously bound inlink/outlink - * chan - DMA channel of the receiver/transmitter - * tx - true: TX mode (transmitter); false: RX mode (receiver) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp_dma_load(struct esp_dmadesc_s *dmadesc, int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_enable_interrupt - * - * Description: - * Enable DMA interrupt. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * mask - Interrupt mask to change - * en - true: enable; false: disable - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_enable_interrupt(int chan, bool tx, uint32_t mask, bool en); - -/**************************************************************************** - * Name: esp_dma_get_interrupt - * - * Description: - * Gets DMA interrupt status. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * Interrupt status value. - * - ****************************************************************************/ - -int esp_dma_get_interrupt(int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_clear_interrupt - * - * Description: - * Clear DMA interrupt. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * mask - Interrupt mask to change - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_clear_interrupt(int chan, bool tx, uint32_t mask); - -/**************************************************************************** - * Name: esp_dma_get_desc_addr - * - * Description: - * Gets desc addr of DMA interrupt. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * Desc addr. - * - ****************************************************************************/ - -int esp_dma_get_desc_addr(int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_enable - * - * Description: - * Enable DMA channel transmission. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_enable(int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_disable - * - * Description: - * Disable DMA channel transmission. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_disable(int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_wait_idle - * - * Description: - * Wait until transmission ends. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_wait_idle(int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_reset_channel - * - * Description: - * Resets dma channel. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_reset_channel(int chan, bool tx); - -/**************************************************************************** - * Name: esp_dma_init - * - * Description: - * Initialize DMA driver. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_init(void); - -/**************************************************************************** - * Name: esp_dma_deinit - * - * Description: - * Deinitialize DMA driver. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_dma_deinit(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_DMA_H */ diff --git a/arch/risc-v/src/common/espressif/esp_gpio.c b/arch/risc-v/src/common/espressif/esp_gpio.c index b25fc70a220b6..58d585ec512c0 100644 --- a/arch/risc-v/src/common/espressif/esp_gpio.c +++ b/arch/risc-v/src/common/espressif/esp_gpio.c @@ -46,15 +46,21 @@ #include "riscv_internal.h" #include "esp_gpio.h" -#ifdef CONFIG_ESPRESSIF_GPIO_IRQ -# include "esp_irq.h" -#endif +#include "esp_irq.h" /* HAL */ +#include "esp_err.h" #include "soc/interrupts.h" #include "esp_rom_gpio.h" #include "hal/gpio_hal.h" +#include "driver/gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP_INTR_FLAG_DEFAULT 0 /**************************************************************************** * Private Data @@ -65,33 +71,25 @@ static gpio_hal_context_t g_gpio_hal = .dev = GPIO_HAL_GET_HW(GPIO_PORT_0) }; -#ifdef CONFIG_ESPRESSIF_GPIO_IRQ -static int g_gpio_cpuint; -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: gpio_isr_loop + * Name: esp_intr_handler_adapter * * Description: - * Processes all pending GPIO interrupts indicated by the given status - * bitmask. For each set bit in 'status', this function: - * 1. Calculates the GPIO pin number using 'gpio_num_start' as the base - * offset. - * 2. Clears the interrupt status bit for that GPIO pin using - * gpio_hal_clear_intr_status_bit(). - * 3. Dispatches the interrupt to the NuttX IRQ subsystem by calling - * irq_dispatch() with the correct IRQ number and register context. + * This function acts as an adapter to bridge interrupt service routines + * between NuttX and the Espressif's interrupt service routine. It is + * called when a GPIO interrupt occurs, retrieves the function pointer and + * associated data from the 'intr_adapter_from_nuttx' structure passed as + * an argument, and invokes the original user-provided interrupt handler + * with the IRQ number and user argument. * * Input Parameters: - * status - Bitmask indicating which GPIO pins have pending - * interrupts. - * gpio_num_start - The starting GPIO number (used as an offset). - * regs - Pointer to the register context to pass to - * irq_dispatch(). + * arg - Pointer to a structure of type 'intr_adapter_from_nuttx' that + * holds the handler function, the associated IRQ, the context, and + * the user argument. * * Returned Value: * None. @@ -99,70 +97,13 @@ static int g_gpio_cpuint; ****************************************************************************/ #ifdef CONFIG_ESPRESSIF_GPIO_IRQ -static void gpio_isr_loop(uint32_t status, - const uint32_t gpio_num_start, - uint32_t *regs) +static void esp_intr_handler_adapter(void *arg) { - int nbit; - int gpio_num; - - while (status != 0) - { - nbit = __builtin_ffs(status) - 1; - status &= ~(1 << nbit); - gpio_num = gpio_num_start + nbit; + struct intr_adapter_from_nuttx *adapter; - /* Dispatch pending interrupts in the lower GPIO status register */ + adapter = (struct intr_adapter_from_nuttx *)arg; - gpio_hal_clear_intr_status_bit(&g_gpio_hal, gpio_num); - - irq_dispatch(ESP_FIRST_GPIOIRQ + gpio_num, regs); - } -} -#endif - -/**************************************************************************** - * Name: gpio_interrupt - * - * Description: - * GPIO interrupt handler. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * context - Context data from the ISR. - * arg - Opaque pointer to the internal driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_GPIO_IRQ -static int gpio_interrupt(int irq, void *context, void *arg) -{ - int i; - uint32_t gpio_intr_status; - uint32_t gpio_intr_status_h; - int cpu = this_cpu(); - - /* Read the lower GPIO interrupt status */ - - gpio_hal_get_intr_status(&g_gpio_hal, cpu, &gpio_intr_status); - - if (gpio_intr_status) - { - gpio_isr_loop(gpio_intr_status, 0, (uint32_t *)context); - } - - gpio_hal_get_intr_status_high(&g_gpio_hal, cpu, &gpio_intr_status_h); - - if (gpio_intr_status_h) - { - gpio_isr_loop(gpio_intr_status_h, 32, (uint32_t *)context); - } - - return OK; + adapter->func(adapter->irq, adapter->context, adapter->arg); } #endif @@ -243,6 +184,9 @@ int esp_configgpio(int pin, gpio_pinattr_t attr) gpio_hal_pulldown_dis(&g_gpio_hal, pin); } + gpio_hal_set_intr_type(&g_gpio_hal, pin, + (attr & INTR_TYPE_MASK) >> INTR_TYPE_SHIFT); + if ((attr & DRIVE_MASK) != 0) { uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1; @@ -383,16 +327,7 @@ void esp_gpioirqinitialize(void) { /* Setup the GPIO interrupt. */ - g_gpio_cpuint = esp_setup_irq(GPIO_LL_INTR_SOURCE0, - ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); - VERIFY(g_gpio_cpuint); - - /* Attach and enable the interrupt handler */ - - VERIFY(irq_attach(ESP_SOURCE2IRQ(GPIO_LL_INTR_SOURCE0), gpio_interrupt, - NULL)); - up_enable_irq(ESP_SOURCE2IRQ(GPIO_LL_INTR_SOURCE0)); + gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT); } #endif @@ -400,44 +335,29 @@ void esp_gpioirqinitialize(void) * Name: esp_gpioirqenable * * Description: - * Enable the interrupt for specified GPIO IRQ + * Enable the interrupt for specified GPIO * * Input Parameters: - * irq - GPIO IRQ number to be enabled. - * intrtype - Interrupt type to be enabled. + * id - GPIO to be enabled. * * Returned Value: - * None. + * Zero (OK) on success, or -1 (ERROR) in case of failure. * ****************************************************************************/ #ifdef CONFIG_ESPRESSIF_GPIO_IRQ -void esp_gpioirqenable(int irq, gpio_intrtype_t intrtype) +int esp_gpioirqenable(int id) { - uintptr_t regaddr; - uint32_t regval; - int pin; - int cpu; - - DEBUGASSERT(irq >= ESP_FIRST_GPIOIRQ && irq <= ESP_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ - - up_disable_irq(ESP_SOURCE2IRQ(GPIO_LL_INTR_SOURCE0)); - - /* Enable interrupt for this pin on the current core */ - - cpu = this_cpu(); - gpio_hal_set_intr_type(&g_gpio_hal, pin, intrtype); - gpio_hal_intr_enable_on_core(&g_gpio_hal, pin, cpu); + esp_err_t esp_ret; - /* Configuration done. Re-enable the GPIO interrupt. */ + esp_ret = gpio_intr_enable(id); + if (esp_ret != ESP_OK) + { + gpioerr("gpio_intr_enable() failed: %d\n", esp_ret); + return -ERROR; + } - up_enable_irq(ESP_SOURCE2IRQ(GPIO_LL_INTR_SOURCE0)); + return OK; } #endif @@ -445,39 +365,92 @@ void esp_gpioirqenable(int irq, gpio_intrtype_t intrtype) * Name: esp_gpioirqdisable * * Description: - * Disable the interrupt for specified GPIO IRQ + * Disable the interrupt for specified GPIO * * Input Parameters: - * irq - GPIO IRQ number to be disabled. + * id - GPIO to be disabled. * * Returned Value: - * None. + * Zero (OK) on success, or -1 (ERROR) in case of failure. * ****************************************************************************/ #ifdef CONFIG_ESPRESSIF_GPIO_IRQ -void esp_gpioirqdisable(int irq) +int esp_gpioirqdisable(int id) { - uintptr_t regaddr; - uint32_t regval; - int pin; + esp_err_t esp_ret; - DEBUGASSERT(irq >= ESP_FIRST_GPIOIRQ && irq <= ESP_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ + esp_ret = gpio_intr_disable(id); + if (esp_ret != ESP_OK) + { + gpioerr("gpio_intr_disable() failed: %d\n", esp_ret); + return -ERROR; + } - up_disable_irq(ESP_SOURCE2IRQ(GPIO_LL_INTR_SOURCE0)); + return OK; +} +#endif - /* Disable the interrupt for this pin */ +/**************************************************************************** + * Name: esp_gpio_irq + * + * Description: + * Register or unregister a button interrupt handler for the specified + * button ID. Passing a non-NULL handler attaches and enables the ISR for + * the button; passing NULL disables the interrupt and removes any + * previously registered handler. + * + * Input Parameters: + * id - Identifies the button to be monitored. + * irqhandler - The handler to be called when the interrupt occurs. + * Set to NULL to disable the interrupt. + * arg - Pointer to the argument that will be provided to the + * interrupt handler. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ - gpio_hal_intr_disable(&g_gpio_hal, pin); +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret; + int irq = ESP_PIN2IRQ(id); - /* Configuration done. Re-enable the GPIO interrupt. */ + if (NULL != irqhandler) + { + esp_err_t esp_ret; + struct intr_adapter_from_nuttx *adapter; + + gpioinfo("Attach %p\n", irqhandler); + + adapter = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx)); + if (adapter == NULL) + { + gpioerr("kmm_calloc() failed\n"); + return -ERROR; + } + + adapter->func = irqhandler; + adapter->irq = irq; + adapter->context = NULL; + adapter->arg = arg; + + esp_ret = gpio_isr_handler_add(id, esp_intr_handler_adapter, + (void *)adapter); + if (esp_ret != ESP_OK) + { + gpioerr("gpio_isr_handler_add() failed: %d\n", ret); + return -ERROR; + } + } + else + { + gpioinfo("Disable the interrupt\n"); + gpio_isr_handler_remove(id); + } - up_enable_irq(ESP_SOURCE2IRQ(GPIO_LL_INTR_SOURCE0)); + return OK; } #endif diff --git a/arch/risc-v/src/common/espressif/esp_gpio.h b/arch/risc-v/src/common/espressif/esp_gpio.h index 85916bb0aca8a..0410628c9173b 100644 --- a/arch/risc-v/src/common/espressif/esp_gpio.h +++ b/arch/risc-v/src/common/espressif/esp_gpio.h @@ -28,6 +28,7 @@ ****************************************************************************/ #include +#include #include #include @@ -40,9 +41,9 @@ /* Encoded pin attributes used with esp_configgpio() * - * 11 10 9 8 7 6 5 4 3 2 1 0 - * -- -- -- -- -- -- -- -- -- -- -- -- - * DR DR DR FN FN FN OD PD PU F O I + * 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + * IT IT IT DR DR DR FN FN FN OD PD PU F O I */ #define MODE_SHIFT 0 @@ -62,9 +63,6 @@ # define FUNCTION_1 (1 << FUNCTION_SHIFT) # define FUNCTION_2 (2 << FUNCTION_SHIFT) # define FUNCTION_3 (3 << FUNCTION_SHIFT) -# define FUNCTION_4 (4 << FUNCTION_SHIFT) -# define FUNCTION_5 (5 << FUNCTION_SHIFT) -# define FUNCTION_6 (6 << FUNCTION_SHIFT) #define DRIVE_SHIFT 9 #define DRIVE_MASK (7 << DRIVE_SHIFT) @@ -73,6 +71,15 @@ # define DRIVE_2 (3 << DRIVE_SHIFT) # define DRIVE_3 (4 << DRIVE_SHIFT) +#define INTR_TYPE_SHIFT 12 +#define INTR_TYPE_MASK (7 << INTR_TYPE_SHIFT) +# define DISABLED (0 << INTR_TYPE_SHIFT) +# define RISING (1 << INTR_TYPE_SHIFT) +# define FALLING (2 << INTR_TYPE_SHIFT) +# define CHANGE (3 << INTR_TYPE_SHIFT) +# define ONLOW (4 << INTR_TYPE_SHIFT) +# define ONHIGH (5 << INTR_TYPE_SHIFT) + #define INPUT_PULLUP (INPUT | PULLUP) #define INPUT_PULLDOWN (INPUT | PULLDOWN) #define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) @@ -91,33 +98,6 @@ # define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) # define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) -/* Interrupt type used with esp_gpioirqenable() */ - -#define DISABLED 0x00 -#define RISING 0x01 -#define FALLING 0x02 -#define CHANGE 0x03 -#define ONLOW 0x04 -#define ONHIGH 0x05 - -/* Check whether it is a valid GPIO number */ - -#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & \ - SOC_GPIO_VALID_GPIO_MASK) != 0)) - -/* Check whether it can be a valid GPIO number of output mode */ - -#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) - -/* Check whether it can be a valid digital I/O pad */ - -#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) - /**************************************************************************** * Public Types ****************************************************************************/ @@ -275,41 +255,65 @@ void esp_gpioirqinitialize(void); * Name: esp_gpioirqenable * * Description: - * Enable the interrupt for specified GPIO IRQ + * Enable the interrupt for specified GPIO * * Input Parameters: - * irq - GPIO IRQ number to be enabled. - * intrtype - Interrupt type to be enabled. + * id - GPIO to be enabled. * * Returned Value: - * None. + * Zero (OK) on success, or -1 (ERROR) in case of failure. * ****************************************************************************/ #ifdef CONFIG_ESPRESSIF_GPIO_IRQ -void esp_gpioirqenable(int irq, gpio_intrtype_t intrtype); +int esp_gpioirqenable(int id); #else -# define esp_gpioirqenable(irq,intrtype) +# define esp_gpioirqenable(id) #endif /**************************************************************************** * Name: esp_gpioirqdisable * * Description: - * Disable the interrupt for specified GPIO IRQ + * Disable the interrupt for specified GPIO * * Input Parameters: - * irq - GPIO IRQ number to be disabled. + * id - GPIO to be disabled. * * Returned Value: - * None. + * Zero (OK) on success, or -1 (ERROR) in case of failure. * ****************************************************************************/ #ifdef CONFIG_ESPRESSIF_GPIO_IRQ -void esp_gpioirqdisable(int irq); +int esp_gpioirqdisable(int id); #else -# define esp_gpioirqdisable(irq) +# define esp_gpioirqdisable(id) +#endif + +/**************************************************************************** + * Name: esp_gpio_irq + * + * Description: + * Register or unregister a button interrupt handler for the specified + * button ID. Passing a non-NULL handler attaches and enables the ISR for + * the button; passing NULL disables the interrupt and removes any + * previously registered handler. + * + * Input Parameters: + * id - Identifies the button to be monitored. + * irqhandler - The handler to be called when the interrupt occurs. + * Set to NULL to disable the interrupt. + * arg - Pointer to the argument that will be provided to the + * interrupt handler. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg); #endif #ifdef __cplusplus diff --git a/arch/risc-v/src/common/espressif/esp_head.S b/arch/risc-v/src/common/espressif/esp_head.S index 65effe2a06f85..9b85bac5fffe1 100644 --- a/arch/risc-v/src/common/espressif/esp_head.S +++ b/arch/risc-v/src/common/espressif/esp_head.S @@ -48,6 +48,7 @@ ****************************************************************************/ __start: + .option push .option norelax @@ -63,16 +64,10 @@ __start: /* Disable all interrupts (i.e. timer, external) in mstatus */ - csrw CSR_MSTATUS, zero + csrc CSR_STATUS, STATUS_IE .option pop - /* Initialize the Machine Trap-Vector */ - - lui t0, %hi(_vector_table) - addi t0, t0, %lo(_vector_table) - csrw CSR_MTVEC, t0 - /* Jump to __esp_start */ jal x1, __esp_start diff --git a/arch/risc-v/src/common/espressif/esp_hr_timer.c b/arch/risc-v/src/common/espressif/esp_hr_timer.c index 9e9e2fe6af85b..2be1971cb64a5 100644 --- a/arch/risc-v/src/common/espressif/esp_hr_timer.c +++ b/arch/risc-v/src/common/espressif/esp_hr_timer.c @@ -100,6 +100,8 @@ static struct esp_hr_timer_context_s g_hr_timer_context = }; static bool g_hr_timer_initialized; +static uint8_t g_hr_timer_lock_count; +static irqstate_t g_hr_timer_lock_flags; /**************************************************************************** * Private Functions @@ -285,6 +287,7 @@ static int IRAM_ATTR esp_hr_timer_isr(int irq, void *context, void *arg) if (ret < 0) { tmrerr("Failed to post sem ret=%d\n", ret); + return ret; } } @@ -722,6 +725,95 @@ void IRAM_ATTR esp_hr_timer_calibration(uint64_t time_us) spin_unlock_irqrestore(&priv->lock, flags); } +/**************************************************************************** + * Name: esp_hr_timer_set + * + * Description: + * Set the High Resolution Timer counter value to a specific timestamp. + * + * Input Parameters: + * new_us - New counter value in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR esp_hr_timer_set(uint64_t new_us) +{ + struct esp_hr_timer_context_s *priv = &g_hr_timer_context; + + irqstate_t flags = spin_lock_irqsave(&priv->lock); + systimer_counter_value_t new_count = + { + .val = priv->hal.us_to_ticks(new_us), + }; + + systimer_ll_set_counter_value(priv->hal.dev, SYSTIMER_COUNTER_ESPTIMER, + new_count.val); + systimer_ll_apply_counter_value(priv->hal.dev, SYSTIMER_COUNTER_ESPTIMER); + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: esp_hr_timer_lock + * + * Description: + * Acquire the High Resolution Timer lock to protect access to hardware + * registers. Must be paired with esp_hr_timer_unlock(). + * This function supports recursive locking. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR esp_hr_timer_lock(void) +{ + struct esp_hr_timer_context_s *priv = &g_hr_timer_context; + irqstate_t flags; + + if (g_hr_timer_lock_count == 0) + { + flags = spin_lock_irqsave(&priv->lock); + + g_hr_timer_lock_flags = flags; + } + + g_hr_timer_lock_count++; +} + +/**************************************************************************** + * Name: esp_hr_timer_unlock + * + * Description: + * Release the High Resolution Timer lock. Must be paired with + * esp_hr_timer_lock(). + * This function supports recursive unlocking. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR esp_hr_timer_unlock(void) +{ + struct esp_hr_timer_context_s *priv = &g_hr_timer_context; + + g_hr_timer_lock_count--; + + if (g_hr_timer_lock_count == 0) + { + spin_unlock_irqrestore(&priv->lock, g_hr_timer_lock_flags); + } +} + /**************************************************************************** * Name: esp_hr_timer_init * @@ -813,12 +905,9 @@ int esp_hr_timer_init(void) esp_setup_irq(ETS_SYSTIMER_TARGET2_INTR_SOURCE, ESP_IRQ_PRIORITY_DEFAULT, - SYSTIMER_TRIGGER_TYPE); - - /* Attach the systimer interrupt */ - - irq_attach(ESP_SOURCE2IRQ(ETS_SYSTIMER_TARGET2_INTR_SOURCE), - (xcpt_t)esp_hr_timer_isr, NULL); + SYSTIMER_TRIGGER_TYPE, + esp_hr_timer_isr, + NULL); /* Enable the allocated CPU interrupt */ diff --git a/arch/risc-v/src/common/espressif/esp_hr_timer.h b/arch/risc-v/src/common/espressif/esp_hr_timer.h index 2842012710555..35dea08eb0e27 100644 --- a/arch/risc-v/src/common/espressif/esp_hr_timer.h +++ b/arch/risc-v/src/common/espressif/esp_hr_timer.h @@ -247,6 +247,56 @@ uint64_t esp_hr_timer_get_alarm(void); void esp_hr_timer_calibration(uint64_t time_us); +/**************************************************************************** + * Name: esp_hr_timer_set + * + * Description: + * Set the High Resolution Timer counter value to a specific timestamp. + * + * Input Parameters: + * new_us - New counter value in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_set(uint64_t new_us); + +/**************************************************************************** + * Name: esp_hr_timer_lock + * + * Description: + * Acquire the High Resolution Timer lock to protect access to hardware + * registers. Must be paired with esp_hr_timer_unlock(). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_lock(void); + +/**************************************************************************** + * Name: esp_hr_timer_unlock + * + * Description: + * Release the High Resolution Timer lock. Must be paired with + * esp_hr_timer_lock(). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_unlock(void); + /**************************************************************************** * Name: esp_hr_timer_init * diff --git a/arch/risc-v/src/common/espressif/esp_i2c.c b/arch/risc-v/src/common/espressif/esp_i2c.c index 1b4a4a7bee101..c37adb66c7d94 100644 --- a/arch/risc-v/src/common/espressif/esp_i2c.c +++ b/arch/risc-v/src/common/espressif/esp_i2c.c @@ -59,7 +59,7 @@ #include "hal/i2c_ll.h" #include "soc/system_reg.h" #include "soc/gpio_sig_map.h" -#include "soc/i2c_periph.h" +#include "hal/i2c_periph.h" #include "esp_clk_tree.h" #if defined(CONFIG_ARCH_CHIP_ESP32H2) || defined(CONFIG_ARCH_CHIP_ESP32C6) # include "soc/pcr_reg.h" @@ -228,8 +228,6 @@ struct esp_i2c_priv_s uint32_t id; /* I2C instance */ - periph_module_t module; /* Peripheral module */ - /* Port configuration */ struct esp_i2c_config_s *config; @@ -355,7 +353,6 @@ static struct esp_i2c_priv_s esp_i2c0_priv = { .ops = &esp_i2c_ops, .id = 0, - .module = PERIPH_I2C0_MODULE, .config = &esp_i2c0_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, @@ -397,7 +394,6 @@ static struct esp_i2c_priv_s esp_i2c1_priv = { .ops = &esp_i2c_ops, .id = 1, - .module = PERIPH_I2C1_MODULE, .config = &esp_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, @@ -442,7 +438,6 @@ static struct esp_i2c_priv_s esp_lp_i2c0_priv = { .ops = &esp_i2c_ops, .id = LP_I2C_NUM_0, - .module = PERIPH_LP_I2C0_MODULE, .config = &esp_lp_i2c0_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, @@ -1715,7 +1710,9 @@ struct i2c_master_s *esp_i2cbus_initialize(int port) priv->cpuint = esp_setup_irq(i2c_periph_signal[priv->id].irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_i2c_irq, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -1726,20 +1723,6 @@ struct i2c_master_s *esp_i2cbus_initialize(int port) return NULL; } - ret = irq_attach(ESP_SOURCE2IRQ(i2c_periph_signal[priv->id].irq), - esp_i2c_irq, priv); - if (ret != OK) - { - /* Failed to attach IRQ, free the allocated CPU interrupt */ - - esp_teardown_irq(i2c_periph_signal[priv->id].irq, priv->cpuint); - priv->cpuint = -ENOMEM; - priv->refs--; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the I2C device. */ up_enable_irq(ESP_SOURCE2IRQ(i2c_periph_signal[priv->id].irq)); diff --git a/arch/risc-v/src/common/espressif/esp_i2c_slave.c b/arch/risc-v/src/common/espressif/esp_i2c_slave.c index 602b10d7fa4ae..e26fca3fd00f9 100644 --- a/arch/risc-v/src/common/espressif/esp_i2c_slave.c +++ b/arch/risc-v/src/common/espressif/esp_i2c_slave.c @@ -61,7 +61,7 @@ #include "hal/i2c_ll.h" #include "soc/system_reg.h" #include "soc/gpio_sig_map.h" -#include "soc/i2c_periph.h" +#include "hal/i2c_periph.h" #if defined(CONFIG_ARCH_CHIP_ESP32H2) || defined(CONFIG_ARCH_CHIP_ESP32C6) # include "soc/pcr_reg.h" #endif @@ -616,7 +616,7 @@ static void esp_i2c_slave_deinit(struct esp_i2c_priv_s *priv) * ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int esp_i2c_slave_irq(int cpuint, void *context, void *arg) +static int esp_i2c_slave_irq(void *arg) { struct esp_i2c_priv_s *priv = (struct esp_i2c_priv_s *)arg; uint32_t irq_status = 0; @@ -873,7 +873,9 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr) priv->cpuint = esp_setup_irq(i2c_periph_signal[priv->id].irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_i2c_slave_irq, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -884,20 +886,6 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr) return NULL; } - ret = irq_attach(ESP_SOURCE2IRQ(i2c_periph_signal[priv->id].irq), - esp_i2c_slave_irq, priv); - if (ret != OK) - { - /* Failed to attach IRQ, free the allocated CPU interrupt */ - - esp_teardown_irq(i2c_periph_signal[priv->id].irq, priv->cpuint); - priv->cpuint = -ENOMEM; - priv->refs--; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the I2C device. */ up_enable_irq(ESP_SOURCE2IRQ(i2c_periph_signal[priv->id].irq)); diff --git a/arch/risc-v/src/common/espressif/esp_i2s.c b/arch/risc-v/src/common/espressif/esp_i2s.c index a8f8de08a178a..7ed37d04872f6 100644 --- a/arch/risc-v/src/common/espressif/esp_i2s.c +++ b/arch/risc-v/src/common/espressif/esp_i2s.c @@ -47,7 +47,7 @@ #include "hal/i2s_hal.h" #include "hal/i2s_ll.h" -#include "soc/i2s_periph.h" +#include "hal/i2s_periph.h" #include "soc/i2s_reg.h" #include "hal/i2s_types.h" #include "soc/gpio_sig_map.h" @@ -67,7 +67,7 @@ #include "hal/clk_tree_ll.h" #include "clk_ctrl_os.h" #endif -#include "soc/gdma_periph.h" +#include "hal/gdma_periph.h" #include "hal/gdma_ll.h" #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE @@ -169,18 +169,6 @@ cfg.sd_dither = 0, \ cfg.sd_dither2 = 1 \ -#if SOC_PERIPH_CLK_CTRL_SHARED -# define I2S_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() -#else -# define I2S_CLOCK_SRC_ATOMIC() -#endif - -#if !SOC_RCC_IS_INDEPENDENT -# define I2S_RCC_ATOMIC() PERIPH_RCC_ATOMIC() -#else -# define I2S_RCC_ATOMIC() -#endif - #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE # define I2S_DMA_BUFFER_MAX_SIZE DMA_DESCRIPTOR_BUFFER_MAX_SIZE_64B_ALIGNED #else @@ -1568,7 +1556,7 @@ static int i2s_configure(struct esp_i2s_s *priv) port = priv->config->port; i2s_hal_init(priv->config->ctx, port); - I2S_RCC_ATOMIC() + PERIPH_RCC_ATOMIC() { i2s_ll_enable_bus_clock(port, true); i2s_ll_reset_register(port); @@ -1625,7 +1613,7 @@ static int i2s_configure(struct esp_i2s_s *priv) if (priv->config->tx_en && !priv->config->rx_en) { #if SOC_I2S_HW_VERSION_2 - I2S_CLOCK_SRC_ATOMIC() + PERIPH_RCC_ATOMIC() { i2s_ll_mclk_bind_to_tx_clk(priv->config->ctx->dev); } @@ -1680,7 +1668,7 @@ static int i2s_configure(struct esp_i2s_s *priv) /* For "rx + master" mode, select RX signal index for ws and bck */ #if SOC_I2S_HW_VERSION_2 - I2S_CLOCK_SRC_ATOMIC() + PERIPH_RCC_ATOMIC() { i2s_ll_mclk_bind_to_rx_clk(priv->config->ctx->dev); } @@ -2007,6 +1995,13 @@ static uint32_t i2s_get_source_clk_freq(i2s_clock_src_t clk_src, } #endif +#ifdef I2S_LL_DEFAULT_CLK_SRC + if (clk_src == I2S_CLK_SRC_DEFAULT) + { + clk_src = I2S_LL_DEFAULT_CLK_SRC; + } +#endif + esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clk_freq); @@ -2195,7 +2190,7 @@ static int i2s_set_clock(struct esp_i2s_s *priv) priv->config->clk_info->mclk_div = mclk_div; priv->config->clk_info->sclk = sclk; - I2S_CLOCK_SRC_ATOMIC() + PERIPH_RCC_ATOMIC() { i2s_hal_set_tx_clock(priv->config->ctx, priv->config->clk_info, @@ -3255,26 +3250,26 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) esp_err_t err; gdma_trigger_t trig = { - .periph = GDMA_TRIG_PERIPH_I2S + 0 }; switch (priv->config->port) { #if SOC_I2S_NUM > 2 case I2S_NUM_2: - trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S2; + trig = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S, 2); break; #endif #if SOC_I2S_NUM > 1 case I2S_NUM_1: - trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S1; - break; + trig = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S, 1); + break; #endif case I2S_NUM_0: - trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S0; - break; + trig = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_I2S, 0); + break; default: i2serr("Unsupported I2S port number"); @@ -3291,11 +3286,10 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) { gdma_channel_alloc_config_t tx_handle = { - .direction = GDMA_CHANNEL_DIRECTION_TX, - .flags.reserve_sibling = 1, + 0 }; - err = gdma_new_ahb_channel(&tx_handle, &priv->dma_channel_tx); + err = gdma_new_ahb_channel(&tx_handle, &priv->dma_channel_tx, NULL); if (err != ESP_OK) { i2serr("Failed to register tx dma channel: %d\n", err); @@ -3334,11 +3328,10 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) { gdma_channel_alloc_config_t rx_handle = { - .direction = GDMA_CHANNEL_DIRECTION_RX, - .flags.reserve_sibling = 1, + 0 }; - err = gdma_new_ahb_channel(&rx_handle, &priv->dma_channel_rx); + err = gdma_new_ahb_channel(&rx_handle, NULL, &priv->dma_channel_rx); if (err != ESP_OK) { i2serr("Failed to register rx dma channel: %d\n", err); diff --git a/arch/risc-v/src/common/espressif/esp_irq.c b/arch/risc-v/src/common/espressif/esp_irq.c index e8d47096265a6..22827abb50cf1 100644 --- a/arch/risc-v/src/common/espressif/esp_irq.c +++ b/arch/risc-v/src/common/espressif/esp_irq.c @@ -35,6 +35,8 @@ #include #include +#include "irq/irq.h" + #include "riscv_internal.h" #include "esp_gpio.h" @@ -48,276 +50,219 @@ #include "riscv/interrupt.h" #include "soc/soc.h" +#if SOC_INT_CLIC_SUPPORTED +# include "hal/interrupt_clic_ll.h" +# include "esp_private/interrupt_clic.h" +#endif // SOC_INT_CLIC_SUPPORTED + +#include "esp_private/vectors_const.h" + +#ifndef CONFIG_ARCH_CHIP_ESP32C3 +# include "soc/hp_system_reg.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define ESP_DEFAULT_INT_THRESHOLD 1 - -#define IRQ_UNMAPPED 0xff - -/* Helper macros for working with cpuint_mapentry_t fields */ - -#define CPUINT_DISABLE(cpuint) ((cpuint).cpuint_en = 0) -#define CPUINT_ENABLE(cpuint) ((cpuint).cpuint_en = 1) -#define CPUINT_ASSIGN(cpuint,in_irq) do \ - { \ - (cpuint).assigned = 1; \ - (cpuint).cpuint_en = 1; \ - (cpuint).irq = (in_irq); \ - } \ - while(0) -#define CPUINT_GETIRQ(cpuint) ((cpuint).irq) -#define CPUINT_FREE(cpuint) ((cpuint).val = 0) -#define CPUINT_ISENABLED(cpuint) ((cpuint).cpuint_en == 1) -#define CPUINT_ISASSIGNED(cpuint) ((cpuint).assigned == 1) -#define CPUINT_ISRESERVED(cpuint) ((cpuint).reserved0 == 1) -#define CPUINT_ISFREE(cpuint) (!CPUINT_ISASSIGNED(cpuint)) - -/* CPU interrupts can be detached from any interrupt source by setting the - * map register to ETS_INVALID_INUM, which is an invalid CPU interrupt index. - */ - -#define NO_CPUINT ETS_INVALID_INUM - -/* Masks for interrupt type used on esp_setup_irq */ +#ifdef CONFIG_SMP_NCPUS +# define ESP_NCPUS CONFIG_SMP_NCPUS +#else +# define ESP_NCPUS 1 +#endif -#define ESP_CPUINT_IRAM_MASK (1 << 1) -#define ESP_CPUINT_TRIGGER_MASK (1 << 0) +#ifdef CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC +# ifndef CONFIG_ARCH_IRQ_TO_NDX +# error "CONFIG_ARCH_IRQ_TO_NDX must be enabled for RISC-V-based \ + Espressif SoCs. Run 'make menuconfig' to select it." +# endif +# if CONFIG_ARCH_NUSER_INTERRUPTS != 17 +# error "CONFIG_ARCH_NUSER_INTERRUPTS must be 17 for RISC-V-based \ + Espressif SoCs. Run 'make menuconfig' to set it." +# endif +#else +# error "CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC must be enabled for \ + RISC-V-based Espressif SoCs. Additionally, enable \ + CONFIG_ARCH_IRQ_TO_NDX and set CONFIG_ARCH_NUSER_INTERRUPTS to 17.\ + Run 'make menuconfig' to select and set these options." +#endif /**************************************************************************** - * Private Types + * Private Function Prototypes ****************************************************************************/ -/* CPU interrupts to IRQ index mapping */ - -typedef union cpuint_mapentry_u -{ - struct - { - uint16_t assigned:1; - uint16_t cpuint_en:1; - uint16_t irq:10; - uint16_t reserved0:4; - }; - - uint16_t val; -} cpuint_mapentry_t; +static void esp_clear_handle(int cpu, int irq); /**************************************************************************** * Private Data ****************************************************************************/ -/* Map a CPU interrupt to the IRQ of the attached interrupt source */ +/* Map an IRQ to a handle to which the interrupt source is attached to. */ -static cpuint_mapentry_t g_cpuint_map[ESP_NCPUINTS]; - -/* Map an IRQ to a CPU interrupt to which the interrupt source is - * attached to. - */ - -static volatile uint8_t g_irq_map[NR_IRQS]; - -/* Bitsets for free, unallocated CPU interrupts available to peripheral - * devices. - */ - -static uint32_t g_cpuint_freelist = ESP_CPUINT_PERIPHSET; - -/* This bitmask has an 1 if the int should be disabled - * when the flash is disabled. - */ - -static uint32_t non_iram_int_mask[CONFIG_ESPRESSIF_NUM_CPUS]; - -/* This bitmask has 1 in it if the int was disabled - * using esp_intr_noniram_disable. - */ - -static uint32_t non_iram_int_disabled[CONFIG_ESPRESSIF_NUM_CPUS]; -static bool non_iram_int_disabled_flag[CONFIG_ESPRESSIF_NUM_CPUS]; +static volatile intr_handle_t g_handle_map[CONFIG_SMP_NCPUS][NR_IRQS]; #ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG /* The g_iram_count keeps track of how many times such an IRQ ran when the * non-IRAM interrupts were disabled. */ -static uint64_t g_iram_count[NR_IRQS]; +static uint64_t g_iram_count[CONFIG_SMP_NCPUS][NR_IRQS]; #endif +/**************************************************************************** + * Public Data + ****************************************************************************/ + /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: esp_cpuint_alloc + * Name: esp_cpuint_initialize * * Description: - * Allocate a free CPU interrupt for a peripheral device. This function - * will not ignore all of the pre-allocated CPU interrupts for internal - * devices. + * Initialize CPU interrupts. * * Input Parameters: - * irq - IRQ number. + * None. * * Returned Value: - * On success, a CPU interrupt number is returned. - * A negated errno is returned on failure. + * None. * ****************************************************************************/ -static int esp_cpuint_alloc(int irq) +static void esp_cpuint_initialize(void) { - uint32_t bitmask; - uint32_t intset; - int cpuint = ESP_NCPUINTS; - - /* Check if there are CPU interrupts with the requested properties - * available. - */ - - intset = g_cpuint_freelist; - if (intset != 0) - { - /* Skip over initial unavailable CPU interrupts quickly in groups - * of 8 interrupt. - */ - - for (cpuint = 0, bitmask = 0xff; - cpuint < ESP_NCPUINTS && (intset & bitmask) == 0; - cpuint += 8, bitmask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining - * intset. - */ - - for (; cpuint < ESP_NCPUINTS; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - bitmask = BIT(cpuint); - if ((intset & bitmask) != 0) - { - /* Got it! */ - - g_cpuint_freelist &= ~bitmask; - break; - } - } - } - - if (cpuint == ESP_NCPUINTS) - { - /* No unallocated CPU interrupt found */ - - return -ENOMEM; - } - - DEBUGASSERT(CPUINT_ISFREE(g_cpuint_map[cpuint])); - - esp_set_irq(irq, cpuint); + /* Set CPU interrupt threshold level */ - return cpuint; + esprv_int_set_threshold(RVHAL_INTR_ENABLE_THRESH); + rv_utils_intr_global_enable(); } +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG + /**************************************************************************** - * Name: esp_cpuint_free + * Name: esp_iram_interrupt_record * * Description: - * Free a previously allocated CPU interrupt. + * This function keeps track of the IRQs that ran when non-IRAM interrupts + * are disabled and enables debugging of the IRAM-enabled interrupts. * * Input Parameters: - * cpuint - CPU interrupt to be freed. + * irq - The IRQ associated with a CPU interrupt + * cpu - The CPU associated with the CPU interrupt * * Returned Value: * None. * ****************************************************************************/ -static void esp_cpuint_free(int cpuint) +IRAM_ATTR static void esp_irq_iram_interrupt_record(int irq, int cpu) { - uint32_t bitmask; - - DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS); - DEBUGASSERT(CPUINT_ISASSIGNED(g_cpuint_map[cpuint])); + irqstate_t flags = enter_critical_section(); - int irq = CPUINT_GETIRQ(g_cpuint_map[cpuint]); - g_irq_map[irq] = IRQ_UNMAPPED; - CPUINT_FREE(g_cpuint_map[cpuint]); + g_iram_count[cpu][irq]++; - /* Mark the CPU interrupt as available */ + leave_critical_section(flags); +} +#endif - bitmask = BIT(cpuint); +IRAM_ATTR static void isr_adapter_func(void *arg) +{ + struct intr_adapter_from_nuttx *isr_adapter_args; - DEBUGASSERT((g_cpuint_freelist & bitmask) == 0); + isr_adapter_args = (struct intr_adapter_from_nuttx *)arg; - g_cpuint_freelist |= bitmask; + isr_adapter_args->func(isr_adapter_args->irq, + isr_adapter_args->context, + isr_adapter_args->arg); } /**************************************************************************** - * Name: esp_cpuint_initialize + * Name: esp_isr_demultiplexing * * Description: - * Initialize CPU interrupts. + * Demultiplexing interrupt handler. All peripheral interrupts are + * dispatched through this single handler, which then calls the + * appropriate peripheral handler registered via esp_setup_irq. * * Input Parameters: - * None. + * irq - The IRQ number (XTENSA_IRQ_DEMUX) + * context - Saved processor state + * arg - Unused * * Returned Value: - * None. + * Always returns OK. * ****************************************************************************/ -static void esp_cpuint_initialize(void) +IRAM_ATTR static int esp_isr_demultiplexing(int irq, void *context, + void *arg) { - /* Unmap CPU interrupts from every interrupt source */ + int cpuint = esp_get_cpuint(this_cpu(), irq); + intr_handler_t handler; + struct intr_adapter_from_nuttx *handler_arg; + + /* Validate cpuint - if invalid, the interrupt was not properly + * registered via esp_setup_irq. This is a bug that needs to be fixed. + */ - for (int source = 0; source < ESP_NSOURCES; source++) + if (cpuint < 0 || cpuint >= SOC_CPU_INTR_NUM) { - esp_rom_route_intr_matrix(PRO_CPU_NUM, source, NO_CPUINT); + irqwarn("IRQ %d has invalid cpuint=%d (not registered)", irq, cpuint); + return OK; } - /* Set CPU interrupt threshold level */ + handler = (intr_handler_t)esp_cpu_intr_get_handler(cpuint); + handler_arg = (struct intr_adapter_from_nuttx *) + esp_cpu_intr_get_handler_arg(cpuint); - esprv_int_set_threshold(ESP_DEFAULT_INT_THRESHOLD); + /* If the handler is the isr_adapter_func, then we need to set the irq + * and context to the handler_arg. This is true for all interrupts set via + * esp_setup_irq. Exceptions are the interrupts set directly by the + * underlying hardware, like Wi-Fi. + */ - /* Indicate that no interrupt sources are assigned to CPU interrupts */ + if (handler == &isr_adapter_func) + { + handler_arg->irq = irq; + handler_arg->context = context; + } - memset(g_cpuint_map, 0, sizeof(g_cpuint_map)); + if (handler) + { + (*handler)(handler_arg); + } + else + { + /* Handler not found in _xt_interrupt_table. + * This happens when irq_attach was used instead of esp_setup_irq + * with a non-NULL handler. Peripheral handlers must be set via + * esp_setup_irq() when using ARCH_MINIMAL_VECTORTABLE. + */ + + irqwarn("No handler for irq=%d cpuint=%d\n", irq, cpuint); + } + + return OK; } -#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG +/**************************************************************************** + * Public Functions + ****************************************************************************/ /**************************************************************************** - * Name: esp_iram_interrupt_record + * Name: up_irq_to_ndx * * Description: - * This function keeps track of the IRQs that ran when non-IRAM interrupts - * are disabled and enables debugging of the IRAM-enabled interrupts. - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * - * Returned Value: - * None. + * Irq to ndx * ****************************************************************************/ -IRAM_ATTR void esp_irq_iram_interrupt_record(int irq) +int IRAM_ATTR up_irq_to_ndx(int irq) { - irqstate_t flags = enter_critical_section(); - - g_iram_count[irq]++; - - leave_critical_section(flags); + return irq < ESP_IRQ_FIRSTPERIPH ? irq : ESP_IRQ_DEMUX; } -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ /**************************************************************************** * Name: up_irqinitialize @@ -336,20 +281,17 @@ IRAM_ATTR void esp_irq_iram_interrupt_record(int irq) void up_irqinitialize(void) { - /* All CPU ints are non-IRAM interrupts at the beginning and should be - * disabled during a SPI flash operation - */ - - for (int i = 0; i < CONFIG_SMP_NCPUS; i++) - { - non_iram_int_mask[i] = UINT32_MAX; - } + int i; + int j; /* Indicate that no interrupt sources are assigned to CPU interrupts */ - for (int i = 0; i < NR_IRQS; i++) + for (i = 0; i < NR_IRQS; i++) { - g_irq_map[i] = IRQ_UNMAPPED; + for (j = 0; j < CONFIG_SMP_NCPUS; j++) + { + g_handle_map[j][i] = IRQ_UNMAPPED; + } } /* Initialize CPU interrupts */ @@ -372,6 +314,8 @@ void up_irqinitialize(void) #ifndef CONFIG_SUPPRESS_INTERRUPTS + irq_attach(ESP_IRQ_DEMUX, esp_isr_demultiplexing, NULL); + /* And finally, enable interrupts */ riscv_color_intstack(); @@ -395,20 +339,20 @@ void up_irqinitialize(void) void up_enable_irq(int irq) { - int cpuint = g_irq_map[irq]; - - irqinfo("irq=%d | cpuint=%d \n", irq, cpuint); - - /* Check if IRQ is initialized */ - - DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS); - - irqstate_t irqstate = enter_critical_section(); + esp_err_t ret; + intr_handle_t intr_handle = esp_get_handle(this_cpu(), irq); - CPUINT_ENABLE(g_cpuint_map[cpuint]); - esprv_int_enable(BIT(cpuint)); + if (intr_handle == IRQ_UNMAPPED) + { + irqwarn("IRQ %d not mapped to handle\n", irq); + return; + } - leave_critical_section(irqstate); + ret = esp_intr_enable(intr_handle); + if (ret != ESP_OK) + { + irqerr("Failed to enable interrupt %d\n", irq); + } } /**************************************************************************** @@ -427,66 +371,14 @@ void up_enable_irq(int irq) void up_disable_irq(int irq) { - int cpuint = g_irq_map[irq]; - - irqinfo("irq=%d | cpuint=%d \n", irq, cpuint); - - /* Check if IRQ is initialized */ - - DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS); - - irqstate_t irqstate = enter_critical_section(); - - CPUINT_DISABLE(g_cpuint_map[cpuint]); - esprv_int_disable(BIT(cpuint)); - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp_route_intr - * - * Description: - * Assign an interrupt source to a pre-allocated CPU interrupt. - * - * Input Parameters: - * source - Interrupt source (see irq.h) to be assigned to a CPU - * interrupt. - * cpuint - Pre-allocated CPU interrupt to which the interrupt - * source will be assigned. - * priority - Interrupt priority. - * type - Interrupt trigger type. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_route_intr(int source, int cpuint, irq_priority_t priority, - irq_trigger_t type) -{ - /* Ensure the CPU interrupt is disabled */ - - esprv_int_disable(BIT(cpuint)); - - /* Set the interrupt priority */ - - esprv_int_set_priority(cpuint, priority); - - /* Set the interrupt trigger type (Edge or Level) */ + esp_err_t ret; + intr_handle_t intr_handle = esp_get_handle(this_cpu(), irq); - if (type == ESP_IRQ_TRIGGER_EDGE) + ret = esp_intr_disable(intr_handle); + if (ret != ESP_OK) { - esprv_int_set_type(cpuint, INTR_TYPE_EDGE); + irqerr("Failed to disable interrupt %d\n", irq); } - else - { - esprv_int_set_type(cpuint, INTR_TYPE_LEVEL); - } - - /* Route the interrupt source to the provided CPU interrupt */ - - esp_rom_route_intr_matrix(PRO_CPU_NUM, source, cpuint); } /**************************************************************************** @@ -503,51 +395,106 @@ void esp_route_intr(int source, int cpuint, irq_priority_t priority, * type - Interrupt trigger type. * * Returned Value: - * Allocated CPU interrupt. + * Allocated CPU interrupt or a negated errno value on failure. * ****************************************************************************/ -int esp_setup_irq(int source, irq_priority_t priority, int type) +int esp_setup_irq(int source, + irq_priority_t priority, + int type, + xcpt_t handler, + void *arg) { - irqstate_t irqstate; - int irq; - int cpuint; + return esp_setup_irq_intrstatus(source, priority, type, 0, 0, + handler, arg); +} - irqinfo("source = %d\n", source); +int esp_setup_irq_with_flags(int source, + int flags, + xcpt_t handler, + void *arg) +{ + return esp_setup_irq_with_flags_intrstatus(source, flags, 0, 0, + handler, arg); +} - DEBUGASSERT(source >= 0 && source < ESP_NSOURCES); +int esp_setup_irq_intrstatus(int source, + irq_priority_t priority, + int type, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg) +{ + int flags; + + flags = (1 << priority); + flags |= type == ESP_IRQ_TRIGGER_EDGE ? ESP_INTR_FLAG_EDGE : 0; + flags |= ESP_INTR_FLAG_INTRDISABLED; + + return esp_setup_irq_with_flags_intrstatus(source, + flags, + intrstatusreg, + intrstatusmask, + handler, + arg); +} - irqstate = enter_critical_section(); +int esp_setup_irq_with_flags_intrstatus(int source, + int flags, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg) +{ + struct intr_adapter_from_nuttx *isr_adapter_args; + esp_err_t ret; + intr_handle_t ret_handle; + int cpuint; + int irq; - /* Setting up an IRQ includes the following steps: - * 1. Allocate a CPU interrupt. - * 2. Map the CPU interrupt to the IRQ to ease searching later. - * 3. Attach the interrupt source to the newly allocated CPU interrupt. - */ + irqinfo("source = %d\n", source); - irq = ESP_SOURCE2IRQ(source); - cpuint = esp_cpuint_alloc(irq); - if (cpuint < 0) + isr_adapter_args = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx)); + if (isr_adapter_args == NULL) { - _alert("Unable to allocate CPU interrupt for source=%d\n", - source); + irqerr("Failed to kmm_calloc\n"); + return -EINVAL; + } - PANIC(); + isr_adapter_args->func = handler; + isr_adapter_args->arg = arg; + + ret = esp_intr_alloc_intrstatus(source, + flags, + intrstatusreg, + intrstatusmask, + isr_adapter_func, + isr_adapter_args, + &ret_handle); + if (ret != ESP_OK) + { + irqerr("Failed to allocate interrupt for source %d\n", source); + kmm_free(isr_adapter_args); + return -EINVAL; } - esp_route_intr(source, cpuint, priority, (type & ESP_CPUINT_TRIGGER_MASK)); + cpuint = esp_intr_get_intno(ret_handle); - if ((type & ESP_CPUINT_IRAM_MASK) == ESP_IRQ_IRAM) + if (source < 0) { - esp_irq_set_iram_isr(irq); - irqinfo("source %d marked IRAM (irq=%d)\n", source, irq); + irq = source + ETS_INTERNAL_INTR_SOURCE_OFF; } else { - esp_irq_unset_iram_isr(irq); + irq = ESP_SOURCE2IRQ(source); } - leave_critical_section(irqstate); + /* Store the handle. The handle already contains the CPU interrupt and + * CPU information, so no additional mapping is needed. + */ + + esp_set_handle(this_cpu(), irq, ret_handle); return cpuint; } @@ -573,21 +520,26 @@ int esp_setup_irq(int source, irq_priority_t priority, int type) void esp_teardown_irq(int source, int cpuint) { - irqstate_t irqstate = enter_critical_section(); - - /* Tearing down an IRQ includes the following steps: - * 1. Free the previously allocated CPU interrupt. - * 2. Unmap the IRQ from the IRQ-to-cpuint map. - * 3. Detach the interrupt source from the CPU interrupt. - */ + esp_err_t ret; + int cpu = this_cpu(); + int irq = ESP_SOURCE2IRQ(source); + intr_handle_t intr_handle = esp_get_handle(cpu, irq); - esp_cpuint_free(cpuint); + UNUSED(cpuint); - DEBUGASSERT(source >= 0 && source < ESP_NSOURCES); + if (intr_handle == IRQ_UNMAPPED) + { + irqwarn("No handle found for source %d\n", source); + return; + } - esp_rom_route_intr_matrix(PRO_CPU_NUM, source, NO_CPUINT); + ret = esp_intr_free(intr_handle); + if (ret != ESP_OK) + { + irqerr("Failed to free interrupt %d\n", source); + } - leave_critical_section(irqstate); + esp_clear_handle(cpu, irq); } /**************************************************************************** @@ -610,26 +562,35 @@ IRAM_ATTR void *riscv_dispatch_irq(uintreg_t mcause, uintreg_t *regs) int irq; bool is_irq = (RISCV_IRQ_BIT & mcause) != 0; bool is_edge = false; - uint32_t cpu = esp_cpu_get_core_id(); + int cpu = this_cpu(); if (is_irq) { - uint8_t cpuint = mcause & RISCV_IRQ_MASK; + uint8_t cpuint = (mcause & VECTORS_MCAUSE_REASON_MASK) - + RV_EXTERNAL_INT_OFFSET; DEBUGASSERT(cpuint >= 0 && cpuint < ESP_NCPUINTS); - DEBUGASSERT(CPUINT_ISENABLED(g_cpuint_map[cpuint])); - DEBUGASSERT(CPUINT_ISASSIGNED(g_cpuint_map[cpuint])); - irq = g_cpuint_map[cpuint].irq; + irq = esp_cpuint_to_irq(cpuint, cpu); + + if (irq < 0) + { + /* No handle found for this CPU interrupt. This can happen + * if the interrupt was triggered but not properly registered. + */ + + irqwarn("No IRQ found for cpuint=%d cpu=%d\n", cpuint, cpu); + return regs; + } #ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG /* Check if non-IRAM interrupts are disabled */ - if (esp_irq_noniram_status(cpu) == 0) + if (esp_intr_noniram_is_disabled(cpu)) { /* Sum-up the IRAM-enabled counter associated with the IRQ */ - esp_irq_iram_interrupt_record(irq); + esp_irq_iram_interrupt_record(irq, this_cpu()); } #endif @@ -645,7 +606,8 @@ IRAM_ATTR void *riscv_dispatch_irq(uintreg_t mcause, uintreg_t *regs) { /* It's exception */ - irq = mcause; + irq = mcause & + (VECTORS_MCAUSE_INTBIT_MASK | VECTORS_MCAUSE_REASON_MASK); } regs = riscv_doirq(irq, regs); @@ -678,228 +640,168 @@ irqstate_t up_irq_enable(void) } /**************************************************************************** - * Name: esp_intr_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_intr_noniram_disable(void) -{ - uint32_t oldint; - irqstate_t irqstate; - uint32_t cpu; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - cpu = esp_cpu_get_core_id(); - non_iram_ints = non_iram_int_mask[cpu]; - - if (non_iram_int_disabled_flag[cpu]) - { - abort(); - } - - non_iram_int_disabled_flag[cpu] = true; - oldint = esp_cpu_intr_get_enabled_mask(); - esp_cpu_intr_disable(non_iram_ints); - - /* Save disabled ints */ - - non_iram_int_disabled[cpu] = oldint & non_iram_ints; - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp_intr_noniram_enable + * Name: esp_set_handle * * Description: - * Enable interrupts that aren't specifically marked as running from IRAM. + * This function sets the handle associated with an IRQ * * Input Parameters: - * None. + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * handle - The handle to be associated with the IRQ * * Returned Value: - * None. + * OK on success; A negated errno value on failure. * ****************************************************************************/ -void esp_intr_noniram_enable(void) +int esp_set_handle(int cpu, int irq, intr_handle_t handle) { - irqstate_t irqstate; - uint32_t cpu; - int non_iram_ints; - - irqstate = enter_critical_section(); - cpu = esp_cpu_get_core_id(); - non_iram_ints = non_iram_int_disabled[cpu]; + intr_handle_t current_handle = g_handle_map[cpu][irq]; - if (!non_iram_int_disabled_flag[cpu]) + if (current_handle != IRQ_UNMAPPED) { - abort(); + irqinfo("IRQ %d already has a handle\n", irq); + return -EINVAL; } - non_iram_int_disabled_flag[cpu] = false; - esp_cpu_intr_enable(non_iram_ints); - leave_critical_section(irqstate); -} + g_handle_map[cpu][irq] = handle; -/**************************************************************************** - * Name: esp_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core - * - * Input Parameters: - * cpu - The CPU to check the non-IRAM interrupts state - * - * Returned Value: - * true if non-IRAM interrupts are enabled, false otherwise. - * - ****************************************************************************/ - -bool esp_irq_noniram_status(int cpu) -{ - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - return !non_iram_int_disabled_flag[cpu]; + return OK; } /**************************************************************************** - * Name: esp_get_irq + * Name: esp_get_handle * * Description: - * This function returns the IRQ associated with a CPU interrupt + * This function gets the handle associated with an IRQ * * Input Parameters: - * cpuint - The CPU interrupt associated to the IRQ + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt * * Returned Value: - * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if - * IRQ is not yet assigned to a CPU interrupt. + * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is + * associated with the IRQ. * ****************************************************************************/ -int esp_get_irq(int cpuint) +intr_handle_t esp_get_handle(int cpu, int irq) { - return CPUINT_GETIRQ(g_cpuint_map[cpuint]); + return g_handle_map[cpu][irq]; } /**************************************************************************** - * Name: esp_set_irq + * Name: esp_clear_handle * * Description: - * This function assigns a CPU interrupt to a specific IRQ number. It - * updates the mapping between IRQ numbers and CPU interrupts, allowing - * the system to correctly route hardware interrupts to the appropriate - * handlers. Please note that this function is intended to be used only - * when a CPU interrupt is already assigned to an IRQ number. Otherwise, - * please check esp_setup_irq. + * This function clears the handle associated with an IRQ * * Input Parameters: - * irq - The IRQ number to be associated with the CPU interrupt. - * cpuint - The CPU interrupt to be associated with the IRQ number. + * irq - The IRQ associated with a CPU interrupt * * Returned Value: - * None + * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is + * associated with the IRQ. * ****************************************************************************/ -void esp_set_irq(int irq, int cpuint) +static void esp_clear_handle(int cpu, int irq) { - CPUINT_ASSIGN(g_cpuint_map[cpuint], irq); - g_irq_map[irq] = cpuint; + g_handle_map[cpu][irq] = IRQ_UNMAPPED; } /**************************************************************************** - * Name: esp_irq_set_iram_isr + * Name: esp_get_cpuint * * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. + * This function returns the CPU interrupt associated with an IRQ * * Input Parameters: - * irq - The associated IRQ to set + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt * * Returned Value: - * OK on success; A negated errno value on failure. + * The CPU interrupt associated with such IRQ or a negated errno value on + * failure. * ****************************************************************************/ -int esp_irq_set_iram_isr(int irq) +IRAM_ATTR int esp_get_cpuint(int cpu, int irq) { - uint32_t cpu = esp_cpu_get_core_id(); - int cpuint = g_irq_map[irq]; + intr_handle_t intr_handle = esp_get_handle(cpu, irq); - if (cpuint == IRQ_UNMAPPED) + if (intr_handle != IRQ_UNMAPPED && intr_handle != NULL) { - return -EINVAL; + return esp_intr_get_intno(intr_handle); } - non_iram_int_mask[cpu] &= ~(1 << cpuint); - - return OK; + return -EINVAL; } /**************************************************************************** - * Name: esp_irq_unset_iram_isr + * Name: esp_get_iram_interrupt_records * * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. + * This function copies the vector that keeps track of the IRQs that ran + * when non-IRAM interrupts were disabled. * * Input Parameters: - * irq - The associated IRQ to set + * + * irq_count - A previously allocated pointer to store the counter of the + * interrupts that ran when non-IRAM interrupts were disabled. + * cpu - The CPU to retrieve the interrupt records for * * Returned Value: - * OK on success; A negated errno value on failure. + * None * ****************************************************************************/ -int esp_irq_unset_iram_isr(int irq) +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG +void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu) { - uint32_t cpu = esp_cpu_get_core_id(); - int cpuint = g_irq_map[irq]; - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } + irqstate_t flags = enter_critical_section(); - non_iram_int_mask[cpu] |= (1 << cpuint); + memcpy(irq_count, &g_iram_count[cpu], sizeof(uint64_t) * NR_IRQS); - return OK; + leave_critical_section(flags); } +#endif /**************************************************************************** - * Name: esp_get_iram_interrupt_records + * Name: esp_cpuint_to_irq * * Description: - * This function copies the vector that keeps track of the IRQs that ran - * when non-IRAM interrupts were disabled. + * Find an IRQ associated with a given CPU interrupt by searching through + * g_handle_map. For shared interrupts, multiple IRQs may map to the same + * CPU interrupt - this function returns the first one found. * * Input Parameters: - * - * irq_count - A previously allocated pointer to store the counter of the - * interrupts that ran when non-IRAM interrupts were disabled. + * cpuint - The CPU interrupt number + * cpu - The CPU core * * Returned Value: - * None + * The IRQ number, or -1 if not found. * ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG -void esp_get_iram_interrupt_records(uint64_t *irq_count) +IRAM_ATTR int esp_cpuint_to_irq(int cpuint, int cpu) { - irqstate_t flags = enter_critical_section(); + int irq; + intr_handle_t handle; - memcpy(irq_count, &g_iram_count, sizeof(uint64_t) * NR_IRQS); + for (irq = 0; irq < NR_IRQS; irq++) + { + handle = g_handle_map[cpu][irq]; + if (handle != IRQ_UNMAPPED && handle != NULL) + { + if (esp_intr_get_intno(handle) == cpuint && + esp_intr_get_cpu(handle) == cpu) + { + return irq; + } + } + } - leave_critical_section(flags); + return -1; } -#endif diff --git a/arch/risc-v/src/common/espressif/esp_irq.h b/arch/risc-v/src/common/espressif/esp_irq.h index f2b72ad930ad9..36b54d933ca9b 100644 --- a/arch/risc-v/src/common/espressif/esp_irq.h +++ b/arch/risc-v/src/common/espressif/esp_irq.h @@ -32,10 +32,14 @@ #include #include +#include "esp_intr_types.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +#define IRQ_UNMAPPED (intr_handle_t)NULL + #ifndef __ASSEMBLY__ #undef EXTERN @@ -94,32 +98,26 @@ typedef enum irq_priority_e ESP_IRQ_PRIORITY_DEFAULT = ESP_IRQ_PRIORITY_1 /* Default Priority */ } irq_priority_t; -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ +/* Adapter from NuttX to Espressif's interrupt handler */ + +struct intr_adapter_from_nuttx +{ + int (*func)(int irq, void *context, void *arg); /* Interrupt callback function */ + int irq; /* Interrupt number */ + void *context; /* Interrupt context */ + void *arg; /* Interrupt private data */ +}; + +struct intr_adapter_to_nuttx +{ + void (*handler)(void *arg); /* Interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; /**************************************************************************** - * Name: esp_route_intr - * - * Description: - * Assign an interrupt source to a pre-allocated CPU interrupt. - * - * Input Parameters: - * source - Interrupt source (see irq.h) to be assigned to a CPU - * interrupt. - * cpuint - Pre-allocated CPU interrupt to which the interrupt - * source will be assigned. - * priority - Interrupt priority. - * type - Interrupt trigger type. - * - * Returned Value: - * None. - * + * Public Functions Prototypes ****************************************************************************/ -void esp_route_intr(int source, int cpuint, irq_priority_t priority, - irq_trigger_t type); - /**************************************************************************** * Name: esp_setup_irq * @@ -138,7 +136,31 @@ void esp_route_intr(int source, int cpuint, irq_priority_t priority, * ****************************************************************************/ -int esp_setup_irq(int source, irq_priority_t priority, int type); +int esp_setup_irq(int source, + irq_priority_t priority, + int type, + xcpt_t handler, + void *arg); + +int esp_setup_irq_with_flags(int source, + int flags, + xcpt_t handler, + void *arg); + +int esp_setup_irq_intrstatus(int source, + irq_priority_t priority, + int type, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg); + +int esp_setup_irq_with_flags_intrstatus(int source, + int flags, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg); /**************************************************************************** * Name: esp_teardown_irq @@ -162,23 +184,7 @@ int esp_setup_irq(int source, irq_priority_t priority, int type); void esp_teardown_irq(int source, int cpuint); /**************************************************************************** - * Name: esp_intr_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_intr_noniram_disable(void); - -/**************************************************************************** - * Name: esp_intr_noniram_enable + * Name: esp_old_intr_noniram_enable * * Description: * Enable interrupts that aren't specifically marked as running from IRAM. @@ -191,113 +197,102 @@ void esp_intr_noniram_disable(void); * ****************************************************************************/ -void esp_intr_noniram_enable(void); - -/**************************************************************************** - * Name: esp_get_irq - * - * Description: - * This function returns the IRQ associated with a CPU interrupt - * - * Input Parameters: - * cpuint - The CPU interrupt associated to the IRQ - * - * Returned Value: - * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if - * IRQ is not yet assigned to a CPU interrupt. - * - ****************************************************************************/ - -int esp_get_irq(int cpuint); +void esp_old_intr_noniram_enable(void); /**************************************************************************** - * Name: esp_set_irq + * Name: esp_get_cpuint * * Description: - * This function assigns a CPU interrupt to a specific IRQ number. It - * updates the mapping between IRQ numbers and CPU interrupts, allowing - * the system to correctly route hardware interrupts to the appropriate - * handlers. Please note that this function is intended to be used only - * when a CPU interrupt is already assigned to an IRQ number. Otherwise, - * please check esp_setup_irq. + * This function returns the CPU interrupt associated with an IRQ * * Input Parameters: - * irq - The IRQ number to be associated with the CPU interrupt. - * cpuint - The CPU interrupt to be associated with the IRQ number. + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt * * Returned Value: - * None + * The CPU interrupt associated with such IRQ or a negated errno value on + * failure. * ****************************************************************************/ -void esp_set_irq(int irq, int cpuint); +int esp_get_cpuint(int cpu, int irq); /**************************************************************************** - * Name: esp_irq_set_iram_isr + * Name: esp_set_handle * * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. + * This function sets the handle associated with an IRQ * * Input Parameters: - * irq - The associated IRQ to set + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * handle - The handle to be associated with the IRQ * * Returned Value: * OK on success; A negated errno value on failure. * ****************************************************************************/ -int esp_irq_set_iram_isr(int irq); +int esp_set_handle(int cpu, int irq, intr_handle_t handle); /**************************************************************************** - * Name: esp32s3_irq_unset_iram_isr + * Name: esp_get_handle * * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. + * This function gets the handle associated with an IRQ * * Input Parameters: - * irq - The associated IRQ to set + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt * * Returned Value: - * OK on success; A negated errno value on failure. + * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is + * associated with the IRQ. * ****************************************************************************/ -int esp_irq_unset_iram_isr(int irq); +intr_handle_t esp_get_handle(int cpu, int irq); /**************************************************************************** - * Name: esp_irq_noniram_status + * Name: esp_get_iram_interrupt_records * * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core + * This function copies the vector that keeps track of the IRQs that ran + * when non-IRAM interrupts were disabled. * * Input Parameters: - * cpu - The CPU to check the non-IRAM interrupts state + * + * irq_count - A previously allocated pointer to store the counter of the + * interrupts that ran when non-IRAM interrupts were disabled. + * cpu - The CPU to retrieve the interrupt records for * * Returned Value: - * true if non-IRAM interrupts are enabled, false otherwise. + * None * ****************************************************************************/ -bool esp_irq_noniram_status(int cpu); +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG +void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu); +#endif /**************************************************************************** - * Name: esp_get_iram_interrupt_records + * Name: esp_cpuint_to_irq * * Description: - * This function copies the vector that keeps track of the IRQs that ran - * when non-IRAM interrupts were disabled. + * Find an IRQ associated with a given CPU interrupt by searching through + * g_handle_map. For shared interrupts, multiple IRQs may map to the same + * CPU interrupt - this function returns the first one found. * * Input Parameters: - * - * irq_count - A previously allocated pointer to store the counter of the - * interrupts that ran when non-IRAM interrupts were disabled. + * cpuint - The CPU interrupt number + * cpu - The CPU core * * Returned Value: - * None + * The IRQ number, or -1 if not found. * ****************************************************************************/ -void esp_get_iram_interrupt_records(uint64_t *irq_count); +int esp_cpuint_to_irq(int cpuint, int cpu); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/risc-v/src/common/espressif/esp_ledc.c b/arch/risc-v/src/common/espressif/esp_ledc.c index 355197c72c6ac..54ec260d4ab8c 100644 --- a/arch/risc-v/src/common/espressif/esp_ledc.c +++ b/arch/risc-v/src/common/espressif/esp_ledc.c @@ -44,7 +44,7 @@ #include "hal/ledc_hal.h" #include "hal/ledc_types.h" #include "soc/soc_caps.h" -#include "soc/ledc_periph.h" +#include "hal/ledc_periph.h" #include "clk_ctrl_os.h" #include "esp_clk_tree.h" #include "esp_private/esp_clk_tree_common.h" @@ -1161,7 +1161,7 @@ static int ledc_channel_output_enable(ledc_channel_t channel) } ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, true); - ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, true); + ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel); return OK; } @@ -1196,7 +1196,7 @@ static int ledc_channel_output_disable(ledc_channel_t channel) ledc_hal_set_idle_level(&(p_ledc_obj->ledc_hal), channel, 0); ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, false); - ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, false); + ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel); leave_critical_section(flags); return OK; diff --git a/arch/risc-v/src/common/espressif/esp_lowputc.c b/arch/risc-v/src/common/espressif/esp_lowputc.c index af400264e8f58..87d040624c5c2 100644 --- a/arch/risc-v/src/common/espressif/esp_lowputc.c +++ b/arch/risc-v/src/common/espressif/esp_lowputc.c @@ -48,17 +48,16 @@ #include "esp_lowputc.h" #include "esp_usbserial.h" #include "esp_private/critical_section.h" -#include "esp_private/uart_share_hw_ctrl.h" #include "hal/uart_hal.h" -#include "soc/uart_periph.h" +#include "hal/uart_periph.h" #include "periph_ctrl.h" #include "soc/gpio_sig_map.h" #ifdef CONFIG_ESPRESSIF_LP_UART # include "lp_core_uart.h" # include "soc/uart_pins.h" # include "hal/rtc_io_hal.h" -# include "soc/uart_periph.h" +# include "hal/uart_periph.h" # include "driver/rtc_io.h" # include "io_mux.h" #endif @@ -330,19 +329,19 @@ bool esp_lowputc_uart_module_enable(const struct esp_uart_s *priv) { if (uart_num < SOC_UART_HP_NUM) { - HP_UART_BUS_CLK_ATOMIC() + PERIPH_RCC_ATOMIC() { uart_ll_enable_bus_clock(uart_num, true); } if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM) { - HP_UART_BUS_CLK_ATOMIC() + PERIPH_RCC_ATOMIC() { uart_ll_reset_register(uart_num); } - HP_UART_SRC_CLK_ATOMIC() + PERIPH_RCC_ATOMIC() { uart_ll_sclk_enable(g_uart_context[uart_num].hal.dev); } @@ -456,18 +455,21 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv) { esp_configgpio(priv->rxpin, INPUT | PULLUP); esp_gpio_matrix_in(priv->rxpin, - UART_PERIPH_SIGNAL(priv->id, SOC_UART_RX_PIN_IDX), + UART_PERIPH_SIGNAL(priv->id, + SOC_UART_PERIPH_SIGNAL_RX), 0); esp_configgpio(priv->txpin, OUTPUT); esp_gpio_matrix_out(priv->txpin, - UART_PERIPH_SIGNAL(priv->id, SOC_UART_TX_PIN_IDX), + UART_PERIPH_SIGNAL(priv->id, + SOC_UART_PERIPH_SIGNAL_TX), 0, 0); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - uint32_t sig = UART_PERIPH_SIGNAL(priv->id, SOC_UART_RTS_PIN_IDX); + uint32_t sig = UART_PERIPH_SIGNAL(priv->id, + SOC_UART_PERIPH_SIGNAL_RTS); esp_configgpio(priv->rtspin, OUTPUT); esp_gpio_matrix_out(priv->rtspin, sig, 0, 0); @@ -477,7 +479,8 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv) #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow) { - uint32_t sig = UART_PERIPH_SIGNAL(priv->id, SOC_UART_CTS_PIN_IDX); + uint32_t sig = UART_PERIPH_SIGNAL(priv->id, + SOC_UART_PERIPH_SIGNAL_CTS); esp_configgpio(priv->ctspin, INPUT | PULLUP); esp_gpio_matrix_in(priv->ctspin, sig, 0); diff --git a/arch/risc-v/src/common/espressif/esp_mcpwm.c b/arch/risc-v/src/common/espressif/esp_mcpwm.c index 495a535f3ca1a..5e5def1b81549 100644 --- a/arch/risc-v/src/common/espressif/esp_mcpwm.c +++ b/arch/risc-v/src/common/espressif/esp_mcpwm.c @@ -48,8 +48,8 @@ #include "esp_attr.h" #include "hal/mcpwm_hal.h" #include "hal/mcpwm_ll.h" -#include "soc/mcpwm_periph.h" -#include "soc/ledc_periph.h" +#include "hal/mcpwm_periph.h" +#include "hal/ledc_periph.h" #include "periph_ctrl.h" #include "hal/clk_tree_hal.h" #include "esp_clk_tree.h" @@ -1308,7 +1308,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower, if (!enable) { esp_gpio_matrix_in(0x3a, - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ gpio_faults[lower->fault_id].fault_sig, false); return OK; @@ -1323,7 +1323,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower, esp_gpio_matrix_in( lower->fault_pin, - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ gpio_faults[lower->fault_id].fault_sig, false); @@ -1385,13 +1385,13 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower, esp_gpio_matrix_out( lower->generator_pins[MCPWM_GENERATOR_0], - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].generators[MCPWM_GENERATOR_0].pwm_sig, false, false); esp_gpio_matrix_out( lower->generator_pins[MCPWM_GENERATOR_1], - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].generators[MCPWM_GENERATOR_1].pwm_sig, false, false); @@ -1399,14 +1399,12 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower, #ifdef CONFIG_ESP_MCPWM_TEST_LOOPBACK esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH0_GPIO, - mcpwm_periph_signals.\ - groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].\ generators[MCPWM_GENERATOR_0].pwm_sig, 0, 0); esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH1_GPIO, - mcpwm_periph_signals.\ - groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].\ generators[MCPWM_GENERATOR_1].pwm_sig, 0, 0); @@ -1691,7 +1689,8 @@ static int esp_mcpwm_capture_set_gpio( } esp_gpio_matrix_in(lower->gpio_pin, - mcpwm_periph_signals.groups[0].captures[lower->channel_id].cap_sig, + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ + captures[lower->channel_id].cap_sig, false); cpinfo("GPIO: %d configured for channel %d\n", lower->gpio_pin, @@ -1717,32 +1716,25 @@ static int esp_mcpwm_capture_set_gpio( ****************************************************************************/ #if defined(CONFIG_ESP_MCPWM_CAPTURE) || defined(ESP_MCPMW_MOTOR_FAULT) -static int esp_mcpwm_isr_register(int (*fn)(int, void *, void *), - void *arg) +static int esp_mcpwm_isr_register(int (*fn)(int, void *, void *), void *arg) { int cpuint; int ret; - cpuint = esp_setup_irq(mcpwm_periph_signals.groups[0].irq_id, + cpuint = esp_setup_irq(soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ + irq_id, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + fn, + arg); if (cpuint < 0) { cperr("Failed to allocate a CPU interrupt.\n"); return -ENOMEM; } - ret = irq_attach(ESP_SOURCE2IRQ(mcpwm_periph_signals.groups[0].irq_id), - fn, - &g_mcpwm_common); - if (ret < 0) - { - cperr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(mcpwm_periph_signals.groups[0].irq_id, cpuint); - return ret; - } - - up_enable_irq(ESP_SOURCE2IRQ(mcpwm_periph_signals.groups[0].irq_id)); + up_enable_irq(ESP_SOURCE2IRQ( + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].irq_id)); return ret; } diff --git a/arch/risc-v/src/common/espressif/esp_oneshot.c b/arch/risc-v/src/common/espressif/esp_oneshot.c index ff9307d1aaca7..26bd53cccb294 100644 --- a/arch/risc-v/src/common/espressif/esp_oneshot.c +++ b/arch/risc-v/src/common/espressif/esp_oneshot.c @@ -43,9 +43,9 @@ #include "esp_attr.h" #include "hal/timer_hal.h" #include "hal/timer_ll.h" +#include "hal/timer_periph.h" #include "periph_ctrl.h" #include "soc/clk_tree_defs.h" -#include "soc/timer_periph.h" #include "esp_private/esp_clk_tree_common.h" /**************************************************************************** @@ -403,7 +403,7 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) uint32_t counter_src_hz = 0; uint32_t prescale; int ret = OK; - periph_module_t periph; + shared_periph_module_t periph; int irq; UNUSED(chan); @@ -412,14 +412,14 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) lower->running = false; - periph = timer_group_periph_signals.groups[GROUP_ID].module; + periph = soc_timg_gptimer_signals[GROUP_ID][TIMER_ID].parent_module; PERIPH_RCC_ACQUIRE_ATOMIC(periph, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(GROUP_ID, true); - timer_ll_reset_register(GROUP_ID); + timg_ll_enable_bus_clock(GROUP_ID, true); + timg_ll_reset_register(GROUP_ID); } } @@ -434,10 +434,13 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) /* Configure clock source */ - timer_ll_set_clock_source(GROUP_ID, lower->hal.timer_id, - GPTIMER_CLK_SRC_DEFAULT); + ONESHOT_CLOCK_SRC_ATOMIC() + { + timer_ll_set_clock_source(GROUP_ID, lower->hal.timer_id, + GPTIMER_CLK_SRC_DEFAULT); - timer_ll_enable_clock(GROUP_ID, lower->hal.timer_id, true); + timer_ll_enable_clock(GROUP_ID, lower->hal.timer_id, true); + } /* Calculate the suitable prescaler according to the current APB * frequency to generate a period of 1 us. @@ -452,18 +455,16 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) timer_ll_set_clock_prescale(lower->hal.dev, lower->hal.timer_id, prescale); - irq = timer_group_periph_signals.groups[GROUP_ID].timer_irq_id[TIMER_ID]; + irq = soc_timg_gptimer_signals[GROUP_ID][TIMER_ID].irq_id; esp_setup_irq(irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_oneshot_isr, + lower); oneshot_count_init(&lower->lh, USEC_PER_SEC / resolution); - /* Attach the handler for the timer IRQ */ - - irq_attach(ESP_SOURCE2IRQ(irq), (xcpt_t)esp_oneshot_isr, lower); - /* Enable the allocated CPU interrupt */ up_enable_irq(ESP_SOURCE2IRQ(irq)); diff --git a/arch/risc-v/src/common/espressif/esp_pcnt.c b/arch/risc-v/src/common/espressif/esp_pcnt.c index 7326f9aae25b4..88b122e9cacbb 100644 --- a/arch/risc-v/src/common/espressif/esp_pcnt.c +++ b/arch/risc-v/src/common/espressif/esp_pcnt.c @@ -53,7 +53,7 @@ #include "soc/gpio_sig_map.h" #include "periph_ctrl.h" #include "soc/soc_caps.h" -#include "soc/pcnt_periph.h" +#include "hal/pcnt_periph.h" #include "soc/pcnt_reg.h" #include "soc/pcnt_struct.h" #include "soc/gpio_pins.h" @@ -65,10 +65,10 @@ * Pre-processor Definitions ****************************************************************************/ -#define PCNT_UNIT_COUNT SOC_PCNT_GROUPS * SOC_PCNT_UNITS_PER_GROUP -#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id/SOC_PCNT_CHANNELS_PER_UNIT) -#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (SOC_PCNT_CHANNELS_PER_UNIT * unit_id)) -#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((SOC_PCNT_CHANNELS_PER_UNIT * unit_id) + chan_id) +#define PCNT_UNIT_COUNT PCNT_LL_GET(INST_NUM) * PCNT_LL_GET(UNITS_PER_INST) +#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id / PCNT_LL_GET(CHANS_PER_UNIT)) +#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (PCNT_LL_GET(CHANS_PER_UNIT) * unit_id)) +#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((PCNT_LL_GET(CHANS_PER_UNIT) * unit_id) + chan_id) #if !SOC_RCC_IS_INDEPENDENT # define PCNT_RCC_ATOMIC() PERIPH_RCC_ATOMIC() @@ -115,7 +115,7 @@ struct esp_pcnt_priv_s spinlock_t lock; /* Device specific lock. */ int (*cb)(int, void *, void *); /* User defined callback */ uint32_t accum_value; /* Accumulator value of overflowed PCNT unit */ - bool channels[SOC_PCNT_CHANNELS_PER_UNIT]; /* Channel information of PCNT unit */ + bool channels[PCNT_LL_GET(CHANS_PER_UNIT)]; /* Channel information of PCNT unit */ struct esp_pcnt_watch_point_priv_s watchers[PCNT_LL_WATCH_EVENT_MAX]; /* array of PCNT watchers */ }; @@ -125,10 +125,8 @@ struct esp_pcnt_priv_s static int esp_pcnt_open(struct cap_lowerhalf_s *dev); static int esp_pcnt_close(struct cap_lowerhalf_s *dev); -static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, - void *arg); -static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), - int intr_alloc_flags); +static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, void *arg); +static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg); static int esp_pcnt_ioctl(struct cap_lowerhalf_s *dev, int cmd, unsigned long arg); static int esp_pcnt_unit_enable(struct cap_lowerhalf_s *dev); @@ -166,7 +164,7 @@ static pcnt_hal_context_t ctx; /* Struct of the common layer static mutex_t g_pcnt_mutex = NXMUTEX_INITIALIZER; /* Mutual exclusion m:utex */ static bool g_pcnt_intr = false; /* ISR register flag for peripheral */ static spinlock_t g_pcnt_lock = SP_UNLOCKED; /* PCNT unit lock */ -static int g_pcnt_refs[SOC_PCNT_GROUPS] = /* Reference count */ +static int g_pcnt_refs[PCNT_LL_GET(INST_NUM)] = /* Reference count */ { 0 }; @@ -378,8 +376,7 @@ static int esp_pcnt_ioctl(struct cap_lowerhalf_s *dev, int cmd, * ****************************************************************************/ -static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, - void *arg) +static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, void *arg) { struct esp_pcnt_priv_s *unit; int unit_id = 0; @@ -388,13 +385,13 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, struct esp_pcnt_watch_event_data_s data; irqstate_t flags; - for (unit_id = 0; unit_id < SOC_PCNT_UNITS_PER_GROUP; unit_id++) + for (unit_id = 0; unit_id < PCNT_LL_GET(UNITS_PER_INST); unit_id++) { if (intr_status & PCNT_LL_UNIT_WATCH_EVENT(unit_id)) break; } - if (unit_id < SOC_PCNT_UNITS_PER_GROUP) + if (unit_id < PCNT_LL_GET(UNITS_PER_INST)) { unit = &pcnt_units[unit_id]; pcnt_ll_clear_intr_status(ctx.dev, PCNT_LL_UNIT_WATCH_EVENT(unit_id)); @@ -444,7 +441,7 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, * * Input Parameters: * fn - Pointer to the ISR function. - * intr_alloc_flags - Flags for the interrupt allocation. + * arg - Pointer to the argument to be passed to the ISR. * * Returned Value: * Returns OK on successful registration of the ISR; a negated errno value @@ -452,8 +449,7 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, * ****************************************************************************/ -static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), - int intr_alloc_flags) +static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg) { int cpuint; int ret; @@ -461,26 +457,18 @@ static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), DEBUGASSERT(fn); - cpuint = esp_setup_irq(pcnt_periph_signals.groups[0].irq, + cpuint = esp_setup_irq(soc_pcnt_signals[0].irq_id, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + fn, + arg); if (cpuint < 0) { cperr("Failed to allocate a CPU interrupt.\n"); return ERROR; } - ret = irq_attach(ESP_SOURCE2IRQ(pcnt_periph_signals.groups[0].irq), - fn, - 0); - if (ret < 0) - { - cperr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(pcnt_periph_signals.groups[0].irq, cpuint); - return ERROR; - } - - up_enable_irq(ESP_SOURCE2IRQ(pcnt_periph_signals.groups[0].irq)); + up_enable_irq(ESP_SOURCE2IRQ(soc_pcnt_signals[0].irq_id)); return OK; } @@ -858,7 +846,7 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit( if (!pcnt_units[unit_id].unit_used) { pcnt_units[unit_id].unit_used = true; - group_id = unit_id / SOC_PCNT_UNITS_PER_GROUP; + group_id = unit_id / PCNT_LL_GET(UNITS_PER_INST); pcnt_units[unit_id].group_id = group_id; break; } @@ -889,7 +877,7 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit( if (!g_pcnt_intr) { nxmutex_lock(&g_pcnt_mutex); - ret = esp_pcnt_isr_register(esp_pcnt_isr_default, 0); + ret = esp_pcnt_isr_register(esp_pcnt_isr_default, NULL); if (ret < 0) { pcnt_units[unit_id].unit_used = false; @@ -967,7 +955,7 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev) return ERROR; } - for (i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++) + for (i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++) { if (!priv->channels[i]) { @@ -996,7 +984,7 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev) pcnt_ll_enable_bus_clock(priv->group_id, false); } - esp_teardown_irq(pcnt_periph_signals.groups[0].irq, -ENOMEM); + esp_teardown_irq(soc_pcnt_signals[0].irq_id, -ENOMEM); } spin_unlock_irqrestore(&priv->lock, flags); @@ -1106,7 +1094,7 @@ int esp_pcnt_unit_add_watch_point(struct cap_lowerhalf_s *dev, else { - int thres_num = SOC_PCNT_THRES_POINT_PER_UNIT - 1; + int thres_num = PCNT_LL_GET(THRES_POINT_PER_UNIT) - 1; switch (thres_num) { case 1: @@ -1261,7 +1249,6 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, int gpio_mode; int virt_gpio; int ret_id = 0; - const pcnt_signal_conn_t *chan; if (!config) { @@ -1281,7 +1268,7 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, return ERROR; } - for (int i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++) + for (int i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++) { if (!priv->channels[i]) { @@ -1300,13 +1287,13 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, (config->flags && ESP_PCNT_CHAN_IO_LOOPBACK ? OUTPUT_FUNCTION : 0); virt_gpio = (config->flags && ESP_PCNT_CHAN_VIRT_LVL_IO_LVL) ? GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT; - chan = &pcnt_periph_signals; if (config->edge_gpio_num >= 0) { esp_configgpio(config->edge_gpio_num, gpio_mode); esp_gpio_matrix_in(config->edge_gpio_num, - chan->groups[0].units[unit_id].channels[channel_id].pulse_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + pulse_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN)); } else @@ -1314,7 +1301,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, /* using virtual IO */ esp_gpio_matrix_in(virt_gpio, - chan->groups[0].units[unit_id].channels[channel_id].pulse_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + pulse_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN)); } @@ -1322,7 +1310,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, { esp_configgpio(config->level_gpio_num, gpio_mode); esp_gpio_matrix_in(config->level_gpio_num, - chan->groups[0].units[unit_id].channels[channel_id].control_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + ctl_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN)); } else @@ -1330,7 +1319,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, /* using virtual IO */ esp_gpio_matrix_in(virt_gpio, - chan->groups[0].units[unit_id].channels[channel_id].control_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + ctl_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN)); } diff --git a/arch/risc-v/src/common/espressif/esp_rmt.c b/arch/risc-v/src/common/espressif/esp_rmt.c index 3f7e1d4b48206..83b47e9e9a280 100644 --- a/arch/risc-v/src/common/espressif/esp_rmt.c +++ b/arch/risc-v/src/common/espressif/esp_rmt.c @@ -46,16 +46,14 @@ #include "esp_gpio.h" #include "esp_irq.h" -#include "esp_attr.h" -#include "hal/gpio_types.h" -#include "hal/rmt_hal.h" -#include "hal/rmt_ll.h" -#include "periph_ctrl.h" -#include "soc/gpio_sig_map.h" -#include "soc/rmt_periph.h" -#include "soc/soc_caps.h" -#include "esp_clk_tree.h" -#include "esp_private/esp_clk_tree_common.h" +#include "esp_err.h" +#include "driver/rmt_types.h" +#include "driver/rmt_rx.h" +#include "driver/rmt_tx.h" +#include "driver/rmt_encoder.h" +#include "driver/rmt_common.h" +#include "esp_private/rmt.h" +#include "rmt_private.h" #include "esp_rmt.h" @@ -78,45 +76,6 @@ #define RMT_ENCODE_RX_CHANNEL(decode_chan) \ ((decode_chan + RMT_RX_CHANNEL_ENCODING_START)) -/* Default configuration for TX channel */ - -#define RMT_DEFAULT_CONFIG_TX(gpio, channel_id) \ - { \ - .rmt_mode = RMT_MODE_TX, \ - .channel = channel_id, \ - .gpio_num = gpio, \ - .clk_div = RMT_DEFAULT_CLK_DIV, \ - .mem_block_num = 1, \ - .flags = 0, \ - .tx_config = { \ - .carrier_freq_hz = 38000, \ - .carrier_level = RMT_CARRIER_LEVEL_HIGH, \ - .idle_level = RMT_IDLE_LEVEL_LOW, \ - .carrier_duty_percent = 33, \ - .loop_count = 0, \ - .carrier_en = false, \ - .loop_en = false, \ - .idle_output_en = true, \ - } \ - } - -/* Default configuration for RX channel */ - -#define RMT_DEFAULT_CONFIG_RX(gpio, channel_id) \ - { \ - .rmt_mode = RMT_MODE_RX, \ - .channel = channel_id, \ - .gpio_num = gpio, \ - .clk_div = RMT_DEFAULT_CLK_DIV, \ - .mem_block_num = 1, \ - .flags = 0, \ - .rx_config = { \ - .idle_threshold = 12000, \ - .filter_ticks_thresh = 100, \ - .filter_en = true, \ - } \ - } - #if SOC_PERIPH_CLK_CTRL_SHARED #define RMT_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() #else @@ -129,112 +88,10 @@ #define RMT_RCC_ATOMIC() #endif -#define rmt_item32_t rmt_symbol_word_t - /**************************************************************************** * Private Types ****************************************************************************/ -/* RMT channel ID */ - -enum rmt_channel_e -{ - RMT_CHANNEL_0, /* RMT channel number 0 */ - RMT_CHANNEL_1, /* RMT channel number 1 */ - RMT_CHANNEL_2, /* RMT channel number 2 */ - RMT_CHANNEL_3, /* RMT channel number 3 */ -#if SOC_RMT_CHANNELS_PER_GROUP > 4 - RMT_CHANNEL_4, /* RMT channel number 4 */ - RMT_CHANNEL_5, /* RMT channel number 5 */ - RMT_CHANNEL_6, /* RMT channel number 6 */ - RMT_CHANNEL_7, /* RMT channel number 7 */ -#endif - RMT_CHANNEL_MAX /* Number of RMT channels */ -}; - -typedef enum rmt_channel_e rmt_channel_t; - -/* RMT Channel Working Mode (TX or RX) */ - -enum rmt_mode_e -{ - RMT_MODE_TX, /* RMT TX mode */ - RMT_MODE_RX, /* RMT RX mode */ - RMT_MODE_MAX -}; - -typedef enum rmt_mode_e rmt_mode_t; - -/* RMT Idle Level */ - -enum rmt_idle_level_e -{ - RMT_IDLE_LEVEL_LOW, /* RMT TX idle level: low Level */ - RMT_IDLE_LEVEL_HIGH, /* RMT TX idle level: high Level */ - RMT_IDLE_LEVEL_MAX, -}; - -typedef enum rmt_idle_level_e rmt_idle_level_t; - -/* RMT Carrier Level */ - -enum rmt_carrier_level_e -{ - RMT_CARRIER_LEVEL_LOW, /* RMT carrier wave is modulated for low Level output */ - RMT_CARRIER_LEVEL_HIGH, /* RMT carrier wave is modulated for high Level output */ - RMT_CARRIER_LEVEL_MAX -}; - -typedef enum rmt_carrier_level_e rmt_carrier_level_t; - -/* RMT Channel Status */ - -enum rmt_channel_status_e -{ - RMT_CHANNEL_UNINIT, /* RMT channel uninitialized */ - RMT_CHANNEL_IDLE, /* RMT channel status idle */ - RMT_CHANNEL_BUSY, /* RMT channel status busy */ -}; - -typedef enum rmt_channel_status_e rmt_channel_status_t; - -/* RMT hardware memory layout */ - -struct rmt_channel_data_s -{ - volatile rmt_item32_t data32[SOC_RMT_MEM_WORDS_PER_CHANNEL]; -}; - -struct rmt_mem_s -{ - struct rmt_channel_data_s chan[SOC_RMT_CHANNELS_PER_GROUP]; -}; - -typedef struct rmt_mem_s rmt_mem_t; - -struct rmt_dev_common_s -{ - rmt_hal_context_t hal; /* HAL context */ - rmutex_t rmt_driver_isr_lock; - - /* Mutex lock for protecting concurrent register/unregister of the RMT - * channels' ISR. - */ - - spinlock_t rmt_spinlock; - - /* Bitmask of installed drivers' channels, used to protect concurrent - * register/unregister of the RMT channels' ISR. - */ - - uint8_t rmt_driver_channels; - bool rmt_module_enabled; - - /* Bitmap of channels already added in the synchronous group */ - - uint32_t synchro_channel_mask; -}; - struct rmt_dev_lowerhalf_s { /* The following block is part of the upper-half device struct */ @@ -246,118 +103,19 @@ struct rmt_dev_lowerhalf_s /* The following is private to the ESP32 RMT driver */ - rmt_mode_t mode; - struct rmt_dev_common_s *common; /* RMT peripheral common parameters */ -}; - -struct rmt_obj_s -{ - size_t tx_offset; - size_t tx_len_rem; - size_t tx_sub_len; - bool wait_done; /* Mark whether wait tx done */ - bool loop_autostop; /* Mark whether loop auto-stop is enabled */ - rmt_channel_t channel; - const rmt_item32_t *tx_data; - sem_t tx_sem; -#ifdef CONFIG_SPIRAM_USE_MALLOC - int intr_alloc_flags; - sem_t tx_sem_buffer; -#endif - rmt_item32_t *tx_buf; - struct circbuf_s rx_buf; - sem_t rx_sem; -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - rmt_item32_t *rx_item_buf; - uint32_t rx_item_buf_size; - uint32_t rx_item_len; - int rx_item_start_idx; -#endif - void *tx_context; - size_t sample_size_remain; - const uint8_t *sample_cur; -}; - -typedef struct rmt_obj_s rmt_obj_t; - -/* Data struct of RMT TX configure parameters */ - -struct rmt_tx_config_s -{ - uint32_t carrier_freq_hz; /* RMT carrier frequency */ - rmt_carrier_level_t carrier_level; /* Level of the RMT output, when the carrier is applied */ - rmt_idle_level_t idle_level; /* RMT idle level */ - uint8_t carrier_duty_percent; /* RMT carrier duty (%) */ - uint32_t loop_count; /* Maximum loop count, only take effect for chips that is capable of `SOC_RMT_SUPPORT_TX_LOOP_COUNT` */ - bool carrier_en; /* RMT carrier enable */ - bool loop_en; /* Enable sending RMT items in a loop */ - bool idle_output_en; /* RMT idle level output enable */ -}; - -/* Data struct of RMT RX configure parameters */ - -struct rmt_rx_config_s -{ - uint16_t idle_threshold; /* RMT RX idle threshold */ - uint8_t filter_ticks_thresh; /* RMT filter tick number */ - bool filter_en; /* RMT receiver filter enable */ -#if SOC_RMT_SUPPORT_RX_DEMODULATION - bool rm_carrier; /* RMT receiver remove carrier enable */ - uint32_t carrier_freq_hz; /* RMT carrier frequency */ - uint8_t carrier_duty_percent; /* RMT carrier duty (%) */ - rmt_carrier_level_t carrier_level; /* The level to remove the carrier */ -#endif -}; - -struct rmt_channel_config_s -{ - rmt_mode_t rmt_mode; /* RMT mode: transmitter or receiver */ - rmt_channel_t channel; /* RMT channel */ - int gpio_num; /* RMT GPIO number */ - uint8_t clk_div; /* RMT channel counter divider */ - uint8_t mem_block_num; /* RMT memory block number */ - uint32_t flags; /* RMT channel extra configurations, OR'd with RMT_CHANNEL_FLAGS_[*] */ - union - { - struct rmt_tx_config_s tx_config; /* RMT TX parameter */ - struct rmt_rx_config_s rx_config; /* RMT RX parameter */ - }; + rmt_channel_handle_t handle; + rmt_encoder_handle_t encoder; }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void rmt_module_enable(void); -static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst); -static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst); -static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en); -static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, - uint16_t evt_thresh); -static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, - gpio_num_t gpio_num, bool invert_signal); -static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode); -static int rmt_internal_config(rmt_dev_t *dev, - const struct rmt_channel_config_s *rmt_param); -static int rmt_config(const struct rmt_channel_config_s *rmt_param); -static void rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item, - uint16_t item_num, uint16_t mem_offset); -static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg, - int intr_alloc_flags); -static int rmt_driver_isr_default(int irq, void *context, void *arg); -static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, - int intr_alloc_flags); -static int rmt_write_items(rmt_channel_t channel, - const rmt_item32_t *rmt_item, - int item_num, - bool wait_tx_done); static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, size_t buflen); static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, size_t buflen); -static struct rmt_dev_s - *esp_rmtinitialize(struct rmt_channel_config_s config); /**************************************************************************** * Private Data @@ -369,1632 +127,334 @@ static const struct rmt_ops_s g_rmtops = .write = esp_rmt_write, }; -static struct rmt_dev_common_s g_rmtdev_common = -{ - .hal.regs = &RMT, - .rmt_driver_isr_lock = NXRMUTEX_INITIALIZER, - .rmt_driver_channels = 0, - .rmt_module_enabled = false, - .synchro_channel_mask = 0 -}; - -static struct rmt_obj_s *p_rmt_obj[RMT_CHANNEL_MAX]; - -#ifdef CONFIG_RMT_LOOP_TEST_MODE -static rmt_channel_t g_tx_channel = RMT_CHANNEL_MAX; -static rmt_channel_t g_rx_channel = RMT_CHANNEL_MAX; -#endif - -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT -uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; -#else -uint32_t g_rmt_source_clock_hz; -#endif - -/* RMTMEM address is declared in .peripherals.ld */ - -extern rmt_mem_t RMTMEM; - /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: rmt_module_enable + * Name: esp_rmt_read * * Description: - * This function enables the RMT (Remote Control) module if it's not - * already enabled. + * This function reads data from the RMT device. + * It starts the RMT module in receiving mode for a specific channel and + * checks for any errors. If an error occurs during the start of the RMT + * module, it returns the error code. Please note that this function + * starts the receiver, but the actual data is read from the ring buffer + * by the upper half driver. * * Input Parameters: - * None. + * dev - Pointer to the RMT device structure. + * buffer - Pointer to the buffer where the read data should be stored. + * buflen - The maximum amount of data to be read. * * Returned Value: - * None. + * Returns the number of bytes read from the RMT device; a negated errno + * value is returned on any failure. * ****************************************************************************/ -static void rmt_module_enable(void) +static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, + size_t buflen) { - irqstate_t flags; + esp_err_t esp_ret; + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; + rmt_receive_config_t receive_config = + { + .signal_range_min_ns = 1250, + .signal_range_max_ns = 3000000, + }; - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); + DEBUGASSERT((buflen % 4) == 0); - if (g_rmtdev_common.rmt_module_enabled == false) + if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4)) { - RMT_RCC_ATOMIC() - { - rmt_ll_enable_bus_clock(0, true); - rmt_ll_reset_register(0); - } - - rmt_ll_mem_power_by_pmu(g_rmtdev_common.hal.regs); - g_rmtdev_common.rmt_module_enabled = true; + rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested " + "read bytes (%d bytes). A partial read will take place!\n", + CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE, + buflen); } - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); -} - -/**************************************************************************** - * Name: rmt_set_rx_thr_intr_en - * - * Description: - * This function enables or disables the RMT RX threshold interrupt. When - * the number of received items reaches the threshold, an interrupt is - * triggered if this feature is enabled. - * - * Input Parameters: - * channel - The RMT channel. - * en - Enable (true) or disable (false) the RX threshold int. - * evt_thresh - The number of received items that triggers the interrupt. - * - * Returned Value: - * Returns 0 on success; a negated errno value is returned on any failure. - * - ****************************************************************************/ - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG -static int rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, - uint16_t evt_thresh) -{ - irqstate_t flags; - uint32_t mask; - - DEBUGASSERT(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX); - - if (en) +#ifndef SOC_RMT_SUPPORT_RX_PINGPONG + if ((buflen / 4) > RMT_MEM_ITEM_NUM) { - uint32_t item_block_len = - rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, - RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM; - - if (evt_thresh >= item_block_len) - { - rmterr("Invalid threshold value %d\n", evt_thresh); - return -EINVAL; - } - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_rx_set_limit(g_rmtdev_common.hal.regs, - RMT_DECODE_RX_CHANNEL(channel), evt_thresh); - mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, true); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmtwarn("WARN: RMT RX channel is able to receive up to " + "%d RMT items (%d bytes)!", + RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4); } - else +#endif + + esp_ret = rmt_receive(priv->handle, buffer, + buflen, &receive_config); + if (esp_ret != ESP_OK) { - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, false); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmterr("Failed to Receive RMT data"); + return -ERROR; } - return OK; + return (ssize_t)0; } -#endif /**************************************************************************** - * Name: rmt_rx_start + * Name: esp_rmt_write * * Description: - * This function starts the RMT module in receiving mode for a specific - * channel. + * This function writes data to the RMT memory for a specific channel. It + * asserts that the length of the data is a multiple of 4, then calls the + * rmt_write_items function to write the items to the RMT memory. * * Input Parameters: - * channel - The RMT peripheral channel number. - * rx_idx_rst - If true, the RX index for the channel is reset, which means - * the receiving process will start from the beginning of the - * RMT memory block. + * dev - Pointer to the RMT device structure. + * buffer - Pointer to the data to be written to the RMT memory. + * buflen - The length of the data to be written. * * Returned Value: - * Returns OK on successful start of the RMT module in receiving mode; a - * negated errno value is returned on any failure. + * Returns the number of items written to the RMT memory. * ****************************************************************************/ -static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) +static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, + size_t buflen) { - irqstate_t flags; - rmt_channel_t ch = RMT_DECODE_RX_CHANNEL(channel); -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - const uint32_t item_block_len = - rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, ch) * - RMT_MEM_ITEM_NUM; -#endif - - DEBUGASSERT(RMT_IS_RX_CHANNEL(channel)); - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, false); - if (rx_idx_rst) + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; + rmt_transmit_config_t tx_config = { - rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, ch); - } - - rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_RX_DONE(ch)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_RX_DONE(ch), true); - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - p_rmt_obj[channel]->rx_item_start_idx = 0; - p_rmt_obj[channel]->rx_item_len = 0; - rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2); -#endif + .loop_count = 0, + }; - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, true); + DEBUGASSERT((buflen % 4) == 0); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmt_transmit(priv->handle, priv->encoder, buffer, buflen, &tx_config); + rmt_tx_wait_all_done(priv->handle, -1); - return OK; + return (ssize_t)buflen; } -/**************************************************************************** - * Name: rmt_tx_start - * - * Description: - * This function starts sending RMT items from the specific channel. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * tx_idx_rst - Set it true to reset memory index for TX. - * - * Returned Value: - * Returns OK on successful start of transmission. - * - ****************************************************************************/ - -static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst) +static size_t encoder_callback(const void *data, size_t data_size, + size_t symbols_written, size_t symbols_free, + rmt_symbol_word_t *symbols, bool *done, + void *arg) { - irqstate_t flags; + size_t data_pos = symbols_written; + rmt_symbol_word_t data_bytes = + (rmt_symbol_word_t)((uint32_t *)data)[data_pos]; + + /* Encode a single symbol */ - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + symbols[0] = data_bytes; - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - if (tx_idx_rst) + if (((symbols_written + 1) * 4) == data_size) { - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); + *done = true; } - rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_DONE(channel)); + return 1; +} - /* Enable tx end interrupt in non-loop mode */ +static bool rmt_rx_done_callback(rmt_channel_handle_t channel, + const rmt_rx_done_event_data_t *edata, + void *user_data) +{ + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)user_data; - if (!rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) - { - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_DONE(channel), true); - } - else + int bytes = circbuf_write(priv->circbuf, + edata->received_symbols, + edata->num_symbols * 4); + + nxsem_post(priv->recvsem); + if (bytes < (edata->num_symbols * 4)) { -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - rmt_ll_tx_reset_loop_count(g_rmtdev_common.hal.regs, channel); - rmt_ll_tx_enable_loop_count(g_rmtdev_common.hal.regs, channel, true); - rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_LOOP_END(channel)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_LOOP_END(channel), true); -#endif + rmterr("RMT RX BUFFER FULL"); } - rmt_ll_tx_start(g_rmtdev_common.hal.regs, channel); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - return OK; + return 0; } /**************************************************************************** - * Name: rmt_set_tx_loop_mode - * - * Description: - * This function enables or disables the loop mode for RMT transmission on - * the specified channel. The loop mode, when enabled, allows the RMT - * transmitter to continuously send items. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * loop_en - A boolean indicating whether to enable (true) or disable - * (false) the loop mode. - * - * Returned Value: - * Returns OK on successful setting of the loop mode. - * + * Public Functions ****************************************************************************/ -static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en) -{ - irqstate_t flags; - - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_tx_enable_loop(g_rmtdev_common.hal.regs, channel, loop_en); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - return OK; -} - /**************************************************************************** - * Name: rmt_set_tx_thr_intr_en + * Name: esp_rmt_tx_init * * Description: - * This function enables or disables the RMT TX threshold interrupt for the - * specified channel. The threshold is set to trigger an interrupt when the - * number of transmitted items reaches the specified value. + * Initialize the selected RMT device in TX mode * * Input Parameters: - * channel - The RMT peripheral channel number. - * en - A boolean indicating whether to enable (true) or disable - * (false) the TX threshold interrupt. - * evt_thresh - The number of transmitted items at which to trigger the - * interrupt. + * tx_pin - The pin used for the TX channel * * Returned Value: - * Returns OK on successful setting of the interrupt. + * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, - uint16_t evt_thresh) +struct rmt_dev_s *esp_rmt_tx_init(int tx_pin) { - irqstate_t flags; - - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + int channel_id; + esp_err_t ret; + struct rmt_dev_lowerhalf_s *priv; + rmt_channel_handle_t tx_chan = NULL; + rmt_encoder_handle_t simple_encoder = NULL; + rmt_tx_channel_config_t tx_chan_config = + { + .clk_src = RMT_CLK_SRC_DEFAULT, /* select source clock */ + .gpio_num = tx_pin, + .mem_block_symbols = 64, /* increase the block size can make the LED less flickering */ + .resolution_hz = 10000000, + .trans_queue_depth = 4, /* set the number of transactions that can be pending in the background */ + }; - if (en) + const rmt_simple_encoder_config_t simple_encoder_cfg = { - uint32_t item_block_len = - rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, channel) * \ - RMT_MEM_ITEM_NUM; - - DEBUGASSERT(evt_thresh <= item_block_len); + .callback = encoder_callback + }; - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_tx_set_limit(g_rmtdev_common.hal.regs, channel, evt_thresh); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_THRES(channel), true); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - } - else + ret = rmt_new_tx_channel(&tx_chan_config, &tx_chan); + if (ret != ESP_OK) { - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_THRES(channel), false); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmterr("Failed to Initialize RMT TX channel"); + return NULL; } - return OK; -} - -/**************************************************************************** - * Name: rmt_set_gpio - * - * Description: - * This function configures the GPIO for the specified RMT (Remote Control) - * channel and mode. It sets the GPIO to the appropriate input or output - * function based on the mode, and configures the signal inversion if - * necessary. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * mode - The mode of operation for the RMT channel (RMT_MODE_TX - * for transmission, RMT_MODE_RX for reception). - * gpio_num - The GPIO number to configure for the RMT channel. - * invert_signal - A boolean indicating whether to invert the signal. - * - * Returned Value: - * Returns OK on successful configuration of the GPIO. - * - ****************************************************************************/ - -static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, - gpio_num_t gpio_num, bool invert_signal) -{ - int ret; + ret = rmt_new_simple_encoder(&simple_encoder_cfg, &simple_encoder); + if (ret != ESP_OK) + { + rmterr("Failed to Initialize RMT Simple Encoder"); + return NULL; + } - DEBUGASSERT(channel < RMT_CHANNEL_MAX); - DEBUGASSERT(mode < RMT_MODE_MAX); - DEBUGASSERT((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || - (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && - (mode == RMT_MODE_TX))); + ret = rmt_enable(tx_chan); + if (ret != ESP_OK) + { + rmterr("Failed to Enable RMT TX channel"); + return NULL; + } - if (mode == RMT_MODE_TX) + priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); + if (priv) { - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); - esp_configgpio(gpio_num, OUTPUT); - esp_gpio_matrix_out( - gpio_num, - rmt_periph_signals.groups[0].channels[channel].tx_sig, - invert_signal, 0); + priv->ops = &g_rmtops; + priv->handle = tx_chan; + priv->encoder = simple_encoder; } else { - DEBUGASSERT(RMT_IS_RX_CHANNEL(channel)); - esp_configgpio(gpio_num, INPUT); - esp_gpio_matrix_in( - gpio_num, - rmt_periph_signals.groups[0].channels[channel].rx_sig, - invert_signal); + rmterr("ERROR: memory allocation failed\n"); + return NULL; } - return OK; -} - -/**************************************************************************** - * Name: rmt_is_channel_number_valid - * - * Description: - * This function checks if the provided RMT channel number is valid for the - * specified mode (TX or RX). For RX mode, it checks if the channel number - * is within the range of valid RX channels and less than the maximum - * channel number. For TX mode, it checks if the channel number is a valid - * TX channel. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * mode - The mode of operation for the RMT channel (RMT_MODE_TX for - * transmission, RMT_MODE_RX for reception). - * - * Returned Value: - * Returns true if the channel number is valid, false otherwise. - * - ****************************************************************************/ - -static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode) -{ - if (mode == RMT_MODE_RX) + ret = rmt_get_channel_id(tx_chan, &channel_id); + if (ret != ESP_OK) { - return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX); + rmterr("Failed to Get RMT RX channel ID"); + return NULL; } - return (channel >= 0) && RMT_IS_TX_CHANNEL(channel); + priv->minor = channel_id + RMT_TX_CHANNEL_OFFSET_IN_GROUP; + + return (struct rmt_dev_s *)priv; } /**************************************************************************** - * Name: rmt_internal_config + * Name: esp_rmt_rx_init * * Description: - * This function configures the RMT peripheral with provided parameters. - * It sets the mode (TX or RX), channel, GPIO number, memory block number, - * clock divider, carrier frequency, and carrier enable flag. It also - * configures the clock source, memory access, idle level, carrier - * modulation, and other settings based on the mode and parameters. + * Initialize the selected RMT device in RX mode * * Input Parameters: - * dev - Pointer to the RMT peripheral device structure. - * rmt_param - Pointer to the structure containing the RMT channel - * configuration parameters. + * rx_pin - The pin used for the RX channel * * Returned Value: - * Returns OK on successful configuration of the RMT peripheral. + * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -static int rmt_internal_config(rmt_dev_t *dev, - const struct rmt_channel_config_s *rmt_param) +struct rmt_dev_s *esp_rmt_rx_init(int rx_pin) { - uint8_t mode = rmt_param->rmt_mode; - uint8_t channel = rmt_param->channel; - uint8_t gpio_num = rmt_param->gpio_num; - uint8_t mem_cnt = rmt_param->mem_block_num; - uint8_t clk_div = rmt_param->clk_div; - uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz; - bool carrier_en = rmt_param->tx_config.carrier_en; - uint32_t rmt_source_clk_hz; - irqstate_t flags; - int ret = OK; - - if (!rmt_is_channel_number_valid(channel, mode)) + int channel_id; + esp_err_t esp_ret; + int ret; + struct rmt_dev_lowerhalf_s *priv; + rmt_channel_handle_t rx_chan = NULL; + rmt_rx_channel_config_t rx_channel_cfg = { - rmterr("Invalid channel number %u for %s mode!", - channel, mode == RMT_MODE_TX ? "transmitter" : "receiver"); - return -EINVAL; - } + .clk_src = RMT_CLK_SRC_DEFAULT, + .resolution_hz = 10000000, + .mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL, /* amount of RMT symbols that the channel can store at a time */ + .gpio_num = rx_pin, + }; - DEBUGASSERT(mem_cnt + channel <= SOC_RMT_CHANNELS_PER_GROUP && - mem_cnt > 0); - DEBUGASSERT(clk_div > 0); + rmt_rx_event_callbacks_t cbs = + { + .on_recv_done = rmt_rx_done_callback, + }; - if (mode == RMT_MODE_TX && carrier_en && carrier_freq_hz <= 0) + esp_ret = rmt_new_rx_channel(&rx_channel_cfg, &rx_chan); + if (esp_ret != ESP_OK) { - return -EINVAL; + rmterr("Failed to Initialize RMT RX channel"); + return NULL; } - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - - rmt_ll_enable_mem_access_nonfifo(dev, true); - - if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) + priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); + if (priv) { -#if SOC_RMT_SUPPORT_XTAL - - /* clock src: XTAL_CLK */ - - esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &rmt_source_clk_hz); - ret = esp_clk_tree_enable_src((soc_module_clk_t)RMT_BASECLK_XTAL, - true); - if (ret != ESP_OK) - { - rmterr("Failed to enable XTAL clock source: %d", ret); - return -EPERM; - } - - RMT_CLOCK_SRC_ATOMIC() - { - rmt_ll_set_group_clock_src(dev, channel, - (rmt_clock_source_t)RMT_BASECLK_XTAL, - 1, 0, 0); - } - -#elif SOC_RMT_SUPPORT_REF_TICK - - /* clock src: REF_CLK */ - - esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &rmt_source_clk_hz); - RMT_CLOCK_SRC_ATOMIC() - { - rmt_ll_set_group_clock_src(dev, channel, - (rmt_clock_source_t)RMT_BASECLK_REF, - 1, 0, 0); - } -#else -#error "No clock source is aware of DFS" -#endif + priv->ops = &g_rmtops; + priv->handle = rx_chan; } else { - /* fallback to use default clock source */ - - esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &rmt_source_clk_hz); - ret = esp_clk_tree_enable_src((soc_module_clk_t)RMT_BASECLK_DEFAULT, - true); - if (ret != ESP_OK) - { - rmterr("Failed to enable XTAL clock source: %d", ret); - return -EPERM; - } - - RMT_CLOCK_SRC_ATOMIC() - { - rmt_ll_set_group_clock_src(dev, channel, - (rmt_clock_source_t)RMT_BASECLK_DEFAULT, - 1, 0, 0); - } + rmterr("ERROR: memory allocation failed\n"); + return NULL; } - RMT_CLOCK_SRC_ATOMIC() + esp_ret = rmt_get_channel_id(rx_chan, &channel_id); + if (esp_ret != ESP_OK) { - rmt_ll_enable_group_clock(dev, true); + rmterr("Failed to Get RMT RX channel ID"); + return NULL; } - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + priv->minor = channel_id + RMT_RX_CHANNEL_OFFSET_IN_GROUP; -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT - g_rmt_source_clock_hz[channel] = rmt_source_clk_hz; -#else - if (g_rmt_source_clock_hz && rmt_source_clk_hz != g_rmt_source_clock_hz) + priv->recvsem = kmm_zalloc(sizeof(sem_t)); + if (priv->recvsem == NULL) { - rmterr("RMT clock source has been configured to %"PRIu32" by other " - "channel, now reconfigure it to %"PRIu32"", - g_rmt_source_clock_hz, rmt_source_clk_hz); + rmterr("ERROR: memory allocation failed\n"); + return NULL; } - g_rmt_source_clock_hz = rmt_source_clk_hz; -#endif - rmtinfo("rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz); + nxsem_init(priv->recvsem, 0, 0); - if (mode == RMT_MODE_TX) + priv->circbuf = kmm_zalloc(sizeof(struct circbuf_s)); + if (priv->circbuf == NULL) { - uint16_t carrier_duty_percent = - rmt_param->tx_config.carrier_duty_percent; - uint8_t carrier_level = rmt_param->tx_config.carrier_level; - uint8_t idle_level = rmt_param->tx_config.idle_level; - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div); - rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt); - rmt_ll_tx_reset_pointer(dev, channel); - rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en); -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - if (rmt_param->tx_config.loop_en) - { - rmt_ll_tx_set_loop_count(dev, channel, - rmt_param->tx_config.loop_count); - } -#endif - - /* always enable tx ping-pong */ - - rmt_ll_tx_enable_wrap(dev, channel, true); - - /* Set idle level */ - - rmt_ll_tx_fix_idle_level(dev, channel, idle_level, - rmt_param->tx_config.idle_output_en); - - /* Set carrier */ - - rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en); - if (carrier_en) - { - uint32_t duty_div; - uint32_t duty_h; - uint32_t duty_l; - duty_div = rmt_source_clk_hz / carrier_freq_hz; - duty_h = duty_div * carrier_duty_percent / 100; - duty_l = duty_div - duty_h; - rmt_ll_tx_set_carrier_level(dev, channel, carrier_level); - rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l); - } - else - { - rmt_ll_tx_set_carrier_level(dev, channel, 0); - } - - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - rmtinfo("Rmt Tx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Carrier_Hz" - " %"PRIu32"|Duty %u", channel, gpio_num, rmt_source_clk_hz, - clk_div, carrier_freq_hz, carrier_duty_percent); - } - else if (RMT_MODE_RX == mode) - { - uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh; - uint16_t threshold = rmt_param->rx_config.idle_threshold; - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), - clk_div); - rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt); - rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel)); - rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), - RMT_LL_MEM_OWNER_HW); - - /* Set idle threshold */ - - rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), - threshold); - - /* Set RX filter */ - - rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), - filter_cnt); - rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), - rmt_param->rx_config.filter_en); - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - - /* always enable rx ping-pong */ - - rmt_ll_rx_enable_wrap(dev, RMT_DECODE_RX_CHANNEL(channel), true); -#endif - -#if SOC_RMT_SUPPORT_RX_DEMODULATION - rmt_ll_rx_enable_carrier_demodulation(dev, - RMT_DECODE_RX_CHANNEL(channel), - rmt_param->rx_config.rm_carrier); - if (rmt_param->rx_config.rm_carrier) - { - uint32_t duty_total; - uint32_t duty_high; - uint32_t ch_clk_div = - rmt_ll_rx_get_channel_clock_div(dev, - RMT_DECODE_RX_CHANNEL(channel)); - duty_total = rmt_source_clk_hz / \ - ch_clk_div / \ - rmt_param->rx_config.carrier_freq_hz; - duty_high = duty_total * - rmt_param->rx_config.carrier_duty_percent / 100; - - /* there could be residual in timing the carrier pulse, so double - * enlarge the theoretical value. - */ - - rmt_ll_rx_set_carrier_high_low_ticks( - dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, - (duty_total - duty_high) * 2); - rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), - rmt_param->rx_config.carrier_level); - } -#endif - - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Threshold " - "%u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, - threshold, filter_cnt); - } - - return ret; -} - -/**************************************************************************** - * Name: rmt_config - * - * Description: - * This function configures the RMT channel with the provided parameters. - * It enables the RMT module, sets the GPIO for the RMT channel, and - * configures the RMT peripheral using the internal configuration function. - * - * Input Parameters: - * rmt_param - Pointer to the structure containing the RMT channel - * configuration parameters. - * - * Returned Value: - * Returns OK on successful configuration of the RMT channel; a negated - * errno value is returned on any failure. - * - ****************************************************************************/ - -static int rmt_config(const struct rmt_channel_config_s *rmt_param) -{ - int ret = ERROR; - - rmt_module_enable(); - - rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, - rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG); - - ret = rmt_internal_config(&RMT, rmt_param); - - return ret; -} - -/**************************************************************************** - * Name: rmt_fill_memory - * - * Description: - * This function fills the RMT memory with the provided items. It copies - * the items from the source to the RMT memory for the specified channel, - * starting at the specified memory offset. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * item - Pointer to the items to be copied to the RMT memory. - * item_num - The number of items to be copied. - * mem_offset - The memory offset at which to start copying. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, - const rmt_item32_t *item, - uint16_t item_num, - uint16_t mem_offset) -{ - uint32_t *from = (uint32_t *)item; - volatile uint32_t *to = - (volatile uint32_t *)&RMTMEM.chan[channel].data32[0].val; - - to += mem_offset; - - while (item_num--) - { - *to++ = *from++; - } -} - -/**************************************************************************** - * Name: rmt_isr_register - * - * Description: - * This function registers an interrupt service routine (ISR) for the RMT - * peripheral. It allocates a CPU interrupt, attaches the ISR to the - * interrupt, and returns the status of the operation. - * - * Input Parameters: - * fn - Pointer to the ISR function. - * arg - Pointer to the argument to be passed to the ISR. - * intr_alloc_flags - Flags for the interrupt allocation. - * - * Returned Value: - * Returns OK on successful registration of the ISR; a negated errno value - * is returned on any failure. - * - ****************************************************************************/ - -static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg, - int intr_alloc_flags) -{ - int cpuint; - int ret; - int cpu = this_cpu(); - - DEBUGASSERT(fn); - DEBUGASSERT(g_rmtdev_common.rmt_driver_channels == 0); - - cpuint = esp_setup_irq(rmt_periph_signals.groups[0].irq, - ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); - if (cpuint < 0) - { - rmterr("Failed to allocate a CPU interrupt.\n"); - return -ENOMEM; - } - - ret = irq_attach(ESP_SOURCE2IRQ(rmt_periph_signals.groups[0].irq), - fn, &g_rmtdev_common.hal); - if (ret < 0) - { - rmterr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(rmt_periph_signals.groups[0].irq, cpuint); - return ret; - } - - up_enable_irq(ESP_SOURCE2IRQ(rmt_periph_signals.groups[0].irq)); - - return ret; -} - -/**************************************************************************** - * Name: rmt_driver_isr_default - * - * Description: - * This function is the default interrupt service routine (ISR) for the RMT - * peripheral. It handles TX end, TX threshold, RX end, RX threshold, loop - * count, RX error, and TX error interrupts. For each interrupt type, it - * checks the status, clears the interrupt, and performs the appropriate - * actions based on the RMT object associated with the channel. - * - * Input Parameters: - * irq - The interrupt request number. - * context - Pointer to the interrupt context. - * arg - Pointer to the argument to be passed to the ISR. - * - * Returned Value: - * Returns OK after handling all active interrupts. - * - ****************************************************************************/ - -static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context, - void *arg) -{ - uint32_t status = 0; - rmt_item32_t *addr = NULL; - uint8_t channel = 0; - rmt_hal_context_t *hal = (rmt_hal_context_t *)arg; - - /* Tx end interrupt */ - - status = rmt_ll_get_tx_end_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - nxsem_post(&p_rmt->tx_sem); - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); - p_rmt->tx_data = NULL; - p_rmt->tx_len_rem = 0; - p_rmt->tx_offset = 0; - p_rmt->tx_sub_len = 0; - p_rmt->sample_cur = NULL; - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_DONE(channel)); - } - - /* Tx thres interrupt */ - - status = rmt_ll_get_tx_thres_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - const rmt_item32_t *pdata = p_rmt->tx_data; - size_t len_rem = p_rmt->tx_len_rem; - rmt_idle_level_t idle_level = - rmt_ll_tx_get_idle_level(hal->regs, channel); - rmt_item32_t stop_data = (rmt_item32_t) - { - .level0 = idle_level, - .duration0 = 0, - }; - - if (len_rem >= p_rmt->tx_sub_len) - { - rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, - p_rmt->tx_offset); - p_rmt->tx_data += p_rmt->tx_sub_len; - p_rmt->tx_len_rem -= p_rmt->tx_sub_len; - } - else if (len_rem == 0) - { - rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_offset); - } - else - { - rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset); - rmt_fill_memory(channel, &stop_data, 1, - p_rmt->tx_offset + len_rem); - p_rmt->tx_data += len_rem; - p_rmt->tx_len_rem -= len_rem; - } - - if (p_rmt->tx_offset == 0) - { - p_rmt->tx_offset = p_rmt->tx_sub_len; - } - else - { - p_rmt->tx_offset = 0; - } - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_THRES(channel)); - } - - /* Rx end interrupt */ - - status = rmt_ll_get_rx_end_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; - if (p_rmt) - { - int item_len; - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, false); - item_len = - rmt_ll_rx_get_memory_writer_offset(g_rmtdev_common.hal.regs, - channel); - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_SW); - if (circbuf_is_init(&p_rmt->rx_buf)) - { - int bytes; - - addr = (rmt_item32_t *) - RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32; -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - if (item_len > p_rmt->rx_item_start_idx) - { - item_len = item_len - p_rmt->rx_item_start_idx; - } - else - { - item_len = p_rmt->rx_item_start_idx - item_len; - } - - /* Check for RX buffer max length */ - - if ((p_rmt->rx_item_len + item_len) > \ - (p_rmt->rx_item_buf_size / 4)) - { - int remaining_len = (p_rmt->rx_item_buf_size / 4) - \ - p_rmt->rx_item_len; - rmterr("ERROR: RX buffer too small: %d items dropped\n", - item_len - remaining_len); - item_len = remaining_len; - } - - memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), - (void *)(addr + p_rmt->rx_item_start_idx), - item_len * 4); - p_rmt->rx_item_len += item_len; - bytes = circbuf_write(&p_rmt->rx_buf, - (void *)(p_rmt->rx_item_buf), - p_rmt->rx_item_len * 4); -#else - bytes = circbuf_write(&p_rmt->rx_buf, (void *)addr, - item_len * 4); -#endif - nxsem_post(&p_rmt->rx_sem); - if (bytes < (item_len * 4)) - { - rmterr("RMT RX BUFFER FULL"); - } - } - else - { - rmterr("RMT RX BUFFER ERROR"); - } - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - p_rmt->rx_item_start_idx = 0; - p_rmt->rx_item_len = 0; - memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size); -#endif - rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel); - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_HW); - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, true); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_RX_DONE(channel)); - } - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - - /* Rx thres interrupt */ - - status = rmt_ll_get_rx_thres_interrupt_status(hal->regs); - while (status) - { - int mem_item_size; - int rx_thres_lim; - int item_len; - - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; - mem_item_size = rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, - channel) * RMT_MEM_ITEM_NUM; - rx_thres_lim = rmt_ll_rx_get_limit(g_rmtdev_common.hal.regs, channel); - item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : \ - (mem_item_size - rx_thres_lim); - if ((p_rmt->rx_item_len + item_len) > (p_rmt->rx_item_buf_size / 4)) - { - int remaining_len = (p_rmt->rx_item_buf_size / 4) - \ - p_rmt->rx_item_len; - rmterr("ERROR: RX buffer too small!\n"); - item_len = remaining_len; - } - - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_SW); - memcpy( - (void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), - (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 \ - + p_rmt->rx_item_start_idx), item_len * 4); - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_HW); - p_rmt->rx_item_len += item_len; - p_rmt->rx_item_start_idx += item_len; - if (p_rmt->rx_item_start_idx >= mem_item_size) - { - p_rmt->rx_item_start_idx = 0; - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_RX_THRES(channel)); - } -#endif - -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - - /* loop count interrupt */ - - status = rmt_ll_get_tx_loop_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - if (p_rmt->loop_autostop) - { -#ifndef SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP - - /* hardware doesn't support automatically stop output so driver - * should stop output here (possibility already overshotted - * several us). - */ - - rmt_ll_tx_stop(g_rmtdev_common.hal.regs, channel); - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); -#endif - } - - nxsem_post(&p_rmt->tx_sem); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_LOOP_END(channel)); - } -#endif - - /* RX Err interrupt */ - - status = rmt_ll_get_rx_err_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; - if (p_rmt) - { - /* Reset the receiver's write/read addresses to prevent endless - * err interrupts. - */ - - rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel); - rmtinfo("RMT RX channel %d error", channel); - rmtinfo("status: 0x%08lx", - rmt_ll_rx_get_status_word(g_rmtdev_common.hal.regs, - channel)); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_RX_ERROR(channel)); - } - - /* TX Err interrupt */ - - status = rmt_ll_get_tx_err_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - /* Reset the transmitter's write/read addresses to prevent - * endless err interrupts. - */ - - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); - rmtinfo("RMT TX channel %d error", channel); - rmtinfo("status: 0x%08lx", - rmt_ll_tx_get_status_word(g_rmtdev_common.hal.regs, - channel)); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_ERROR(channel)); - } - - return OK; -} - -/**************************************************************************** - * Name: rmt_driver_install - * - * Description: - * This function installs the RMT driver for a specific channel. It - * allocates memory for the RMT object, initializes the object properties, - * and sets up the RX buffer if specified. It also registers the default - * ISR if this is the first RMT channel using the driver, and resets the - * RMT channel. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * rx_buf_size - The size of the RX buffer. - * intr_alloc_flags - Flags for the interrupt allocation. - * - * Returned Value: - * Returns OK on successful installation of the RMT driver; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, - int intr_alloc_flags) -{ - DEBUGASSERT(channel < RMT_CHANNEL_MAX); - - int ret = OK; - - if (p_rmt_obj[channel]) - { - rmtwarn("RMT driver already installed"); - return ERROR; - } - -#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH - if (intr_alloc_flags & ESP_INTR_FLAG_IRAM) - { - rmterr("ringbuf ISR functions in flash, but used in IRAM interrupt"); - return -EINVAL; - } -#endif - -#ifndef CONFIG_SPIRAM_USE_MALLOC - p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); -#else - if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) - { - p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t)); - } - else - { - p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); - } -#endif - - if (p_rmt_obj[channel] == NULL) - { - rmterr("RMT driver malloc error"); - return -ENOMEM; - } - - p_rmt_obj[channel]->tx_len_rem = 0; - p_rmt_obj[channel]->tx_data = NULL; - p_rmt_obj[channel]->channel = channel; - p_rmt_obj[channel]->tx_offset = 0; - p_rmt_obj[channel]->tx_sub_len = 0; - p_rmt_obj[channel]->wait_done = false; - p_rmt_obj[channel]->loop_autostop = false; - -#ifndef CONFIG_SPIRAM_USE_MALLOC - nxsem_init(&p_rmt_obj[channel]->tx_sem, 0, 0); - nxsem_init(&p_rmt_obj[channel]->rx_sem, 0, 0); -#endif - - nxsem_post(&p_rmt_obj[channel]->tx_sem); - - if (!circbuf_is_init(&p_rmt_obj[channel]->rx_buf) && rx_buf_size > 0) - { - circbuf_init(&p_rmt_obj[channel]->rx_buf, NULL, rx_buf_size); - } - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) - { -# ifndef CONFIG_SPIRAM_USE_MALLOC - p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); -# else - if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) - { - p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size); - } - else - { - p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); - } - -# endif - if (p_rmt_obj[channel]->rx_item_buf == NULL) - { - rmterr("RMT malloc fail"); - nxsem_destroy(&p_rmt_obj[channel]->rx_sem); - return -ENOMEM; - } - - p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size; - } -#endif - - nxrmutex_lock(&(g_rmtdev_common.rmt_driver_isr_lock)); - - if (g_rmtdev_common.rmt_driver_channels == 0) - { - /* first RMT channel using driver */ - - ret = rmt_isr_register(rmt_driver_isr_default, &g_rmtdev_common.hal, - intr_alloc_flags); - } - - if (ret == OK) - { - g_rmtdev_common.rmt_driver_channels |= BIT(channel); - } - - nxrmutex_unlock(&(g_rmtdev_common.rmt_driver_isr_lock)); - - rmt_module_enable(); - - if (RMT_IS_RX_CHANNEL(channel)) - { - rmt_hal_rx_channel_reset(&g_rmtdev_common.hal, - RMT_DECODE_RX_CHANNEL(channel)); - } - else - { - rmt_hal_tx_channel_reset(&g_rmtdev_common.hal, channel); - } - - return OK; -} - -/**************************************************************************** - * Name: rmt_write_items - * - * Description: - * This function writes items to the RMT memory for a specific channel. It - * checks the validity of the parameters, calculates the memory blocks and - * item lengths, and fills the memory with the items. If the number of - * items is greater than the memory block length, it enables the TX - * threshold interrupt and sets up the remaining items to be sent. If the - * number of items is less than the memory block length, it fills the - * remaining memory with idle level items. It then starts the TX process - * and waits for it to finish if specified. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * rmt_item - Pointer to the items to be written to the RMT memory. - * item_num - The number of items to be written. - * wait_tx_done - Flag to indicate whether to wait for the TX process to - * finish. - * - * Returned Value: - * Returns OK on successful writing of the items to the RMT memory; a - * negated errno value is returned on any failure. - * - ****************************************************************************/ - -static int rmt_write_items(rmt_channel_t channel, - const rmt_item32_t *rmt_item, - int item_num, - bool wait_tx_done) -{ - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); - DEBUGASSERT(p_rmt_obj[channel]); - DEBUGASSERT(rmt_item); - DEBUGASSERT(item_num > 0); - - uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, - channel); - - DEBUGASSERT(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP); -#ifdef CONFIG_SPIRAM_USE_MALLOC - if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) - { - if (!esp_ptr_internal(rmt_item)) - { - rmterr(RMT_PSRAM_BUFFER_WARN_STR); - return ESP_ERR_INVALID_ARG; - } - } -#endif - - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - int item_block_len = mem_blocks * RMT_MEM_ITEM_NUM; - int item_sub_len = mem_blocks * RMT_MEM_ITEM_NUM / 2; - int len_rem = item_num; - nxsem_wait(&p_rmt->tx_sem); - - /* fill the memory block first */ - - if (item_num >= item_block_len) - { - rmt_fill_memory(channel, rmt_item, item_block_len, 0); - len_rem -= item_block_len; - rmt_set_tx_loop_mode(channel, false); - rmt_set_tx_thr_intr_en(channel, 1, item_sub_len); - p_rmt->tx_data = rmt_item + item_block_len; - p_rmt->tx_len_rem = len_rem; - p_rmt->tx_offset = 0; - p_rmt->tx_sub_len = item_sub_len; - } - else - { - rmt_idle_level_t idle_level; - rmt_fill_memory(channel, rmt_item, len_rem, 0); - idle_level = rmt_ll_tx_get_idle_level(g_rmtdev_common.hal.regs, - channel); - rmt_item32_t stop_data = (rmt_item32_t) - { - .level0 = idle_level, - .duration0 = 0, - }; - - rmt_fill_memory(channel, &stop_data, 1, len_rem); - p_rmt->tx_len_rem = 0; - } - - rmt_tx_start(channel, true); - p_rmt->wait_done = wait_tx_done; - if (wait_tx_done) - { - /* wait loop done */ - - if (rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) - { -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - nxsem_wait(&p_rmt->tx_sem); - nxsem_post(&p_rmt->tx_sem); -#endif - } - else - { - /* wait tx end */ - - nxsem_wait(&p_rmt->tx_sem); - nxsem_post(&p_rmt->tx_sem); - } - } - - return OK; -} - -/**************************************************************************** - * Name: esp_rmt_read - * - * Description: - * This function reads data from the RMT device. - * It starts the RMT module in receiving mode for a specific channel and - * checks for any errors. If an error occurs during the start of the RMT - * module, it returns the error code. Please note that this function - * starts the receiver, but the actual data is read from the ring buffer - * by the upper half driver. - * - * Input Parameters: - * dev - Pointer to the RMT device structure. - * buffer - Pointer to the buffer where the read data should be stored. - * buflen - The maximum amount of data to be read. - * - * Returned Value: - * Returns the number of bytes read from the RMT device; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, - size_t buflen) -{ - struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; - rmt_mode_t mode = priv->mode; - int channel = priv->minor; - int ret; - ssize_t nread; - - if (mode != RMT_MODE_RX) - { - rmterr("ERROR: RMT channel %d is not in RX mode\n", channel); - return -EINVAL; - } - - DEBUGASSERT((buflen % 4) == 0); - - if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4)) - { - rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested " - "read bytes (%d bytes). A partial read will take place!\n", - CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE, - buflen); - } - -#ifndef SOC_RMT_SUPPORT_RX_PINGPONG - if ((buflen / 4) > RMT_MEM_ITEM_NUM) - { - rmtwarn("WARN: RMT RX channel is able to receive up to " - "%d RMT items (%d bytes)!", - RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4); + rmterr("ERROR: memory allocation failed\n"); + return NULL; } -#endif - ret = rmt_rx_start(channel, true); - if (ret < 0) + ret = circbuf_init(priv->circbuf, NULL, + CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE); + if (ret != OK) { - rmterr("ERROR: rmt_rx_start failed: %d\n", ret); - return (ssize_t)ret; - } - - return (ssize_t)ret; -} - -/**************************************************************************** - * Name: esp_rmt_write - * - * Description: - * This function writes data to the RMT memory for a specific channel. It - * asserts that the length of the data is a multiple of 4, then calls the - * rmt_write_items function to write the items to the RMT memory. - * - * Input Parameters: - * dev - Pointer to the RMT device structure. - * buffer - Pointer to the data to be written to the RMT memory. - * buflen - The length of the data to be written. - * - * Returned Value: - * Returns the number of items written to the RMT memory. - * - ****************************************************************************/ - -static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, - size_t buflen) -{ - struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; - rmt_mode_t mode = priv->mode; - int channel = priv->minor; - int ret; - struct timespec timeout; - - if (mode != RMT_MODE_TX) - { - rmterr("ERROR: RMT channel %d is not in TX mode\n", channel); - return -EINVAL; + rmterr("Failed to Initialize RMT RX buffer"); + return NULL; } - DEBUGASSERT((buflen % 4) == 0); - - ret = rmt_write_items(channel, (const rmt_item32_t *)buffer, - (buflen / 4), true); - - if (ret < 0) + esp_ret = rmt_rx_register_event_callbacks(rx_chan, &cbs, priv); + if (esp_ret != ESP_OK) { - rmterr("ERROR: rmt_write_items failed: %d\n", ret); - return (ssize_t)0; + rmterr("Failed to Register RMT RX event callbacks"); + return NULL; } - return (ssize_t)buflen; -} - -/**************************************************************************** - * Name: esp_rmtinitialize - * - * Description: - * This function initializes the specified RMT (Remote Control) device - * with the provided configuration. - * - * Input Parameters: - * config - A structure containing the configuration settings for the - * RMT channel to be initialized. - * - * Returned Value: - * On success, this function returns a valid pointer to the RMT device - * structure. If the initialization fails, it returns NULL. - * - ****************************************************************************/ - -static struct rmt_dev_s - *esp_rmtinitialize(struct rmt_channel_config_s config) -{ - struct rmt_dev_lowerhalf_s *priv; - int ret; -#ifdef CONFIG_RMT_LOOP_TEST_MODE - uint8_t channel; -#endif - -#if (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE % 4) != 0 -# error "CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE must be a multiple of 4" -#endif - - priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); - if (priv) - { - ret = rmt_config(&config); - if (ret < 0) - { - rmterr("ERROR: rmt_config failed: %d\n", ret); - return NULL; - } - -#ifdef CONFIG_RMT_LOOP_TEST_MODE - if (config.rmt_mode == RMT_MODE_TX) - { - if (g_tx_channel != RMT_CHANNEL_MAX) - { - rmterr("ERROR: only one TX channel can be used in loop test " - "mode\n"); - PANIC(); - } - - g_tx_channel = config.channel; - } - else - { - if (g_rx_channel != RMT_CHANNEL_MAX) - { - rmterr("ERROR: only one RX channel can be used in loop test " - "mode\n"); - PANIC(); - } - - g_rx_channel = config.channel; - } - - if (g_rx_channel != RMT_CHANNEL_MAX && g_tx_channel != RMT_CHANNEL_MAX) - { - uint32_t tx_sig = - rmt_periph_signals.groups[0].channels[g_tx_channel].tx_sig; - uint32_t rx_sig = - rmt_periph_signals.groups[0].channels[g_rx_channel].rx_sig; - esp_configgpio(config.gpio_num, OUTPUT | INPUT); - esp_gpio_matrix_out(config.gpio_num, - tx_sig, - 0, 0); - esp_gpio_matrix_in(config.gpio_num, - rx_sig, - 0); - rmtwarn("RX channel %d and TX channel %d are used in loop test " - "mode\n", g_rx_channel, g_tx_channel); - } -#endif - - ret = rmt_driver_install(config.channel, - config.rmt_mode == RMT_MODE_RX ? \ - CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE : 0, 0); - if (ret < 0) - { - rmterr("ERROR: rmt_driver_install failed: %d\n", ret); - return NULL; - } - - priv->ops = &g_rmtops; - priv->recvsem = &p_rmt_obj[config.channel]->rx_sem; - priv->circbuf = &p_rmt_obj[config.channel]->rx_buf; - priv->minor = config.channel; - - priv->common = &g_rmtdev_common; - priv->mode = config.rmt_mode; - } - else + esp_ret = rmt_enable(rx_chan); + if (esp_ret != ESP_OK) { - rmterr("ERROR: memory allocation failed\n"); + rmterr("Failed to Enable RMT RX channel"); return NULL; } return (struct rmt_dev_s *)priv; } -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_rmt_tx_init - * - * Description: - * Initialize the selected RMT device in TX mode - * - * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the TX channel - * - * Returned Value: - * Valid RMT device structure reference on success; NULL, otherwise. - * - ****************************************************************************/ - -struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin) -{ - struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_TX(pin, ch); - - return esp_rmtinitialize(config); -} - -/**************************************************************************** - * Name: esp_rmt_rx_init - * - * Description: - * Initialize the selected RMT device in RC mode - * - * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the RX channel - * - * Returned Value: - * Valid RMT device structure reference on success; NULL, otherwise. - * - ****************************************************************************/ - -struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin) -{ - struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_RX(pin, ch); - - return esp_rmtinitialize(config); -} - #endif diff --git a/arch/risc-v/src/common/espressif/esp_rmt.h b/arch/risc-v/src/common/espressif/esp_rmt.h index fe163f99300c5..2956db80b4bf2 100644 --- a/arch/risc-v/src/common/espressif/esp_rmt.h +++ b/arch/risc-v/src/common/espressif/esp_rmt.h @@ -68,38 +68,36 @@ extern "C" #if defined(CONFIG_ESP_RMT) /**************************************************************************** - * Name: esp_rmt_tx_init + * Name: esp_rmt_rx_init * * Description: * Initialize the selected RMT device in TX mode * * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the TX channel + * tx_pin - The pin used for the TX channel * * Returned Value: * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin); +struct rmt_dev_s *esp_rmt_rx_init(int tx_pin); /**************************************************************************** - * Name: esp_rmt_rx_init + * Name: esp_rmt_tx_init * * Description: - * Initialize the selected RMT device in RC mode + * Initialize the selected RMT device in RX mode * * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the RX channel + * rx_pin - The pin used for the RX channel * * Returned Value: * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin); +struct rmt_dev_s *esp_rmt_tx_init(int rx_pin); #endif diff --git a/arch/risc-v/src/common/espressif/esp_rtc.c b/arch/risc-v/src/common/espressif/esp_rtc.c index 4e55697159f87..7c472aca5425f 100644 --- a/arch/risc-v/src/common/espressif/esp_rtc.c +++ b/arch/risc-v/src/common/espressif/esp_rtc.c @@ -47,15 +47,7 @@ #include "esp_attr.h" #include "soc/rtc.h" -/* Chip-dependent headers from esp-hal-3rdparty */ - -#ifdef CONFIG_ARCH_CHIP_ESP32C3 -#include "esp32c3/rom/rtc.h" -#elif defined(CONFIG_ARCH_CHIP_ESP32C6) -#include "esp32c6/rom/rtc.h" -#elif defined(CONFIG_ARCH_CHIP_ESP32H2) -#include "esp32h2/rom/rtc.h" -#endif +#include "rom/rtc.h" /**************************************************************************** * Pre-processor Definitions @@ -848,6 +840,91 @@ int up_rtc_initialize(void) return OK; } +/**************************************************************************** + * Name: esp_set_time_from_rtc + * + * Description: + * Update the offset between RTC timer and HR-Timer after light sleep + * wake-up. This function is called by the ESP-HAL sleep_modes.c after + * waking from light sleep to resynchronize the timers. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_ESPRESSIF_HR_TIMER) +void esp_set_time_from_rtc(void) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock); + + if (g_hr_timer_enabled) + { + /* Update offset between RTC and HR Timer */ + + g_rtc_save->offset = esp_rtc_get_time_us() - esp_hr_timer_time_us(); + } + + spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags); +} +#endif /* CONFIG_RTC_DRIVER && CONFIG_ESPRESSIF_HR_TIMER */ + +/**************************************************************************** + * Name: esp_sync_timekeeping_timers + * + * Description: + * Synchronize the RTC timer and HR-Timer by recalculating and adjusting + * the offset between them. This function can be called periodically to + * compensate for any drift between the two time sources. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_ESPRESSIF_HR_TIMER) +void esp_sync_timekeeping_timers(void) +{ + irqstate_t flags; + int64_t new_offset; + int64_t drift; + + flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock); + + if (g_hr_timer_enabled) + { + /* Recalculate the offset between RTC and HR Timer */ + + new_offset = esp_rtc_get_time_us() - esp_hr_timer_time_us(); + + /* Calculate the drift between the old and new offset */ + + drift = g_rtc_save->offset - new_offset; + + /* Adjust the boot time to compensate for the drift. + * This ensures that the absolute time remains consistent + * across both time sources. + */ + + esp_rtc_set_boot_time(esp_rtc_get_boot_time() + drift); + + /* Update the offset with the new value */ + + g_rtc_save->offset = new_offset; + } + + spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags); +} +#endif /* CONFIG_RTC_DRIVER && CONFIG_ESPRESSIF_HR_TIMER */ + /**************************************************************************** * Name: esp_rtc_driverinit * diff --git a/arch/risc-v/src/common/espressif/esp_rtc.h b/arch/risc-v/src/common/espressif/esp_rtc.h index c7bf0bf5cc344..f08b273501a9a 100644 --- a/arch/risc-v/src/common/espressif/esp_rtc.h +++ b/arch/risc-v/src/common/espressif/esp_rtc.h @@ -33,6 +33,52 @@ * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: esp_set_time_from_rtc + * + * Description: + * Update the offset between RTC timer and HR-Timer after light sleep + * wake-up. This function is called by the ESP-HAL sleep_modes.c after + * waking from light sleep to resynchronize the timers. + * + * Note: This function is only available when both CONFIG_RTC_DRIVER and + * CONFIG_ESPRESSIF_HR_TIMER are enabled. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_ESPRESSIF_HR_TIMER) +void esp_set_time_from_rtc(void); +#endif + +/**************************************************************************** + * Name: esp_sync_timekeeping_timers + * + * Description: + * Synchronize the RTC timer and HR-Timer by recalculating and adjusting + * the offset between them. This function can be called periodically to + * compensate for any drift between the two time sources. + * + * Note: This function is only available when both CONFIG_RTC_DRIVER and + * CONFIG_ESPRESSIF_HR_TIMER are enabled. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_ESPRESSIF_HR_TIMER) +void esp_sync_timekeeping_timers(void); +#endif + /**************************************************************************** * Name: esp_rtc_driverinit * diff --git a/arch/risc-v/src/common/espressif/esp_rtc_gpio.c b/arch/risc-v/src/common/espressif/esp_rtc_gpio.c index 59ba8a421a756..53d613cab104a 100644 --- a/arch/risc-v/src/common/espressif/esp_rtc_gpio.c +++ b/arch/risc-v/src/common/espressif/esp_rtc_gpio.c @@ -39,7 +39,7 @@ #include "riscv_internal.h" #include "esp_irq.h" #include "esp_rtc_gpio.h" -#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_periph.h" #include "hal/rtc_io_hal.h" #include "soc/rtc_cntl_periph.h" #include "soc/periph_defs.h" @@ -54,6 +54,18 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Structure to store RTC GPIO interrupt handlers */ + +struct rtcio_handler_s +{ + xcpt_t handler; /* User interrupt handler */ + void *arg; /* Argument for handler */ +}; + /**************************************************************************** * Private Data ****************************************************************************/ @@ -62,8 +74,8 @@ #ifdef CONFIG_ESPRESSIF_RTCIO_IRQ static int g_rtcio_cpuint; static uint32_t last_status; +static struct rtcio_handler_s g_rtcio_handlers[ESP_NIRQ_RTCIO]; -#ifdef CONFIG_ARCH_CHIP_ESP32C3 static const int rtc_irq_reg_shift[ESP_NIRQ_RTCIO] = { RTC_CNTL_SLP_WAKEUP_INT_ENA_S, @@ -77,7 +89,6 @@ static const int rtc_irq_reg_shift[ESP_NIRQ_RTCIO] = RTC_CNTL_BBPLL_CAL_INT_ENA_S }; #define RTC_IRQ_REG_SHIFT(x) rtc_irq_reg_shift[x] -#endif /* CONFIG_ARCH_CHIP_ESP32C3 */ #endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */ /**************************************************************************** @@ -100,7 +111,7 @@ static const int rtc_irq_reg_shift[ESP_NIRQ_RTCIO] = ****************************************************************************/ #ifdef CONFIG_ESPRESSIF_RTCIO_IRQ -static void rtcio_dispatch(int irq, uint32_t *reg_status) +static void rtcio_dispatch(int irq, void *context, uint32_t *reg_status) { uint32_t status = *reg_status; uint32_t mask; @@ -115,11 +126,14 @@ static void rtcio_dispatch(int irq, uint32_t *reg_status) mask = (UINT32_C(1) << RTC_IRQ_REG_SHIFT(i)); if ((status & mask) != 0) { - /* Yes... perform the second level dispatch. The IRQ context will - * contain the contents of the status register. - */ + /* Call the registered handler if one exists */ - irq_dispatch(irq + i, (void *)reg_status); + if (g_rtcio_handlers[i].handler != NULL) + { + g_rtcio_handlers[i].handler(irq, + (void *)reg_status, + g_rtcio_handlers[i].arg); + } /* Clear the bit in the status so that we might execute this loop * sooner. @@ -155,7 +169,7 @@ static int rtcio_interrupt(int irq, void *context, void *arg) /* Dispatch pending interrupts in the RTC status register */ - rtcio_dispatch(ESP_FIRST_RTCIOIRQ, &last_status); + rtcio_dispatch(ESP_FIRST_RTCIOIRQ, context, &last_status); return OK; } @@ -183,18 +197,102 @@ static int rtcio_interrupt(int irq, void *context, void *arg) #ifdef CONFIG_ESPRESSIF_RTCIO_IRQ void esp_rtcioirqinitialize(void) { + int i; + + /* Initialize handler array */ + + for (i = 0; i < ESP_NIRQ_RTCIO; i++) + { + g_rtcio_handlers[i].handler = NULL; + g_rtcio_handlers[i].arg = NULL; + } + /* Setup the RTCIO interrupt. */ g_rtcio_cpuint = esp_setup_irq(ETS_RTC_CORE_INTR_SOURCE, - 1, ESP_IRQ_TRIGGER_LEVEL); + 1, ESP_IRQ_TRIGGER_LEVEL, + rtcio_interrupt, NULL); DEBUGASSERT(g_rtcio_cpuint >= 0); - /* Attach and enable the interrupt handler */ + /* Enable the interrupt handler */ - DEBUGVERIFY(irq_attach(ESP_IRQ_RTC_CORE, rtcio_interrupt, NULL)); up_enable_irq(ESP_IRQ_RTC_CORE); } +/**************************************************************************** + * Name: esp_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp_rtcioirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP_FIRST_RTCIOIRQ && + irq <= ESP_LAST_RTCIOIRQ); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP_FIRST_RTCIOIRQ; + + DEBUGASSERT(bit >= 0 && bit < ESP_NIRQ_RTCIO); + + /* Store the handler and argument */ + + g_rtcio_handlers[bit].handler = handler; + g_rtcio_handlers[bit].arg = arg; + + return OK; +} + +/**************************************************************************** + * Name: esp_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp_rtcioirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP_FIRST_RTCIOIRQ && + irq <= ESP_LAST_RTCIOIRQ); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP_FIRST_RTCIOIRQ; + + DEBUGASSERT(bit >= 0 && bit < ESP_NIRQ_RTCIO); + + /* Clear the handler and argument */ + + g_rtcio_handlers[bit].handler = NULL; + g_rtcio_handlers[bit].arg = NULL; + + return OK; +} + /**************************************************************************** * Name: esp_rtcioirqenable * @@ -271,7 +369,6 @@ void esp_rtcioirqdisable(int irq) #endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */ #endif /* CONFIG_ARCH_CHIP_ESP32C3 */ -#ifdef CONFIG_ARCH_CHIP_ESP32C6 /**************************************************************************** * Name: esp_rtcio_config_gpio * @@ -287,6 +384,7 @@ void esp_rtcioirqdisable(int irq) * ****************************************************************************/ +#ifdef CONFIG_ARCH_CHIP_ESP32C6 int esp_rtcio_config_gpio(int pin, enum esp_rtc_gpio_mode_e mode) { int ret = rtc_gpio_init(pin); diff --git a/arch/risc-v/src/common/espressif/esp_rtc_gpio.h b/arch/risc-v/src/common/espressif/esp_rtc_gpio.h index 52837e9dcebb6..1ca6f732726a9 100644 --- a/arch/risc-v/src/common/espressif/esp_rtc_gpio.h +++ b/arch/risc-v/src/common/espressif/esp_rtc_gpio.h @@ -75,12 +75,56 @@ typedef enum esp_rtc_gpio_mode_e * ****************************************************************************/ -#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +#if defined(CONFIG_ESPRESSIF_RTCIO_IRQ) && defined(CONFIG_ARCH_CHIP_ESP32C3) void esp_rtcioirqinitialize(void); #else # define esp_rtcioirqinitialize() #endif +/**************************************************************************** + * Name: esp_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +int esp_rtcioirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp_rtcioirqattach(irq, handler, arg) (-ENOSYS) +#endif + +/**************************************************************************** + * Name: esp_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +int esp_rtcioirqdetach(int irq); +#else +# define esp_rtcioirqdetach(irq) (-ENOSYS) +#endif + /**************************************************************************** * Name: esp_rtcioirqenable * diff --git a/arch/risc-v/src/common/espressif/esp_sdm.c b/arch/risc-v/src/common/espressif/esp_sdm.c index 931307dcf1529..ee725a9af0dd8 100644 --- a/arch/risc-v/src/common/espressif/esp_sdm.c +++ b/arch/risc-v/src/common/espressif/esp_sdm.c @@ -44,10 +44,9 @@ #include "esp_clk_tree.h" #include "hal/sdm_hal.h" #include "hal/sdm_ll.h" -#include "soc/sdm_periph.h" -#if defined(CONFIG_ARCH_CHIP_ESP32C6) || defined(CONFIG_ARCH_CHIP_ESP32H2) +#include "hal/sdm_periph.h" +#include "hal/sdm_caps.h" #include "hal/gpio_ll.h" -#endif /**************************************************************************** * Pre-processor Definitions @@ -69,18 +68,18 @@ struct esp_sdm_channel_priv_s struct esp_sdm_group_priv_s { - int group_id; /* Group ID, index from 0 */ - spinlock_t spinlock; /* Spinlock for protecting concurrent operations */ - sdm_hal_context_t hal; /* Common layer context */ - soc_periph_sdm_clk_src_t clk_src; /* Clock source */ - struct esp_sdm_channel_priv_s *channels[SOC_SDM_CHANNELS_PER_GROUP]; /* Array of SDM channels */ + int group_id; /* Group ID, index from 0 */ + spinlock_t spinlock; /* Spinlock for protecting concurrent operations */ + sdm_hal_context_t hal; /* Common layer context */ + soc_periph_sdm_clk_src_t clk_src; /* Clock source */ + struct esp_sdm_channel_priv_s *channels[SDM_CAPS_GET(CHANS_PER_INST)]; /* Array of SDM channels */ }; struct esp_sdm_priv_s { - rmutex_t lock; /* Lock for protecting concurrent operations */ - struct esp_sdm_group_priv_s *groups[SOC_SDM_GROUPS]; /* SDM group pool */ - int group_ref_counts[SOC_SDM_GROUPS]; /* Reference count used to protect group install/uninstall */ + rmutex_t lock; /* Lock for protecting concurrent operations */ + struct esp_sdm_group_priv_s *groups[SDM_CAPS_GET(INST_NUM)]; /* SDM group pool */ + int group_ref_counts[SDM_CAPS_GET(INST_NUM)]; /* Reference count used to protect group install/uninstall */ }; /**************************************************************************** @@ -359,7 +358,7 @@ struct esp_sdm_channel_priv_s *esp_sdm_create_config_channel( esp_configgpio(config.gpio_num, attr); esp_gpio_matrix_out(config.gpio_num, - sigma_delta_periph_signals.channels[ret->chan_id].sd_sig, + soc_sdm_signals[group_id].channels[ret->chan_id].sig_id_matrix, (config.flags && INVERT_OUT), false); esp_clk_tree_src_get_freq_hz(g_esp_sdm.groups[ret->group_id]->clk_src, @@ -411,7 +410,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num)); - for (i = 0; i < SOC_SDM_GROUPS; i++) + for (i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { nxrmutex_lock(&(g_esp_sdm.lock)); if (g_esp_sdm.groups[i] == NULL) @@ -425,16 +424,21 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( } else { + sdm_hal_init_config_t hal_config = + { + .group_id = group_id, + }; + g_esp_sdm.groups[i]->group_id = i; g_esp_sdm.groups[i]->clk_src = SDM_CLK_SRC_DEFAULT; group_id = i; - sdm_hal_init(&g_esp_sdm.groups[i]->hal, i); + sdm_hal_init(&g_esp_sdm.groups[i]->hal, &hal_config); sdm_ll_enable_clock(g_esp_sdm.groups[i]->hal.dev, true); ainfo("new group (%d) at %p\n", i, g_esp_sdm.groups[i]); break; } } - else if (g_esp_sdm.group_ref_counts[i] < SOC_SDM_CHANNELS_PER_GROUP) + else if (g_esp_sdm.group_ref_counts[i] < SDM_CAPS_GET(CHANS_PER_INST)) { group_id = i; break; @@ -442,7 +446,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( } if (g_esp_sdm.group_ref_counts[group_id] >= - SOC_SDM_CHANNELS_PER_GROUP) + SDM_CAPS_GET(CHANS_PER_INST)) { aerr("ERROR! No free slot available\n"); return NULL; @@ -453,7 +457,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( nxrmutex_unlock(&(g_esp_sdm.lock)); flags = spin_lock_irqsave(&group->spinlock); - for (j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++) + for (j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { if (group->channels[j] == NULL) { @@ -521,7 +525,7 @@ int esp_sdm_create_channel(struct esp_sdm_chan_config_s config, DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num)); - for (i = 0; i < SOC_SDM_CHANNELS_PER_GROUP; i++) + for (i = 0; i < SDM_CAPS_GET(CHANS_PER_INST); i++) { if (group->channels[i] == NULL) { @@ -582,7 +586,7 @@ struct dac_dev_s *esp_sdminitialize(struct esp_sdm_chan_config_s config) { ret->ad_priv = (void *)sdm; ret->ad_ops = &ops; - ret->ad_nchannel = SOC_SDM_CHANNELS_PER_GROUP; + ret->ad_nchannel = SDM_CAPS_GET(CHANS_PER_INST); } return (struct dac_dev_s *)ret; diff --git a/arch/risc-v/src/common/espressif/esp_serial.c b/arch/risc-v/src/common/espressif/esp_serial.c index 56ce7f62c98b1..5df365e033b70 100644 --- a/arch/risc-v/src/common/espressif/esp_serial.c +++ b/arch/risc-v/src/common/espressif/esp_serial.c @@ -55,10 +55,9 @@ #endif #include "esp_clk_tree.h" -#include "esp_private/uart_share_hw_ctrl.h" #include "esp_private/esp_clk_tree_common.h" #include "hal/uart_hal.h" -#include "soc/uart_periph.h" +#include "hal/uart_periph.h" #include "soc/clk_tree_defs.h" #include "periph_ctrl.h" @@ -465,6 +464,7 @@ static int esp_setup(uart_dev_t *dev) soc_module_clk_t src_clk; uint32_t sclk_freq; bool success = false; + irqstate_t flags; /* Enable the UART Clock */ @@ -476,7 +476,7 @@ static int esp_setup(uart_dev_t *dev) ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq); - esp_os_enter_critical(&(g_uart_context[priv->id].spinlock)); + flags = enter_critical_section(); /* Initialize UART module */ #ifdef CONFIG_ESPRESSIF_LP_UART @@ -500,7 +500,7 @@ static int esp_setup(uart_dev_t *dev) if (priv->id < SOC_UART_HP_NUM) { esp_clk_tree_enable_src(UART_SCLK_XTAL, true); - HP_UART_SRC_CLK_ATOMIC() + PERIPH_RCC_ATOMIC() { uart_hal_set_sclk(priv->hal, UART_SCLK_XTAL); success = uart_hal_set_baudrate(priv->hal, priv->baud, sclk_freq); @@ -567,7 +567,7 @@ static int esp_setup(uart_dev_t *dev) else #endif - esp_os_exit_critical(&(g_uart_context[priv->id].spinlock)); + leave_critical_section(flags); if (success == false) { @@ -643,18 +643,21 @@ static int esp_attach(uart_dev_t *dev) source = uart_periph_signal[priv->id].irq; priv->cpuint = esp_setup_irq(source, priv->int_pri, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + uart_handler, + dev); /* Attach and enable the IRQ */ - ret = irq_attach(ESP_SOURCE2IRQ(source), uart_handler, dev); - if (ret == OK) + if (priv->cpuint >= 0) { up_enable_irq(ESP_SOURCE2IRQ(source)); + ret = OK; } else { up_disable_irq(ESP_SOURCE2IRQ(source)); + ret = -EINVAL; } return ret; diff --git a/arch/risc-v/src/common/espressif/esp_sha.c b/arch/risc-v/src/common/espressif/esp_sha.c index 2be3486100b57..a4dd20609b83d 100644 --- a/arch/risc-v/src/common/espressif/esp_sha.c +++ b/arch/risc-v/src/common/espressif/esp_sha.c @@ -247,6 +247,7 @@ int esp_sha1_update(struct esp_sha1_context_s *ctx, return ret; } + sha_hal_set_mode(ctx->mode); if (ctx->sha_state == ESP_SHA_STATE_INIT) { ctx->first_block = true; @@ -471,6 +472,7 @@ int esp_sha256_update(struct esp_sha256_context_s *ctx, return ret; } + sha_hal_set_mode(ctx->mode); if (ctx->sha_state == ESP_SHA_STATE_INIT) { ctx->first_block = true; diff --git a/arch/risc-v/src/common/espressif/esp_spi.c b/arch/risc-v/src/common/espressif/esp_spi.c index 82f289cf92bf6..96dc575e26a73 100644 --- a/arch/risc-v/src/common/espressif/esp_spi.c +++ b/arch/risc-v/src/common/espressif/esp_spi.c @@ -51,10 +51,6 @@ #include "esp_irq.h" #include "esp_gpio.h" -#ifdef CONFIG_ESPRESSIF_SPI2_DMA -#include "esp_dma.h" -#endif - #include "riscv_internal.h" #include "esp_cache.h" @@ -68,8 +64,9 @@ #include "hal/hal_utils.h" #include "periph_ctrl.h" #include "esp_private/spi_share_hw_ctrl.h" -#include "soc/gdma_periph.h" +#include "hal/gdma_periph.h" #include "hal/gdma_ll.h" +#include "hal/dma_types.h" #include "esp_memory_utils.h" #if SOC_GDMA_SUPPORTED @@ -185,6 +182,10 @@ typedef dma_descriptor_align4_t spi_dma_desc_t; #define spi_dma_start(chan, addr) gdma_start(chan, (intptr_t)(addr)) #endif +/* peripheral hardware limitation for clock source into peripheral */ + +#define SPI_PERIPH_SRC_FREQ_MAX (80*1000*1000) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -229,6 +230,11 @@ struct esp_spi_priv_s * Private Function Prototypes ****************************************************************************/ +#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV +static uint32_t spi_find_clock_src_pre_div(uint32_t src_freq, + uint32_t target_freq); +#endif //SPI_LL_SUPPORT_CLK_SRC_PRE_DIV + #ifdef CONFIG_ESPRESSIF_SPI2_DMA static uint32_t spi_common_dma_setup(int chan, bool tx, spi_dma_desc_t *dmadesc, uint32_t num, @@ -401,6 +407,39 @@ static uint32_t blank_arr[SPI_BLANK_ARRAY_SIZE]; * Private Functions ****************************************************************************/ +#if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV +static uint32_t spi_find_clock_src_pre_div(uint32_t src_freq, + uint32_t target_freq) +{ + /* pre division must be even and at least 2 */ + + uint32_t total_div; + uint32_t pre_div; + uint32_t min_div = ((src_freq / SPI_PERIPH_SRC_FREQ_MAX) + 1) & (~0x01ul); + + min_div = min_div < 2 ? 2 : min_div; + + total_div = src_freq / target_freq; + + /* Loop the `div` to find a divisible value of `total_div` */ + + for (pre_div = min_div; + pre_div <= MIN(total_div, SPI_LL_SRC_PRE_DIV_MAX); + pre_div += 2) + { + if ((total_div % pre_div) || + (total_div / pre_div) > SPI_LL_PERIPH_CLK_DIV_MAX) + { + continue; + } + + return pre_div; + } + + return min_div; +} +#endif //SPI_LL_SUPPORT_CLK_SRC_PRE_DIV + /**************************************************************************** * Name: spi_common_dma_setup * @@ -443,7 +482,7 @@ static uint32_t spi_common_dma_setup(int chan, bool tx, for (i = 0; i < num; i++) { - data_len = MIN(bytes, ESPRESSIF_DMA_BUFLEN_MAX); + data_len = MIN(bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED); /* Buffer length must be rounded to next 32-bit boundary. */ @@ -614,24 +653,9 @@ static uint32_t esp_spi_setfrequency(struct spi_dev_s *dev, } #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV - if (clock_source_hz / 2 > (80 * 1000000)) - { - /* clock_source_hz beyond peripheral HW limitation, calc pre-divider */ - - hal_utils_clk_info_t clk_cfg = - { - .src_freq_hz = clock_source_hz, - .exp_freq_hz = frequency * 2, /* we have (hs_clk = 2*mst_clk), calc hs_clk first */ - .round_opt = HAL_DIV_ROUND, - .min_integ = 1, - .max_integ = SPI_LL_CLK_SRC_PRE_DIV_MAX / 2, - }; - - hal_utils_calc_clk_div_integer(&clk_cfg, &clock_source_div); - } - - clock_source_div *= 2; /* convert to mst_clk function divider */ - clock_source_hz /= clock_source_div; /* actual freq enter to SPI peripheral */ + clock_source_div = spi_find_clock_src_pre_div(clock_source_hz, + SPI_DEFAULT_FREQ); + clock_source_hz /= clock_source_div; /* actual freq enter to SPI peripheral */ #endif priv->timing_param->clk_src_hz = clock_source_hz; @@ -1308,24 +1332,21 @@ void esp_spi_dma_init(struct spi_dev_s *dev) struct esp_spi_priv_s *priv = (struct esp_spi_priv_s *)dev; gdma_channel_alloc_config_t tx_handle = { - .direction = GDMA_CHANNEL_DIRECTION_TX, - .flags.reserve_sibling = 1, + 0 }; gdma_channel_alloc_config_t rx_handle = { - .direction = GDMA_CHANNEL_DIRECTION_RX, + 0 }; /* Request a GDMA channel for SPI peripheral */ - SPI_GDMA_NEW_CHANNEL(&tx_handle, &priv->dma_channel_tx); + SPI_GDMA_NEW_CHANNEL(&tx_handle, &priv->dma_channel_tx, NULL); gdma_connect(priv->dma_channel_tx, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); - rx_handle.sibling_chan = priv->dma_channel_tx; - - SPI_GDMA_NEW_CHANNEL(&rx_handle, &priv->dma_channel_rx); + SPI_GDMA_NEW_CHANNEL(&rx_handle, NULL, &priv->dma_channel_rx); gdma_connect(priv->dma_channel_rx, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); } @@ -1398,7 +1419,7 @@ static void esp_spi_init(struct spi_dev_s *dev) spi_periph_signal[priv->id].spiclk_out, 0, 0); #endif - SPI_COMMON_RCC_CLOCK_ATOMIC() + PERIPH_RCC_ATOMIC() { spi_ll_enable_bus_clock(priv->id, true); spi_ll_reset_register(priv->id); @@ -1464,7 +1485,7 @@ static void esp_spi_deinit(struct spi_dev_s *dev) # endif #endif - SPI_COMMON_RCC_CLOCK_ATOMIC() + PERIPH_RCC_ATOMIC() { spi_ll_enable_bus_clock(priv->id, false); } @@ -1557,7 +1578,9 @@ struct spi_dev_s *esp_spibus_initialize(int port) priv->cpuint = esp_setup_irq(spi_periph_signal[priv->id].irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_spi_interrupt, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -1566,18 +1589,6 @@ struct spi_dev_s *esp_spibus_initialize(int port) return NULL; } - if (irq_attach(ESP_SOURCE2IRQ(spi_periph_signal[priv->id].irq), - esp_spi_interrupt, priv) != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp_teardown_irq(spi_periph_signal[priv->id].irq, priv->cpuint); - priv->cpuint = -ENOMEM; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the SPI device. */ up_enable_irq(ESP_SOURCE2IRQ(spi_periph_signal[priv->id].irq)); diff --git a/arch/risc-v/src/common/espressif/esp_spi_slave.c b/arch/risc-v/src/common/espressif/esp_spi_slave.c index 587e24b758168..5f38a91174d16 100644 --- a/arch/risc-v/src/common/espressif/esp_spi_slave.c +++ b/arch/risc-v/src/common/espressif/esp_spi_slave.c @@ -44,7 +44,6 @@ #include -#include "esp_dma.h" #include "esp_cache.h" #include "esp_heap_caps.h" #include "esp_private/esp_cache_private.h" @@ -56,8 +55,9 @@ #include "hal/spi_slave_hal.h" #include "periph_ctrl.h" #include "esp_private/spi_share_hw_ctrl.h" -#include "soc/gdma_periph.h" +#include "hal/gdma_periph.h" #include "hal/gdma_ll.h" +#include "hal/dma_types.h" #if SOC_GDMA_SUPPORTED # include "esp_private/gdma.h" @@ -74,10 +74,10 @@ #ifdef CONFIG_ESPRESSIF_SPI2_DMA /* SPI DMA RX/TX number of descriptors */ -#if (SPI_SLAVE_BUFSIZE % ESPRESSIF_DMA_DATALEN_MAX) > 0 -# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESPRESSIF_DMA_DATALEN_MAX + 1) +#if (SPI_SLAVE_BUFSIZE % DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) > 0 +# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED + 1) #else -# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / ESPRESSIF_DMA_DATALEN_MAX) +# define SPI_DMA_DESC_NUM (SPI_SLAVE_BUFSIZE / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) #endif #endif /* CONFIG_ESPRESSIF_SPI2_DMA */ @@ -390,7 +390,7 @@ static uint32_t spi_slave_common_dma_setup(int chan, bool tx, for (i = 0; i < num; i++) { - data_len = MIN(bytes, ESPRESSIF_DMA_BUFLEN_MAX); + data_len = MIN(bytes, DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED); /* Buffer length must be rounded to next 32-bit boundary. */ @@ -894,24 +894,21 @@ static void spislave_dma_init(struct spislave_priv_s *priv) gdma_channel_alloc_config_t tx_handle = { - .direction = GDMA_CHANNEL_DIRECTION_TX, - .flags.reserve_sibling = 1, + 0 }; gdma_channel_alloc_config_t rx_handle = { - .direction = GDMA_CHANNEL_DIRECTION_RX, + 0 }; /* Request a GDMA channel for SPI peripheral */ - SPI_GDMA_NEW_CHANNEL(&tx_handle, &priv->dma_channel_tx); + SPI_GDMA_NEW_CHANNEL(&tx_handle, &priv->dma_channel_tx, NULL); gdma_connect(priv->dma_channel_tx, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); - rx_handle.sibling_chan = priv->dma_channel_tx; - - SPI_GDMA_NEW_CHANNEL(&rx_handle, &priv->dma_channel_rx); + SPI_GDMA_NEW_CHANNEL(&rx_handle, NULL, &priv->dma_channel_rx); gdma_connect(priv->dma_channel_rx, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_SPI, 2)); } @@ -943,7 +940,7 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) esp_gpiowrite(config->miso_pin, 1); esp_gpiowrite(config->clk_pin, 1); - esp_configgpio(config->cs_pin, CS_PIN_FUNCTION); + esp_configgpio(config->cs_pin, CS_PIN_FUNCTION | RISING); esp_configgpio(config->mosi_pin, MOSI_PIN_FUNCTION); esp_configgpio(config->miso_pin, MISO_PIN_FUNCTION); esp_configgpio(config->clk_pin, CLK_PIN_FUNCTION); @@ -964,7 +961,7 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) spi_periph_signal[priv->cfg.host_id].spiclk_in, 0); #endif - SPI_COMMON_RCC_CLOCK_ATOMIC() + PERIPH_RCC_ATOMIC() { spi_ll_enable_bus_clock(priv->cfg.host_id, true); spi_ll_reset_register(priv->cfg.host_id); @@ -974,7 +971,7 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) spislave_dma_init(priv); #endif - esp_gpioirqenable(ESP_PIN2IRQ(config->cs_pin), RISING); + esp_gpioirqenable(config->cs_pin); priv->ctx.rx_lsbfirst = 0; priv->ctx.tx_lsbfirst = 0; @@ -1412,9 +1409,9 @@ struct spi_slave_ctrlr_s *esp_spislave_ctrlr_initialize(int port) /* Attach IRQ for CS pin interrupt */ - ret = irq_attach(ESP_PIN2IRQ(priv->config->cs_pin), - spislave_cs_interrupt, - priv); + ret = esp_gpio_irq(priv->config->cs_pin, + spislave_cs_interrupt, + priv); if (ret != OK) { /* Failed to attach IRQ for CS pin interrupt. */ @@ -1435,7 +1432,9 @@ struct spi_slave_ctrlr_s *esp_spislave_ctrlr_initialize(int port) priv->cpuint = esp_setup_irq(spi_periph_signal[priv->cfg.host_id].irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + spislave_periph_interrupt, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -1445,21 +1444,6 @@ struct spi_slave_ctrlr_s *esp_spislave_ctrlr_initialize(int port) return NULL; } - ret = irq_attach(ESP_SOURCE2IRQ(spi_periph_signal[priv->cfg.host_id].irq), - spislave_periph_interrupt, priv); - - if (ret != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp_teardown_irq(spi_periph_signal[priv->cfg.host_id].irq, - priv->cpuint); - priv->cpuint = -ENOMEM; - leave_critical_section(flags); - - return NULL; - } - priv->refs++; spislave_initialize(spislave_dev); @@ -1513,7 +1497,7 @@ int esp_spislave_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr) spi_ll_disable_intr(priv->ctx.hw, SPI_LL_INTR_TRANS_DONE); - SPI_COMMON_RCC_CLOCK_ATOMIC() + PERIPH_RCC_ATOMIC() { spi_ll_enable_bus_clock(priv->cfg.host_id, false); } diff --git a/arch/risc-v/src/common/espressif/esp_spiflash.c b/arch/risc-v/src/common/espressif/esp_spiflash.c index 96ec09a60dfb5..b42223f11ef60 100644 --- a/arch/risc-v/src/common/espressif/esp_spiflash.c +++ b/arch/risc-v/src/common/espressif/esp_spiflash.c @@ -37,7 +37,7 @@ #include #include -#include "esp_flash_internal.h" +#include "esp_private/esp_flash_internal.h" #include "esp_flash.h" #include "esp_flash_encrypt.h" #include "esp_private/cache_utils.h" @@ -456,126 +456,6 @@ static bool aligned_flash_erase(size_t addr, size_t size) } #endif /* CONFIG_ESP_FLASH_ENCRYPTION */ -/**************************************************************************** - * Name: spi_flash_op_block_task - * - * Description: - * Disable the non-IRAM interrupts on the other core (the one that isn't - * handling the SPI flash operation) and notify that the SPI flash - * operation can start. Wait on a busy loop until it's finished and then - * re-enable the non-IRAM interrupts. - * - * Input Parameters: - * argc - Not used. - * argv - Not used. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SMP -static int spi_flash_op_block_task(int argc, char *argv[]) -{ - struct tcb_s *tcb = this_task(); - int cpu = this_cpu(); - - for (; ; ) - { - DEBUGASSERT((1 << cpu) & tcb->affinity); - /* Wait for a request from the other CPU to suspend interrupts - * and cache on this CPU. - */ - - nxsem_wait(&g_cpu_prepare_sem[cpu]); - - sched_lock(); - esp_intr_noniram_disable(); - - s_flash_op_complete = false; - s_flash_op_can_start = true; - while (!s_flash_op_complete) - { - /* Wait for a request to restore interrupts and cache on this CPU. - * This indicates SPI Flash operation is complete. - */ - } - - esp_intr_noniram_enable(); - sched_unlock(); - } - - return OK; -} - -/**************************************************************************** - * Name: spiflash_init_spi_flash_op_block_task - * - * Description: - * Starts a kernel thread that waits for a semaphore indicating that a SPI - * flash operation is going to take place in the other CPU. - * - * Input Parameters: - * cpu - The CPU core that will run the created task to wait on a busy - * loop while the SPI flash operation finishes - * - * Returned Value: - * 0 (OK) on success; A negated errno value on failure. - * - ****************************************************************************/ - -static int spiflash_init_spi_flash_op_block_task(int cpu) -{ - FAR struct tcb_s *tcb; - int ret; - char *argv[2]; - char arg1[32]; - cpu_set_t cpuset; - - snprintf(arg1, sizeof(arg1), "%p", &cpu); - argv[0] = arg1; - argv[1] = NULL; - - /* Allocate a TCB for the new task. */ - - tcb = kmm_zalloc(sizeof(struct tcb_s)); - if (!tcb) - { - serr("ERROR: Failed to allocate TCB\n"); - return -ENOMEM; - } - - /* Setup the task type */ - - tcb->flags = TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_FREE_TCB; - - /* Initialize the task */ - - ret = nxtask_init(tcb, "spiflash_op", - SCHED_PRIORITY_MAX, - NULL, SPIFLASH_OP_TASK_STACKSIZE, - spi_flash_op_block_task, argv, environ, NULL); - if (ret < OK) - { - kmm_free(tcb); - return ret; - } - - /* Set the affinity */ - - CPU_ZERO(&cpuset); - CPU_SET(cpu, &cpuset); - tcb->affinity = cpuset; - - /* Activate the task */ - - nxtask_activate(tcb); - - return ret; -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -733,44 +613,3 @@ int esp_spiflash_erase(uint32_t address, uint32_t length) return ret; } - -/**************************************************************************** - * Name: esp_spiflash_init - * - * Description: - * Initialize ESP SPI flash driver. - * SPI Flash actual chip initialization initial is done by esp_start on - * STARTUP_FN hook. - * - * Input Parameters: - * None. - * - * Returned Value: - * OK if success or a negative value if fail. - * - ****************************************************************************/ - -int esp_spiflash_init(void) -{ - int ret = OK; - int cpu; - -#ifdef CONFIG_SMP - sched_lock(); - - for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) - { - ret = spiflash_init_spi_flash_op_block_task(cpu); - if (ret != OK) - { - return ret; - } - } - - sched_unlock(); -#else - UNUSED(cpu); -#endif - - return ret; -} diff --git a/arch/risc-v/src/common/espressif/esp_spiflash.h b/arch/risc-v/src/common/espressif/esp_spiflash.h index 0d29a28945515..70061e04b6f4e 100644 --- a/arch/risc-v/src/common/espressif/esp_spiflash.h +++ b/arch/risc-v/src/common/espressif/esp_spiflash.h @@ -104,22 +104,6 @@ int esp_spiflash_erase(uint32_t start, uint32_t length); int esp_spiflash_write(uint32_t address, const void *buffer, uint32_t length); -/**************************************************************************** - * Name: esp_spiflash_init - * - * Description: - * Initialize ESP SPI flash driver. - * - * Input Parameters: - * None. - * - * Returned Value: - * OK if success or a negative value if fail. - * - ****************************************************************************/ - -int esp_spiflash_init(void); - #ifdef __cplusplus } #endif diff --git a/arch/risc-v/src/common/espressif/esp_start.c b/arch/risc-v/src/common/espressif/esp_start.c index 6d21aa14bc9b3..1e5f07ebbfaaa 100644 --- a/arch/risc-v/src/common/espressif/esp_start.c +++ b/arch/risc-v/src/common/espressif/esp_start.c @@ -51,25 +51,31 @@ #include "hal/cache_types.h" #include "hal/cache_ll.h" #include "hal/cache_hal.h" +#include "hal/rwdt_ll.h" #include "soc/ext_mem_defs.h" -#include "soc/extmem_reg.h" -#include "soc/mmu.h" #include "soc/reg_base.h" #include "spi_flash_mmap.h" #include "rom/cache.h" +#include "soc/soc.h" +#include "soc/soc_caps.h" #include "soc/rtc.h" #include "bootloader_init.h" +#include "bootloader_sha.h" #ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT -#include "bootloader_flash_priv.h" -#include "esp_rom_uart.h" +#include "esp_rom_serial_output.h" #include "esp_app_format.h" #endif +#include "bootloader_flash_priv.h" #include "esp_private/startup_internal.h" #include "esp_private/spi_flash_os.h" +#if SOC_APM_SUPPORTED +# include "hal/apm_hal.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -82,31 +88,25 @@ #if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -# define PRIMARY_SLOT_OFFSET CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET -# define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) -#else -/* Force offset to the beginning of the whole image - */ - -# define PRIMARY_SLOT_OFFSET 0 -#endif +# ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +# define PRIMARY_SLOT_OFFSET CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET +# else +# define PRIMARY_SLOT_OFFSET 0 /* Force offset to the beginning of the whole image */ +# endif # define HDR_ATTR __attribute__((section(".entry_addr"))) \ - __attribute__((used)) -# define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) -# define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) -# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ -# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG -# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \ - EXTMEM_ICACHE_SHUT_DBUS_M) - + __attribute__((used)) # define CHECKSUM_ALIGN 16 # define IS_PADD(addr) ((addr) == 0) +#if defined(SOC_TCM_LOW) || defined(SOC_TCM_HIGH) +# define IS_TCM(addr) ((addr) >= SOC_TCM_LOW && (addr) < SOC_TCM_HIGH) +#else +# define IS_TCM(addr) false +#endif # define IS_DRAM(addr) ((addr) >= SOC_DRAM_LOW && (addr) < SOC_DRAM_HIGH) # define IS_IRAM(addr) ((addr) >= SOC_IRAM_LOW && (addr) < SOC_IRAM_HIGH) # define IS_IROM(addr) ((addr) >= SOC_IROM_LOW && (addr) < SOC_IROM_HIGH) # define IS_DROM(addr) ((addr) >= SOC_DROM_LOW && (addr) < SOC_DROM_HIGH) -# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) +# define IS_SRAM(addr) (IS_TCM(addr) || IS_IRAM(addr) || IS_DRAM(addr)) # define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) # ifdef SOC_RTC_FAST_MEM_SUPPORTED # define IS_RTC_FAST_IRAM(addr) \ @@ -129,6 +129,7 @@ # define IS_NONE(addr) (!IS_IROM(addr) \ && !IS_DROM(addr) \ && !IS_IRAM(addr) \ + && !IS_TCM(addr) \ && !IS_DRAM(addr) \ && !IS_RTC_FAST_IRAM(addr) \ && !IS_RTC_FAST_DRAM(addr) \ @@ -138,6 +139,8 @@ # define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr) #endif +#define NAPOT_RWX (PMPCFG_A_NAPOT | PMPCFG_RWX_MASK) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -153,6 +156,12 @@ extern uint8_t _image_drom_lma[]; extern uint8_t _image_drom_size[]; #endif +extern int _vector_table; + +#if SOC_INT_CLIC_SUPPORTED +extern int _mtvt_table; +#endif + /**************************************************************************** * ROM Function Prototypes ****************************************************************************/ @@ -195,30 +204,6 @@ extern uint8_t _rodata_reserved_end[]; * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: calc_mmu_pages - * - * Description: - * Calculate the number of cache pages to map. - * - * Input Parameters: - * size - Size of data to map - * vaddr - Virtual address where data will be mapped - * - * Returned Value: - * Number of cache MMU pages required to do the mapping. - * - ****************************************************************************/ - -#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ - defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) -static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) -{ - return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / - MMU_BLOCK_SIZE; -} -#endif - /**************************************************************************** * Name: map_rom_segments * @@ -307,7 +292,8 @@ static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, IS_MMAP(segment_hdr.load_addr) ? IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" : IS_PADD(segment_hdr.load_addr) ? "padd" : - IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram", + IS_TCM(segment_hdr.load_addr) ? "tcm" : + IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram", offset + sizeof(esp_image_segment_header_t), segment_hdr.load_addr, segment_hdr.data_len, segment_hdr.data_len); @@ -383,6 +369,12 @@ static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, cache_ll_l1_enable_bus(1, bus_mask); #endif +#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + cache_ll_invalidate_addr(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, + CACHE_LL_ID_ALL, app_irom_vaddr_aligned, + actual_mapped_len); +#endif + /* ------------------Enable Cache----------------------------------- */ cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); @@ -428,12 +420,66 @@ static void IRAM_ATTR NOINLINE_ATTR recalib_bbpll(void) * Public Functions ****************************************************************************/ +extern void esp_chip_revision_check(void); + +/**************************************************************************** + * Name: riscv_soc_initialize + * + * Description: + * Initialize SoC-specific initialization. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function riscv_soc_initialize(void) +{ + sys_startup_fn(); +} + +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void) +{ + SYS_STARTUP_FN(); +} + /**************************************************************************** * Name: __esp_start ****************************************************************************/ void __esp_start(void) { + esp_cpu_intr_set_ivt_addr(&_vector_table); + +#if SOC_INT_CLIC_SUPPORTED + /* When hardware vectored interrupts are enabled in CLIC, + * the CPU jumps to this base address + 4 * interrupt_id. + */ + + esp_cpu_intr_set_mtvt_addr(&_mtvt_table); +#endif + #ifdef CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE uint32_t _instruction_size; uint32_t cache_mmu_irom_size; @@ -448,6 +494,11 @@ void __esp_start(void) #else bootloader_clear_bss_section(); #endif + /* Initialize the per CPU areas */ + +#ifdef CONFIG_RISCV_PERCPU_SCRATCH + riscv_percpu_add_hart(0); +#endif #if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) @@ -553,12 +604,6 @@ void __esp_start(void) showprogress("D"); - SYS_STARTUP_FN(); - - showprogress("E"); - - /* Bring up NuttX */ - nx_start(); for (; ; ); diff --git a/arch/risc-v/src/common/espressif/esp_start.h b/arch/risc-v/src/common/espressif/esp_start.h index 3b87bdf068b01..9667207db76e2 100644 --- a/arch/risc-v/src/common/espressif/esp_start.h +++ b/arch/risc-v/src/common/espressif/esp_start.h @@ -29,6 +29,26 @@ #include +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void); + /**************************************************************************** * Name: esp_board_initialize * diff --git a/arch/risc-v/src/common/espressif/esp_systemreset.c b/arch/risc-v/src/common/espressif/esp_systemreset.c index e58a327837b13..fed7cc8adb4a9 100644 --- a/arch/risc-v/src/common/espressif/esp_systemreset.c +++ b/arch/risc-v/src/common/espressif/esp_systemreset.c @@ -52,7 +52,7 @@ static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO]; ****************************************************************************/ /**************************************************************************** - * Name: esp_register_shutdown_handler + * Name: esp_register_reset_handler * * Description: * This function allows you to register a handler that gets invoked before @@ -67,7 +67,7 @@ static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO]; * ****************************************************************************/ -int esp_register_shutdown_handler(shutdown_handler_t handler) +int esp_register_reset_handler(shutdown_handler_t handler) { for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) { @@ -86,11 +86,11 @@ int esp_register_shutdown_handler(shutdown_handler_t handler) } /**************************************************************************** - * Name: esp_unregister_shutdown_handler + * Name: esp_unregister_reset_handler * * Description: * This function allows you to unregister a handler which was previously - * registered using esp_register_shutdown_handler function. + * registered using esp_register_reset_handler function. * * Input Parameters: * handler - Function to execute on restart. @@ -101,7 +101,7 @@ int esp_register_shutdown_handler(shutdown_handler_t handler) * ****************************************************************************/ -int esp_unregister_shutdown_handler(shutdown_handler_t handler) +int esp_unregister_reset_handler(shutdown_handler_t handler) { for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) { diff --git a/arch/risc-v/src/common/espressif/esp_systemreset.h b/arch/risc-v/src/common/espressif/esp_systemreset.h index 5f51d8bb3d682..5daef4fa2b2bf 100644 --- a/arch/risc-v/src/common/espressif/esp_systemreset.h +++ b/arch/risc-v/src/common/espressif/esp_systemreset.h @@ -53,7 +53,7 @@ typedef void (*shutdown_handler_t)(void); ****************************************************************************/ /**************************************************************************** - * Name: esp_register_shutdown_handler + * Name: esp_register_reset_handler * * Description: * This function allows you to register a handler that gets invoked before @@ -68,14 +68,14 @@ typedef void (*shutdown_handler_t)(void); * ****************************************************************************/ -int esp_register_shutdown_handler(shutdown_handler_t handler); +int esp_register_reset_handler(shutdown_handler_t handler); /**************************************************************************** - * Name: esp_unregister_shutdown_handler + * Name: esp_unregister_reset_handler * * Description: * This function allows you to unregister a handler which was previously - * registered using esp_register_shutdown_handler function. + * registered using esp_register_reset_handler function. * * Input Parameters: * handler - Function to execute on restart. @@ -86,7 +86,7 @@ int esp_register_shutdown_handler(shutdown_handler_t handler); * ****************************************************************************/ -int esp_unregister_shutdown_handler(shutdown_handler_t handler); +int esp_unregister_reset_handler(shutdown_handler_t handler); /**************************************************************************** * Name: up_shutdown_handler diff --git a/arch/risc-v/src/common/espressif/esp_temperature_sensor.c b/arch/risc-v/src/common/espressif/esp_temperature_sensor.c index 7b5a8edd84c3d..d5738658335bc 100644 --- a/arch/risc-v/src/common/espressif/esp_temperature_sensor.c +++ b/arch/risc-v/src/common/espressif/esp_temperature_sensor.c @@ -62,7 +62,7 @@ #include "hal/regi2c_ctrl.h" #include "hal/temperature_sensor_ll.h" #include "hal/temperature_sensor_types.h" -#include "soc/temperature_sensor_periph.h" +#include "hal/temperature_sensor_periph.h" #include "esp_efuse_rtc_calib.h" #include "hal/adc_ll.h" @@ -106,7 +106,6 @@ struct esp_temp_priv_s const temperature_sensor_attribute_t *tsens_attribute; /* Attribute struct of the common layer */ struct esp_temp_sensor_config_t cfg; /* Configuration struct of the common layer */ temperature_sensor_clk_src_t clk_src; /* Clock source to use */ - int module; /* Peripheral module */ int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifdef CONFIG_ESPRESSIF_TEMP_UORB @@ -198,7 +197,6 @@ struct esp_temp_priv_s esp_temp_priv = 0 }, .clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT, - .module = PERIPH_TEMPSENSOR_MODULE, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_ESPRESSIF_TEMP_UORB @@ -322,11 +320,10 @@ static int temperature_sensor_choose_best_range(struct esp_temp_priv_s *priv) static int temperature_sensor_read_delta_t(void) { - if (esp_efuse_rtc_calib_get_tsens_val(&g_delta_t) != OK) + g_delta_t = temperature_sensor_ll_load_calib_param(); + if (g_delta_t == 0) { - snwarn("Calibration failed"); - g_delta_t = 0; - return ERROR; + snwarn("No calibration param in eFuse"); } sninfo("delta_T = %f", g_delta_t); diff --git a/arch/risc-v/src/common/espressif/esp_tickless.c b/arch/risc-v/src/common/espressif/esp_tickless.c index f66688a19b395..7d76fb6711d3a 100644 --- a/arch/risc-v/src/common/espressif/esp_tickless.c +++ b/arch/risc-v/src/common/espressif/esp_tickless.c @@ -431,15 +431,13 @@ void up_timer_initialize(void) true); systimer_hal_enable_counter(&systimer_hal, SYSTIMER_COUNTER_OS_TICK); - esp_setup_irq(SYSTIMER_TARGET0_EDGE_INTR_SOURCE, + esp_setup_irq(ETS_SYSTIMER_TARGET0_INTR_SOURCE, ESP_IRQ_PRIORITY_DEFAULT, - SYSTIMER_TRIGGER_TYPE); - - /* Attach the timer interrupt. */ - - irq_attach(ESP_IRQ_SYSTIMER_TARGET0_EDGE, (xcpt_t)esp_tickless_isr, NULL); + SYSTIMER_TRIGGER_TYPE, + esp_tickless_isr, + NULL); /* Enable the allocated CPU interrupt. */ - up_enable_irq(ESP_IRQ_SYSTIMER_TARGET0_EDGE); + up_enable_irq(ESP_SOURCE2IRQ(ETS_SYSTIMER_TARGET0_INTR_SOURCE)); } diff --git a/arch/risc-v/src/common/espressif/esp_timer.c b/arch/risc-v/src/common/espressif/esp_timer.c index ca31facefa25f..016954cd2de67 100644 --- a/arch/risc-v/src/common/espressif/esp_timer.c +++ b/arch/risc-v/src/common/espressif/esp_timer.c @@ -42,9 +42,9 @@ #include "esp_attr.h" #include "hal/timer_hal.h" #include "hal/timer_ll.h" +#include "hal/timer_periph.h" #include "periph_ctrl.h" #include "soc/clk_tree_defs.h" -#include "soc/timer_periph.h" #include "esp_private/esp_clk_tree_common.h" /**************************************************************************** @@ -196,17 +196,13 @@ static int esp_timer_start(struct timer_lowerhalf_s *lower) timer_ll_enable_clock(priv->group_id, hal->timer_id, true); } - /* Enable timer group module clock */ - - timer_ll_enable_clock(priv->group_id, hal->timer_id, true); - /* Calculate the suitable prescaler according to the current APB * frequency to generate a period of 1 us. */ esp_clk_tree_src_get_freq_hz((soc_module_clk_t)GPTIMER_CLK_SRC_DEFAULT, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &counter_src_hz); + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, + &counter_src_hz); prescale = counter_src_hz / USEC_PER_SEC; /* Configure TIMER prescaler */ @@ -544,7 +540,7 @@ int esp_timer_initialize(int group_id) struct esp_timer_lowerhalf_s *lower = NULL; int timer_id = DEFAULT_TIMER_ID; char *devpath; - periph_module_t periph; + shared_periph_module_t periph; int irq; switch (group_id) @@ -581,14 +577,14 @@ int esp_timer_initialize(int group_id) lower->callback = NULL; lower->started = false; - periph = timer_group_periph_signals.groups[group_id].module; + periph = soc_timg_gptimer_signals[group_id][timer_id].parent_module; PERIPH_RCC_ACQUIRE_ATOMIC(periph, ref_count) { if (ref_count == 0) { - timer_ll_enable_bus_clock(group_id, true); - timer_ll_reset_register(group_id); + timg_ll_enable_bus_clock(group_id, true); + timg_ll_reset_register(group_id); } } @@ -615,15 +611,13 @@ int esp_timer_initialize(int group_id) lib_put_pathbuffer(devpath); - irq = timer_group_periph_signals.groups[group_id].timer_irq_id[timer_id]; + irq = soc_timg_gptimer_signals[group_id][timer_id].irq_id; esp_setup_irq(irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); - - /* Attach the handler for the timer IRQ */ - - irq_attach(ESP_SOURCE2IRQ(irq), (xcpt_t)esp_timer_isr, lower); + ESP_IRQ_TRIGGER_LEVEL, + esp_timer_isr, + lower); /* Enable the allocated CPU interrupt */ diff --git a/arch/risc-v/src/common/espressif/esp_timerisr.c b/arch/risc-v/src/common/espressif/esp_timerisr.c index a71a35d884d5f..42080fd1fc0b1 100644 --- a/arch/risc-v/src/common/espressif/esp_timerisr.c +++ b/arch/risc-v/src/common/espressif/esp_timerisr.c @@ -159,13 +159,9 @@ void up_timer_initialize(void) esp_setup_irq(CHIP_SYSTIMER_SOURCE, ESP_IRQ_PRIORITY_DEFAULT, - SYSTIMER_TRIGGER_TYPE); - - /* Attach the timer interrupt. */ - - irq_attach(ESP_SOURCE2IRQ(CHIP_SYSTIMER_SOURCE), - (xcpt_t)systimer_irq_handler, - NULL); + SYSTIMER_TRIGGER_TYPE, + systimer_irq_handler, + NULL); /* Enable the allocated CPU interrupt. */ diff --git a/arch/risc-v/src/common/espressif/esp_twai.c b/arch/risc-v/src/common/espressif/esp_twai.c index 5173ad4b4f215..14f9275f4fdc0 100644 --- a/arch/risc-v/src/common/espressif/esp_twai.c +++ b/arch/risc-v/src/common/espressif/esp_twai.c @@ -52,6 +52,7 @@ #include "periph_ctrl.h" #include "hal/twai_hal.h" #include "hal/twai_ll.h" +#include "hal/twai_periph.h" #include "soc/gpio_sig_map.h" #include "soc/reg_base.h" @@ -315,7 +316,7 @@ static int esp_twai_setup(struct can_dev_s *dev) twai_ll_get_and_clear_intrs(priv->ctx.dev); /* clear latched interrupts */ - irq = twai_controller_periph_signals.controllers[priv->port].irq_id; + irq = twai_periph_signals[priv->port].irq_id; if (priv->cpuint != -ENOMEM) { @@ -326,7 +327,9 @@ static int esp_twai_setup(struct can_dev_s *dev) priv->cpuint = esp_setup_irq(irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_twai_interrupt, + dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -337,18 +340,6 @@ static int esp_twai_setup(struct can_dev_s *dev) return ret; } - ret = irq_attach(ESP_SOURCE2IRQ(irq), esp_twai_interrupt, dev); - if (ret != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp_teardown_irq(irq, priv->cpuint); - priv->cpuint = -ENOMEM; - leave_critical_section(flags); - - return ret; - } - /* Enable the CPU interrupt that is linked to the TWAI device. */ up_enable_irq(ESP_SOURCE2IRQ(irq)); @@ -385,16 +376,12 @@ static void esp_twai_shutdown(struct can_dev_s *dev) { int irq; - irq = twai_controller_periph_signals.controllers[priv->port].irq_id; + irq = twai_periph_signals[priv->port].irq_id; /* Disable cpu interrupt */ up_disable_irq(ESP_SOURCE2IRQ(irq)); - /* Dissociate the IRQ from the ISR */ - - irq_detach(ESP_SOURCE2IRQ(irq)); - /* Free cpu interrupt that is attached to this peripheral */ esp_teardown_irq(irq, priv->cpuint); @@ -751,6 +738,8 @@ static int esp_twai_interrupt(int irq, void *context, void *arg) if ((regval & TWAI_LL_INTR_RI) != 0) { + twai_frame_header_t header; + memset(&hdr, 0, sizeof(hdr)); memset(data, 0, sizeof(data)); @@ -759,11 +748,13 @@ static int esp_twai_interrupt(int irq, void *context, void *arg) /* Release the receive buffer */ twai_ll_set_cmd_release_rx_buffer(priv->ctx.dev); - twai_ll_parse_frame_buffer(&rx_frame, &id, &dlc, data, - TWAI_FRAME_MAX_LEN, &flags); - hdr.ch_id = id; - hdr.ch_dlc = dlc; - hdr.ch_rtr = (flags && TWAI_MSG_FLAG_RTR) ? 1 : 0; + + twai_hal_parse_frame(&priv->ctx, &rx_frame, &header, data, + TWAI_FRAME_MAX_LEN); + + hdr.ch_id = header.id; + hdr.ch_dlc = header.dlc; + hdr.ch_rtr = (header.rtr && TWAI_MSG_FLAG_RTR) ? 1 : 0; can_receive(dev, &hdr, data); } @@ -814,8 +805,8 @@ struct can_dev_s *esp_twaiinitialize(int port) #ifdef CONFIG_ESPRESSIF_TWAI0 if (port == 0) { - int tx_sig = twai_controller_periph_signals.controllers[0].tx_sig; - int rx_sig = twai_controller_periph_signals.controllers[0].rx_sig; + int tx_sig = twai_periph_signals[0].tx_sig; + int rx_sig = twai_periph_signals[0].rx_sig; /* Configure CAN GPIO pins */ @@ -833,8 +824,8 @@ struct can_dev_s *esp_twaiinitialize(int port) #ifdef CONFIG_ESPRESSIF_TWAI1 if (port == 1) { - int tx_sig = twai_controller_periph_signals.controllers[1].tx_sig; - int rx_sig = twai_controller_periph_signals.controllers[1].rx_sig; + int tx_sig = twai_periph_signals[1].tx_sig; + int rx_sig = twai_periph_signals[1].rx_sig; /* Configure CAN GPIO pins */ diff --git a/arch/risc-v/src/common/espressif/esp_ulp.mk b/arch/risc-v/src/common/espressif/esp_ulp.mk index c84feed6df9f5..f6aedfcbdafcb 100644 --- a/arch/risc-v/src/common/espressif/esp_ulp.mk +++ b/arch/risc-v/src/common/espressif/esp_ulp.mk @@ -35,6 +35,22 @@ ULP_FOLDER = $(ULP_APP_FOLDER)$(DELIM)ulp ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO) ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)ulp ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include @@ -67,9 +83,10 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)c ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)lp_core$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)include + ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include # Linker scripts @@ -88,8 +105,8 @@ ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared$(DELIM)ulp_lp_core_memory_shared.c ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared$(DELIM)ulp_lp_core_lp_uart_shared.c ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared$(DELIM)ulp_lp_core_lp_timer_shared.c -ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)lp_core$(DELIM)lp_core_i2c.c ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)lp_core$(DELIM)lp_core_startup.c ULP_CSOURCES += $(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)lp_core$(DELIM)lp_core_utils.c diff --git a/arch/risc-v/src/common/espressif/esp_usbserial.c b/arch/risc-v/src/common/espressif/esp_usbserial.c index 5d7a6072f0917..a69374d05d3d2 100644 --- a/arch/risc-v/src/common/espressif/esp_usbserial.c +++ b/arch/risc-v/src/common/espressif/esp_usbserial.c @@ -280,7 +280,6 @@ static void esp_rxint(struct uart_dev_s *dev, bool enable) static int esp_attach(struct uart_dev_s *dev) { struct esp_priv_s *priv = dev->priv; - int ret; DEBUGASSERT(priv->cpuint == -ENOMEM); @@ -297,7 +296,9 @@ static int esp_attach(struct uart_dev_s *dev) priv->cpuint = esp_setup_irq(priv->source, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_interrupt, + dev); if (priv->cpuint < 0) { return priv->cpuint; @@ -305,8 +306,7 @@ static int esp_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, esp_interrupt, dev); - if (ret == OK) + if (priv->cpuint >= 0) { up_enable_irq(priv->irq); } @@ -315,7 +315,7 @@ static int esp_attach(struct uart_dev_s *dev) up_disable_irq(priv->irq); } - return ret; + return OK; } /**************************************************************************** diff --git a/arch/risc-v/src/common/espressif/esp_vectors.S b/arch/risc-v/src/common/espressif/esp_vectors.S index a939489dea209..df22fb249c7db 100644 --- a/arch/risc-v/src/common/espressif/esp_vectors.S +++ b/arch/risc-v/src/common/espressif/esp_vectors.S @@ -53,7 +53,49 @@ _vector_table: .option push .option norvc - .rept (32) - j exception_common - .endr + j _panic_handler /* 0: Exception entry */ + j exception_common /* 1: Free interrupt number */ + j exception_common /* 2: Free interrupt number */ + j exception_common /* 3: Free interrupt number */ + j exception_common /* 4: Free interrupt number */ + j exception_common /* 5: Free interrupt number */ + j exception_common /* 6: Free interrupt number */ + j exception_common /* 7: Free interrupt number */ + j exception_common /* 8: Free interrupt number */ + j exception_common /* 9: Free interrupt number */ + j exception_common /* 10: Free interrupt number */ + j exception_common /* 11: Free interrupt number */ + j exception_common /* 12: Free interrupt number */ + j exception_common /* 13: Free interrupt number */ + j exception_common /* 14: Free interrupt number */ + j exception_common /* 15: Free interrupt number */ + j exception_common /* 16: Free interrupt number */ + j exception_common /* 17: Free interrupt number */ + j exception_common /* 18: Free interrupt number */ + j exception_common /* 19: Free interrupt number */ + j exception_common /* 20: Free interrupt number */ + j exception_common /* 21: Free interrupt number */ + j exception_common /* 22: Free interrupt number */ + j exception_common /* 23: Free interrupt number */ + j _panic_handler /* 24: ETS_INT_WDT_INUM panic-interrupt (soc-level panic) */ + j _panic_handler /* 25: ETS_CACHEERR_INUM panic-interrupt (soc-level panic) */ + j _panic_handler /* 26: ETS_MEMPROT_ERR_INUM handler (soc-level panic) */ + j _panic_handler /* 27: ETS_ASSIST_DEBUG_INUM handler (soc-level panic) */ + j exception_common /* 28: Free interrupt number */ + j exception_common /* 29: Free interrupt number */ + j exception_common /* 30: Free interrupt number */ + j exception_common /* 31: Free interrupt number */ +/**************************************************************************** + * Name: exception_common + * + * Description: + * Handles interrupts. If kernel is in S-mode, handles delegated interrupts + * in S-mode interrupt handler. + * + ****************************************************************************/ + + .global _panic_handler + +_panic_handler: + j exception_common /* Dispatch the system call */ diff --git a/arch/risc-v/src/common/espressif/esp_wdt.c b/arch/risc-v/src/common/espressif/esp_wdt.c index 81a4d8e17b7cc..a9feac9c9d242 100644 --- a/arch/risc-v/src/common/espressif/esp_wdt.c +++ b/arch/risc-v/src/common/espressif/esp_wdt.c @@ -40,6 +40,7 @@ #include "hal/mwdt_ll.h" #include "hal/rwdt_ll.h" +#include "hal/timer_ll.h" #ifdef CONFIG_ESPRESSIF_XTWDT #include "hal/xt_wdt_ll.h" #include "hal/xt_wdt_hal.h" @@ -48,6 +49,7 @@ #endif #include "hal/wdt_hal.h" #include "soc/rtc.h" +#include "soc/system_intr.h" #include "periph_ctrl.h" /**************************************************************************** @@ -90,9 +92,11 @@ wdt_hal_write_protect_enable(dev->ctx); \ } while(0); -/* Check whether the provided device is a XTAL32K Watchdog Timer */ +/* Check whether the provided device type is XTAL32K, MWDT or RWDT */ #define IS_XTWDT(dev) (((struct esp_wdt_lowerhalf_s *)dev)->peripheral == XTAL32K) +#define IS_MWDT(dev) (((struct esp_wdt_lowerhalf_s *)dev)->peripheral == TIMER) +#define IS_RWDT(dev) (((struct esp_wdt_lowerhalf_s *)dev)->peripheral == RTC) /* XTWDT clock period in nanoseconds */ @@ -106,14 +110,9 @@ #define XT_WDT_CLK_CAL_CYCLES (500) -/* Helpers for converting from Q13.19 fixed-point format to float */ - -#define N 19 -#define Q_TO_FLOAT(x) ((float)x/(float)(1<peripheral == TIMER) { priv->action = WDT_STAGE_ACTION_RESET_SYSTEM; - timeout = MWDT_TIMEOUT_MS(priv->timeout); } else { priv->action = WDT_STAGE_ACTION_RESET_RTC; - timeout = RWDT_TIMEOUT_MS(priv->timeout); } wdt_hal_config_stage(priv->ctx, WDT_STAGE0, - timeout, - priv->action); + priv->timeout_ticks, + priv->action); } } else @@ -336,17 +338,15 @@ static int wdt_start(struct watchdog_lowerhalf_s *lower) if (priv->peripheral == TIMER) { priv->action = WDT_STAGE_ACTION_INT; - timeout = MWDT_TIMEOUT_MS(priv->timeout); } else { priv->action = WDT_STAGE_ACTION_INT; - timeout = RWDT_TIMEOUT_MS(priv->timeout); } wdt_hal_config_stage(priv->ctx, WDT_STAGE0, - timeout, - priv->action); + priv->timeout_ticks, + priv->action); /* Enable interrupt */ @@ -582,14 +582,12 @@ static int wdt_settimeout(struct watchdog_lowerhalf_s *lower, return -ERANGE; } - timeout = MWDT_TIMEOUT_MS(priv->timeout); + priv->timeout_ticks = MWDT_TIMEOUT_MS(priv->timeout); } else if (priv->peripheral == RTC) { - uint32_t period_13q19 = esp_clk_slowclk_cal_get(); - float period = Q_TO_FLOAT(period_13q19); - rtc_cycles = 1000.0f / period; - rtc_ms_max = (RWDT_FULL_STAGE / (uint32_t)rtc_cycles); + uint32_t freq_hz = rtc_clk_slow_freq_get_hz(); + rtc_ms_max = ((uint64_t)RWDT_FULL_STAGE / freq_hz) * 1000; /* Is this timeout a valid value for RTC WDT? */ @@ -600,15 +598,16 @@ static int wdt_settimeout(struct watchdog_lowerhalf_s *lower, return -ERANGE; } - timeout = timeout * rtc_cycles; + priv->timeout_ticks = + (uint32_t)((uint64_t)timeout * freq_hz / 1000); } - wdt_hal_config_stage(priv->ctx, WDT_STAGE0, - timeout, - priv->action); - wdt_hal_feed(priv->ctx); + wdt_hal_config_stage(priv->ctx, WDT_STAGE0, + priv->timeout_ticks, + priv->action); + wdt_hal_write_protect_enable(priv->ctx); } #ifdef CONFIG_ESPRESSIF_XTWDT @@ -627,9 +626,9 @@ static int wdt_settimeout(struct watchdog_lowerhalf_s *lower, return -ERANGE; } - timeout = timeout * xtal32k_cycles; + priv->timeout_ticks = timeout * xtal32k_cycles; xt_wdt_ll_set_timeout(((xt_wdt_hal_context_t *)priv->ctx)->dev, - timeout); + priv->timeout_ticks); return OK; } #endif @@ -695,20 +694,11 @@ static xcpt_t wdt_capture(struct watchdog_lowerhalf_s *lower, xcpt_t handler) if (IS_XTWDT(priv) != true) { - if (priv->peripheral == TIMER) - { - timeout = MWDT_TIMEOUT_MS(priv->timeout); - } - else - { - timeout = RWDT_TIMEOUT_MS(priv->timeout); - } - priv->action = WDT_STAGE_ACTION_INT; wdt_hal_config_stage(priv->ctx, WDT_STAGE0, - timeout, - priv->action); + priv->timeout_ticks, + priv->action); } } @@ -732,12 +722,10 @@ static xcpt_t wdt_capture(struct watchdog_lowerhalf_s *lower, xcpt_t handler) { if (priv->peripheral == TIMER) { - timeout = MWDT_TIMEOUT_MS(priv->timeout); priv->action = WDT_STAGE_ACTION_RESET_SYSTEM; } else { - timeout = RWDT_TIMEOUT_MS(priv->timeout); priv->action = WDT_STAGE_ACTION_RESET_RTC; } @@ -746,8 +734,8 @@ static xcpt_t wdt_capture(struct watchdog_lowerhalf_s *lower, xcpt_t handler) /* Then configure it to reset on WDT expiration */ wdt_hal_config_stage(priv->ctx, WDT_STAGE0, - timeout, - priv->action); + priv->timeout_ticks, + priv->action); } #ifdef CONFIG_ESPRESSIF_XTWDT else @@ -844,7 +832,7 @@ static int wdt_handler(int irq, void *context, void *arg) /* Run the user callback */ - priv->handler(irq, context, priv->upper); + priv->handler(priv->irq, context, priv->upper); WDT_WP_DISABLE(priv); @@ -856,6 +844,7 @@ static int wdt_handler(int irq, void *context, void *arg) } WDT_WP_ENABLE(priv); + return OK; } @@ -889,27 +878,41 @@ int esp_wdt_initialize(const char *devpath, enum esp_wdt_inst_e wdt_id) #ifdef CONFIG_ESPRESSIF_MWDT0 case ESP_WDT_MWDT0: { + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) + { + if (ref_count == 0) + { + timg_ll_enable_bus_clock(0, true); + timg_ll_reset_register(0); + } + } + lower = &g_esp_mwdt0_lowerhalf; - periph_module_enable(PERIPH_TIMG0_MODULE); wdt_hal_init(lower->ctx, WDT_MWDT0, MWDT_LL_DEFAULT_CLK_PRESCALER, true); break; } - #endif #ifdef CONFIG_ESPRESSIF_MWDT1 case ESP_WDT_MWDT1: { + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG1_MODULE, ref_count) + { + if (ref_count == 0) + { + timg_ll_enable_bus_clock(1, true); + timg_ll_reset_register(1); + } + } + lower = &g_esp_mwdt1_lowerhalf; - periph_module_enable(PERIPH_TIMG1_MODULE); wdt_hal_init(lower->ctx, WDT_MWDT1, MWDT_LL_DEFAULT_CLK_PRESCALER, true); break; } - #endif #ifdef CONFIG_ESPRESSIF_RWDT @@ -917,7 +920,6 @@ int esp_wdt_initialize(const char *devpath, enum esp_wdt_inst_e wdt_id) { lower = &g_esp_rwdt_lowerhalf; wdt_hal_init(lower->ctx, WDT_RWDT, 0, true); - esp_rtcioirqenable(lower->irq); break; } #endif @@ -926,7 +928,6 @@ int esp_wdt_initialize(const char *devpath, enum esp_wdt_inst_e wdt_id) case ESP_WDT_XTAL32K: { lower = &g_esp_xtwdt_lowerhalf; - esp_rtcioirqenable(lower->irq); xt_wdt_hal_init((xt_wdt_hal_context_t *)lower->ctx, (xt_wdt_hal_config_t *)&cfg); if (cfg.auto_backup_clk_enable) @@ -977,24 +978,51 @@ int esp_wdt_initialize(const char *devpath, enum esp_wdt_inst_e wdt_id) return -EEXIST; } - esp_setup_irq(lower->periph, - ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); - - /* Attach the handler for the timer IRQ */ - - irq_attach(lower->irq, (xcpt_t)wdt_handler, lower); - /* Enable the allocated CPU interrupt */ - if (IS_XTWDT(lower) != true) + if (IS_MWDT(lower) == true || +#ifndef CONFIG_ARCH_CHIP_ESP32C3 + IS_RWDT(lower) == true +#else + false +#endif + ) { + int cpuint = esp_setup_irq(lower->periph, + ESP_IRQ_PRIORITY_DEFAULT, + ESP_IRQ_TRIGGER_LEVEL, + wdt_handler, + lower); + if (cpuint < 0) + { + tmrerr("ERROR: Failed to allocate a CPU interrupt"); + return -EINVAL; + } + up_enable_irq(lower->irq); } - else + +#if defined(CONFIG_ESPRESSIF_XTWDT) || defined(CONFIG_ESPRESSIF_RWDT) + if (IS_XTWDT(lower) == true || +#ifdef CONFIG_ARCH_CHIP_ESP32C3 + IS_RWDT(lower) == true +#else + false +#endif + ) { - up_enable_irq(ESP_IRQ_RTC_CORE); + int ret = esp_rtcioirqattach(lower->irq, wdt_handler, lower); + if (ret != OK) + { + esp_rtcioirqdisable(lower->irq); + tmrerr("ERROR: Failed to associate an IRQ Number"); + return -EINVAL; + } + + esp_rtcioirqenable(lower->irq); + up_enable_irq(ESP_SOURCE2IRQ(ESP_IRQ_RTC_CORE)); } +#endif return OK; } diff --git a/arch/risc-v/src/common/espressif/esp_wifi_api.c b/arch/risc-v/src/common/espressif/esp_wifi_api.c index 24e8887074f82..7b08296c67ab9 100644 --- a/arch/risc-v/src/common/espressif/esp_wifi_api.c +++ b/arch/risc-v/src/common/espressif/esp_wifi_api.c @@ -282,7 +282,16 @@ int esp_wifi_api_start(uint32_t start_mode) goto errout; } - wlinfo("Wi-Fi started with mode=%d\n", mode); + ret = esp_wifi_get_mode(¤t_mode); + if (ret) + { + wlerr("Failed to get Wi-Fi mode ret=%d. Check if initialized\n", + ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + wlinfo("Wi-Fi started with mode=%d\n", current_mode); errout: esp_wifi_lock(false); diff --git a/arch/risc-v/src/common/espressif/esp_wlan_netdev.c b/arch/risc-v/src/common/espressif/esp_wlan_netdev.c index 6d66537d4ef20..d8a19dfd767f9 100644 --- a/arch/risc-v/src/common/espressif/esp_wlan_netdev.c +++ b/arch/risc-v/src/common/espressif/esp_wlan_netdev.c @@ -970,14 +970,14 @@ void IRAM_ATTR esp_wifi_tx_done_cb(uint8_t ifidx, bool txstatus) { #ifdef ESP_WLAN_HAS_STA - if (ifidx == ESP_IF_WIFI_STA) + if (ifidx == WIFI_IF_STA) { netdev_lower_txdone(&g_wlan_sta.dev); } #endif #ifdef ESP_WLAN_HAS_SOFTAP - if (ifidx == ESP_IF_WIFI_AP) + if (ifidx == WIFI_IF_AP) { netdev_lower_txdone(&g_wlan_softap.dev); } diff --git a/arch/risc-v/src/common/espressif/esp_ws2812.c b/arch/risc-v/src/common/espressif/esp_ws2812.c index 642b9bf37d73a..1e4f74d9186fc 100644 --- a/arch/risc-v/src/common/espressif/esp_ws2812.c +++ b/arch/risc-v/src/common/espressif/esp_ws2812.c @@ -34,6 +34,10 @@ #include #include "hal/rmt_types.h" + +#include "esp_private/rmt.h" +#include "driver/rmt_common.h" + #include "soc/soc.h" #include "esp_rmt.h" @@ -67,6 +71,21 @@ struct rgbw_led_s }; }; +struct rmt_dev_lowerhalf_s +{ + /* The following block is part of the upper-half device struct */ + + const struct rmt_ops_s *ops; + struct circbuf_s *circbuf; + sem_t *recvsem; + int minor; + + /* The following is private to the ESP32 RMT driver */ + + rmt_channel_handle_t handle; + rmt_encoder_handle_t encoder; +}; + struct esp_ws2812_dev_s { struct rmt_dev_s *rmt; @@ -112,12 +131,6 @@ static int esp_write(struct file *filep, const char *data, size_t len); * Private Data ****************************************************************************/ -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT -extern uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; -#else -extern uint32_t g_rmt_source_clock_hz; -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -151,15 +164,19 @@ static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev, uint16_t t0l; uint16_t t1h; uint16_t t1l; - uint32_t clock_period_ps; + uint32_t resolution_hz; uint32_t rmt_period_ps; + esp_err_t ret; + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev->rmt; -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT - clock_period_ps = 1000000000000 / g_rmt_source_clock_hz[dev->rmt->minor]; -#else - clock_period_ps = 1000000000000 / g_rmt_source_clock_hz; -#endif - rmt_period_ps = clock_period_ps / RMT_DEFAULT_CLK_DIV; + ret = rmt_get_channel_resolution(priv->handle, &resolution_hz); + if (ret != ESP_OK) + { + lederr("esp_ws2812 map_byte_to_words failed: %d\n", ret); + return 0; + } + + rmt_period_ps = 1000000000000 / resolution_hz; /* Calculate the RMT period to encode WS2812 frames */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c index c308a781659b8..03397c9c2539e 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c @@ -419,4 +419,3 @@ void esp32c3_gpioirqdisable(int irq) up_enable_irq(ESP32C3_IRQ_GPIO); } #endif - diff --git a/arch/risc-v/src/esp32c3/esp_ble_adapter.c b/arch/risc-v/src/esp32c3/esp_ble_adapter.c index 828b82c88edd3..b972716fd7cd3 100644 --- a/arch/risc-v/src/esp32c3/esp_ble_adapter.c +++ b/arch/risc-v/src/esp32c3/esp_ble_adapter.c @@ -113,38 +113,10 @@ # define BLE_TASK_EVENT_QUEUE_LEN 8 #endif -#ifdef CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS -# define NR_IRQSTATE_FLAGS CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS -#else -# define NR_IRQSTATE_FLAGS 3 -#endif - /**************************************************************************** * Private Types ****************************************************************************/ -/* Pack using bitfields for better memory use */ - -typedef struct vector_desc_s vector_desc_t; - -struct vector_desc_s -{ - int flags: 16; - unsigned int cpu: 1; - unsigned int intno: 5; - int source: 8; - void *shared_vec_info; - vector_desc_t *next; -}; - -/** Interrupt handler associated data structure */ - -struct intr_handle_data_t -{ - vector_desc_t *vector_desc; - void *shared_vector_desc; -}; - /* VHCI function interface */ typedef struct vhci_host_callback_s @@ -153,16 +125,6 @@ typedef struct vhci_host_callback_s int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ } vhci_host_callback_t; -typedef struct -{ - int source; /* ISR source */ - int flags; /* ISR alloc flag */ - void (*fn)(void *); /* ISR function */ - void *arg; /* ISR function args */ - intr_handle_t *handle; /* ISR handle */ - esp_err_t ret; -} btdm_isr_alloc_t; - /* BLE OS function */ struct osi_funcs_s @@ -652,11 +614,9 @@ static DRAM_ATTR void * g_light_sleep_pm_lock; /* BT interrupt private data */ -static sq_queue_t g_ble_int_flags_free; +irqstate_t g_ble_int_flags; -static sq_queue_t g_ble_int_flags_used; - -static struct irqstate_list_s g_ble_int_flags[NR_IRQSTATE_FLAGS]; +static int g_ble_int_count = 0; /* Cached queue control variables */ @@ -774,9 +734,7 @@ static int interrupt_alloc_wrapper(int cpu_id, void *arg, void **ret_handle) { - btdm_isr_alloc_t *p; - struct intr_handle_data_t *handle; - vector_desc_t *vd; + struct intr_adapter_to_nuttx *isr_adapter_args; int ret = OK; int cpuint; int irq; @@ -784,57 +742,24 @@ static int interrupt_alloc_wrapper(int cpu_id, wlinfo("cpu_id=%d , source=%d , handler=%p, arg=%p, ret_handle=%p\n", cpu_id, source, handler, arg, ret_handle); - p = kmm_calloc(1, sizeof(btdm_isr_alloc_t)); - if (p == NULL) + isr_adapter_args = kmm_calloc(1, sizeof(struct intr_adapter_to_nuttx)); + if (isr_adapter_args == NULL) { - return ESP_ERR_NOT_FOUND; + irqerr("Failed to kmm_calloc\n"); + return ESP_ERR_NO_MEM; } - handle = kmm_calloc(1, sizeof(struct intr_handle_data_t)); - if (handle == NULL) - { - free(p); - return ESP_ERR_NOT_FOUND; - } - - p->source = source; - p->flags = ESP_INTR_FLAG_LEVEL2 | ESP_INTR_FLAG_IRAM; - p->fn = handler; - p->arg = arg; - p->handle = (intr_handle_t *)ret_handle; + isr_adapter_args->handler = handler; + isr_adapter_args->arg = arg; - cpuint = esp_setup_irq(source, 2, ESP_IRQ_TRIGGER_LEVEL); + cpuint = esp_setup_irq(source, 2, ESP_IRQ_TRIGGER_LEVEL, esp_int_adpt_cb, + isr_adapter_args); if (cpuint < 0) { - kmm_free(handle); - return ESP_ERR_NOT_FOUND; - } - - vd = kmm_calloc(1, sizeof(vector_desc_t)); - if (vd == NULL) - { - kmm_free(handle); return ESP_ERR_NOT_FOUND; } - vd->intno = cpuint; - vd->cpu = cpu_id; - vd->source = source; - - irq = esp_get_irq(cpuint); - - handle->vector_desc = vd; - handle->shared_vector_desc = vd->shared_vec_info; - - *(p->handle) = handle; - - ret = irq_attach(irq, esp_int_adpt_cb, p); - if (ret != OK) - { - kmm_free(p); - kmm_free(handle); - return ESP_ERR_NOT_FOUND; - } + (*ret_handle) = (void *)esp_get_handle(cpu_id, ESP_SOURCE2IRQ(source)); return ESP_OK; } @@ -879,13 +804,12 @@ static void IRAM_ATTR global_interrupt_disable(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_free); - - ASSERT(irqstate != NULL); - - irqstate->flags = enter_critical_section(); + if (g_ble_int_count == 0) + { + g_ble_int_flags = enter_critical_section(); + } - sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_used); + g_ble_int_count++; } /**************************************************************************** @@ -907,13 +831,12 @@ static void IRAM_ATTR global_interrupt_restore(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_used); + g_ble_int_count--; - ASSERT(irqstate != NULL); - - leave_critical_section(irqstate->flags); - - sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_free); + if (g_ble_int_count == 0) + { + leave_critical_section(g_ble_int_flags); + } } /**************************************************************************** @@ -1099,7 +1022,7 @@ static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms) if (ret) { - wlerr("ERROR: Failed to wait sem in %lu ticks. Error=%d\n", + wlerr("ERROR: Failed to wait sem in %" PRIu32 " ticks. Error=%d\n", MSEC2TICK(block_time_ms), ret); } @@ -1298,7 +1221,8 @@ static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) else { wlerr("Failed to create queue cache." - " Please incresase BLE_TASK_EVENT_QUEUE_LEN to, at least, %ld", + " Please incresase BLE_TASK_EVENT_QUEUE_LEN to, at least, " + "%" PRIu32 "", queue_len); return NULL; } @@ -2035,30 +1959,7 @@ static void * coex_schm_curr_phase_get_wrapper(void) static int interrupt_enable_wrapper(void *handle) { - intr_handle_t isr = (intr_handle_t)handle; - int ret = ESP_OK; - int cpuint; - int irq; - - cpuint = isr->vector_desc->intno; - - irq = esp_get_irq(cpuint); - if (irq == 127) - { - wlerr("CPU interrupt is not assigned!\n"); - return ESP_ERR_INVALID_ARG; - } - - ret = esp_irq_set_iram_isr(irq); - if (ret != ESP_OK) - { - wlerr("Failed to set IRAM ISR\n"); - return ESP_ERR_INVALID_ARG; - } - - up_enable_irq(irq); - - return ret == OK ? ESP_OK : ESP_ERR_INVALID_ARG; + return esp_intr_enable((intr_handle_t)handle); } /**************************************************************************** @@ -2079,23 +1980,7 @@ static int interrupt_enable_wrapper(void *handle) static int interrupt_disable_wrapper(void *handle) { - intr_handle_t isr = (intr_handle_t)handle; - int ret = ESP_OK; - int cpuint; - int irq; - - cpuint = isr->vector_desc->intno; - - irq = esp_get_irq(cpuint); - if (irq == 127) - { - wlerr("CPU interrupt is not assigned!\n"); - return ESP_ERR_INVALID_ARG; - } - - up_disable_irq(irq); - - return ret == OK ? ESP_OK : ESP_ERR_INVALID_ARG; + return esp_intr_disable((intr_handle_t)handle); } /**************************************************************************** @@ -2338,7 +2223,10 @@ static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) * BT interrupt adapter callback function * * Input Parameters: - * arg - interrupt adapter private data + * irq - IRQ associated to that interrupt. + * context - Interrupt register state save info. + * arg - A pointer to the argument provided when the interrupt + * was registered. * * Returned Value: * NuttX error code @@ -2347,9 +2235,11 @@ static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) { - btdm_isr_alloc_t *p = (btdm_isr_alloc_t *)arg; + struct intr_adapter_to_nuttx *isr_adapter_args; + + isr_adapter_args = (struct intr_adapter_to_nuttx *)arg; - p->fn(p->arg); + isr_adapter_args->handler(isr_adapter_args->arg); return OK; } @@ -3091,13 +2981,7 @@ int esp_bt_controller_init(void) int i; int err; - sq_init(&g_ble_int_flags_free); - sq_init(&g_ble_int_flags_used); - - for (i = 0; i < NR_IRQSTATE_FLAGS; i++) - { - sq_addlast((sq_entry_t *)&g_ble_int_flags[i], &g_ble_int_flags_free); - } + g_ble_int_count = 0; if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { @@ -3203,10 +3087,10 @@ int esp_bt_controller_init(void) } #if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED) - scan_stack_enable_adv_flow_ctrl_vs_cmd(true); - adv_stack_enable_clear_legacy_adv_vs_cmd(true); - adv_filter_stack_enable_dup_exc_list_vs_cmd(true); - chan_sel_stack_enable_set_csa_vs_cmd(true); + scan_stack_enable_adv_flow_ctrl_vs_cmd(true); + adv_stack_enable_clear_legacy_adv_vs_cmd(true); + adv_filter_stack_enable_dup_exc_list_vs_cmd(true); + chan_sel_stack_enable_set_csa_vs_cmd(true); #endif g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; @@ -3249,10 +3133,10 @@ int esp_bt_controller_deinit(void) } #if (CONFIG_BT_BLUEDROID_ENABLED || CONFIG_BT_NIMBLE_ENABLED) - scan_stack_enable_adv_flow_ctrl_vs_cmd(false); - adv_stack_enable_clear_legacy_adv_vs_cmd(false); - adv_filter_stack_enable_dup_exc_list_vs_cmd(false); - chan_sel_stack_enable_set_csa_vs_cmd(false); + scan_stack_enable_adv_flow_ctrl_vs_cmd(false); + adv_stack_enable_clear_legacy_adv_vs_cmd(false); + adv_filter_stack_enable_dup_exc_list_vs_cmd(false); + chan_sel_stack_enable_set_csa_vs_cmd(false); #endif btdm_controller_deinit(); diff --git a/arch/risc-v/src/esp32c3/esp_wifi_adapter.c b/arch/risc-v/src/esp32c3/esp_wifi_adapter.c index 2bc47339566a9..5d360a68a38f2 100644 --- a/arch/risc-v/src/esp32c3/esp_wifi_adapter.c +++ b/arch/risc-v/src/esp32c3/esp_wifi_adapter.c @@ -46,8 +46,10 @@ #include "esp_phy_init.h" #include "esp_private/periph_ctrl.h" #include "os.h" +#include "platform/os.h" #include "private/esp_coexist_internal.h" #include "rom/ets_sys.h" +#include "riscv/interrupt.h" #include "espressif/esp_wifi_utils.h" #include "esp_coex_adapter.h" @@ -64,21 +66,23 @@ * Private Types ****************************************************************************/ -/* Wi-Fi interrupt adapter private data */ +typedef struct shared_vector_desc_t shared_vector_desc_t; +typedef struct vector_desc_t vector_desc_t; -struct irq_adpt +typedef struct intr_handle_data_t { - void (*func)(void *arg); /* Interrupt callback function */ - void *arg; /* Interrupt private data */ -}; - -/* Wi-Fi message queue private data */ + vector_desc_t *vector_desc; + shared_vector_desc_t *shared_vector_desc; +} intr_handle_data_t; -struct mq_adpt +struct vector_desc_t { - struct file mq; /* Message queue handle */ - uint32_t msgsize; /* Message size */ - char name[16]; /* Message queue name */ + int flags: 16; + unsigned int cpu: 1; + unsigned int intno: 5; + int source: 16; + shared_vector_desc_t *shared_vec_info; + vector_desc_t *next; }; /**************************************************************************** @@ -216,7 +220,6 @@ static void *event_group_create_wrapper(void); static void event_group_delete_wrapper(void *event); static uint32_t event_group_set_bits_wrapper(void *event, uint32_t bits); static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits); -static int esp_int_adpt_cb(int irq, void *context, void *arg); static int esp_nvs_commit(uint32_t handle); static int esp_nvs_erase_key(uint32_t handle, const char *key); static int esp_nvs_get_blob(uint32_t handle, @@ -545,12 +548,40 @@ static void wifi_delete_queue_wrapper(void *queue) static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio) { + intr_handle_t handle; + int irq = ESP_SOURCE2IRQ(intr_source); + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", cpu_no, intr_source, intr_num, intr_prio); - esp_route_intr(intr_source, intr_num, intr_prio, ESP_IRQ_TRIGGER_LEVEL); - esp_set_irq(ESP_SOURCE2IRQ(intr_source), intr_num); + esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num); + esprv_int_set_priority(intr_num, intr_prio); + esprv_int_set_type(intr_num, INTR_TYPE_LEVEL); + + handle = kmm_calloc(1, sizeof(intr_handle_data_t)); + if (handle == NULL) + { + wlerr("Failed to kmm_calloc\n"); + return; + } + + handle->vector_desc = kmm_calloc(1, sizeof(vector_desc_t)); + if (handle->vector_desc == NULL) + { + wlerr("Failed to kmm_calloc\n"); + kmm_free(handle); + return; + } + + handle->vector_desc->intno = intr_num; + handle->vector_desc->cpu = cpu_no; + handle->vector_desc->source = intr_source; + handle->vector_desc->shared_vec_info = NULL; + handle->vector_desc->next = NULL; + handle->shared_vector_desc = NULL; + + esp_set_handle(cpu_no, irq, handle); } /**************************************************************************** @@ -592,40 +623,7 @@ static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, static void set_isr_wrapper(int32_t n, void *f, void *arg) { - int ret; - uint32_t tmp; - struct irq_adpt *adapter; - int irq = esp_get_irq(n); - - wlinfo("n=%ld f=%p arg=%p irq=%d\n", n, f, arg, irq); - - if (g_irqvector[irq].handler && - g_irqvector[irq].handler != irq_unexpected_isr) - { - wlinfo("irq=%d has been set handler=%p\n", irq, - g_irqvector[irq].handler); - return; - } - - tmp = sizeof(struct irq_adpt); - adapter = kmm_malloc(tmp); - if (!adapter) - { - wlerr("Failed to alloc %ld memory\n", tmp); - PANIC(); - return; - } - - adapter->func = f; - adapter->arg = arg; - - ret = irq_attach(irq, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } + intr_handler_set(n, (intr_handler_t)f, arg); } /**************************************************************************** @@ -646,11 +644,11 @@ static void set_isr_wrapper(int32_t n, void *f, void *arg) static void enable_intr_wrapper(uint32_t intr_mask) { int cpuint = __builtin_ffs(intr_mask) - 1; - int irq = esp_get_irq(cpuint); + int irq = esp_cpuint_to_irq(cpuint, this_cpu()); wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); - up_enable_irq(irq); + esprv_int_enable(intr_mask); } /**************************************************************************** @@ -671,7 +669,7 @@ static void enable_intr_wrapper(uint32_t intr_mask) static void disable_intr_wrapper(uint32_t intr_mask) { int cpuint = __builtin_ffs(intr_mask) - 1; - int irq = esp_get_irq(cpuint); + int irq = esp_cpuint_to_irq(cpuint, this_cpu()); wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); @@ -2338,33 +2336,6 @@ static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits) return false; } -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * This is the callback function for the Wi-Fi interrupt adapter. It - * retrieves the adapter from the argument, then calls the function - * stored in the adapter with its argument. - * - * Input Parameters: - * irq - The IRQ number that caused this interrupt. - * context - The register context at the time of the interrupt. - * arg - A pointer to the interrupt adapter's private data. - * - * Returned Value: - * Always returns 0. - * - ****************************************************************************/ - -static int esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt *adapter = (struct irq_adpt *)arg; - - adapter->func(adapter->arg); - - return 0; -} - /**************************************************************************** * Name: esp_nvs_commit * diff --git a/arch/risc-v/src/esp32c3/esp_wireless.c b/arch/risc-v/src/esp32c3/esp_wireless.c index 39543689b62b2..df686e609cbd8 100644 --- a/arch/risc-v/src/esp32c3/esp_wireless.c +++ b/arch/risc-v/src/esp32c3/esp_wireless.c @@ -297,7 +297,11 @@ int esp_wireless_init(void) return OK; } - priv->cpuint = esp_setup_irq(SWI_PERIPH, ESP_IRQ_PRIORITY_DEFAULT, 0); + priv->cpuint = esp_setup_irq(SWI_PERIPH, + ESP_IRQ_PRIORITY_DEFAULT, + 0, + esp_swi_irq, + NULL); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -309,16 +313,6 @@ int esp_wireless_init(void) return ret; } - ret = irq_attach(SWI_IRQ, esp_swi_irq, NULL); - if (ret < 0) - { - esp_teardown_irq(SWI_PERIPH, priv->cpuint); - leave_critical_section(flags); - wlerr("ERROR: Failed to attach IRQ ret=%d\n", ret); - - return ret; - } - list_initialize(&priv->sc_list); list_initialize(&priv->qc_list); diff --git a/arch/risc-v/src/esp32c3/hal_esp32c3.mk b/arch/risc-v/src/esp32c3/hal_esp32c3.mk index 16f69b315e9fb..bf1a8d4555dc0 100644 --- a/arch/risc-v/src/esp32c3/hal_esp32c3.mk +++ b/arch/risc-v/src/esp32c3/hal_esp32c3.mk @@ -25,7 +25,6 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include @@ -39,14 +38,62 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)interface INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_blockdev$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)etm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_intr$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include @@ -57,11 +104,13 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private @@ -76,19 +125,29 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)priv_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_flash_chips INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_libc$(DELIM)platform_include ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include endif @@ -128,19 +187,24 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)gdma.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src$(DELIM)gdma.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)intr_alloc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)adc2_init_cal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c @@ -153,58 +217,63 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_console.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ext_mem_layout.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)lib_printf.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_print.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_serial_output.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup_funcs.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal_ahb_v1.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal_top.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_ahb_v1.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_top.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sdm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal_sja1000.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_gpspi.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_encrypt_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)xt_wdt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)i2c_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)i2s_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)twai_hal_v1.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)wdt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_gpspi.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)xt_wdt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c @@ -213,7 +282,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)instruction_decode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt_intc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_noos.c @@ -235,24 +304,37 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)flash_brownout_hook.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)cache_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)lldesc.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)interrupts.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_hmac.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_lock.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_periph_clk.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)src$(DELIM)uart_wakeup.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)rtc_io.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_bytes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_copy.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_simple.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c # Bootloader files @@ -269,16 +351,12 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c LDFLAGS += --wrap=bootloader_print_banner else diff --git a/arch/risc-v/src/esp32c6/esp_wifi_adapter.c b/arch/risc-v/src/esp32c6/esp_wifi_adapter.c index 82803644235da..4b6f932050f40 100644 --- a/arch/risc-v/src/esp32c6/esp_wifi_adapter.c +++ b/arch/risc-v/src/esp32c6/esp_wifi_adapter.c @@ -73,11 +73,13 @@ #include "soc/rtc_cntl_periph.h" #include "esp_private/periph_ctrl.h" #include "esp_private/esp_clk.h" +#include "platform/os.h" #include "os.h" #include "esp_smartconfig.h" #include "private/esp_coexist_internal.h" #include "rom/ets_sys.h" #include "private/esp_modem_wrapper.h" +#include "riscv/interrupt.h" #if SOC_PM_MODEM_RETENTION_BY_REGDMA #include "esp_private/esp_regdma.h" @@ -100,21 +102,23 @@ * Private Types ****************************************************************************/ -/* Wi-Fi interrupt adapter private data */ +typedef struct shared_vector_desc_t shared_vector_desc_t; +typedef struct vector_desc_t vector_desc_t; -struct irq_adpt +typedef struct intr_handle_data_t { - void (*func)(void *arg); /* Interrupt callback function */ - void *arg; /* Interrupt private data */ -}; - -/* Wi-Fi message queue private data */ + vector_desc_t *vector_desc; + shared_vector_desc_t *shared_vector_desc; +} intr_handle_data_t; -struct mq_adpt +struct vector_desc_t { - struct file mq; /* Message queue handle */ - uint32_t msgsize; /* Message size */ - char name[16]; /* Message queue name */ + int flags: 16; + unsigned int cpu: 1; + unsigned int intno: 5; + int source: 16; + shared_vector_desc_t *shared_vec_info; + vector_desc_t *next; }; /**************************************************************************** @@ -250,7 +254,6 @@ static void *event_group_create_wrapper(void); static void event_group_delete_wrapper(void *event); static uint32_t event_group_set_bits_wrapper(void *event, uint32_t bits); static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits); -static int esp_int_adpt_cb(int irq, void *context, void *arg); static int esp_nvs_commit(uint32_t handle); static int esp_nvs_erase_key(uint32_t handle, const char *key); static int esp_nvs_get_blob(uint32_t handle, @@ -579,12 +582,40 @@ static void wifi_delete_queue_wrapper(void *queue) static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio) { + intr_handle_t handle; + int irq = ESP_SOURCE2IRQ(intr_source); + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", cpu_no, intr_source, intr_num, intr_prio); - esp_route_intr(intr_source, intr_num, intr_prio, ESP_IRQ_TRIGGER_LEVEL); - esp_set_irq(ESP_SOURCE2IRQ(intr_source), intr_num); + esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num); + esprv_int_set_priority(intr_num, intr_prio); + esprv_int_set_type(intr_num, INTR_TYPE_LEVEL); + + handle = kmm_calloc(1, sizeof(intr_handle_data_t)); + if (handle == NULL) + { + wlerr("Failed to kmm_calloc\n"); + return; + } + + handle->vector_desc = kmm_calloc(1, sizeof(vector_desc_t)); + if (handle->vector_desc == NULL) + { + wlerr("Failed to kmm_calloc\n"); + kmm_free(handle); + return; + } + + handle->vector_desc->intno = intr_num; + handle->vector_desc->cpu = cpu_no; + handle->vector_desc->source = intr_source; + handle->vector_desc->shared_vec_info = NULL; + handle->vector_desc->next = NULL; + handle->shared_vector_desc = NULL; + + esp_set_handle(cpu_no, irq, handle); } /**************************************************************************** @@ -626,40 +657,7 @@ static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, static void set_isr_wrapper(int32_t n, void *f, void *arg) { - int ret; - uint32_t tmp; - struct irq_adpt *adapter; - int irq = esp_get_irq(n); - - wlinfo("n=%ld f=%p arg=%p irq=%d\n", n, f, arg, irq); - - if (g_irqvector[irq].handler && - g_irqvector[irq].handler != irq_unexpected_isr) - { - wlinfo("irq=%d has been set handler=%p\n", irq, - g_irqvector[irq].handler); - return; - } - - tmp = sizeof(struct irq_adpt); - adapter = kmm_malloc(tmp); - if (!adapter) - { - wlerr("Failed to alloc %ld memory\n", tmp); - PANIC(); - return; - } - - adapter->func = f; - adapter->arg = arg; - - ret = irq_attach(irq, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } + intr_handler_set(n, (intr_handler_t)f, arg); } /**************************************************************************** @@ -680,11 +678,11 @@ static void set_isr_wrapper(int32_t n, void *f, void *arg) static void enable_intr_wrapper(uint32_t intr_mask) { int cpuint = __builtin_ffs(intr_mask) - 1; - int irq = esp_get_irq(cpuint); + int irq = esp_cpuint_to_irq(cpuint, this_cpu()); wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); - up_enable_irq(irq); + esprv_int_enable(intr_mask); } /**************************************************************************** @@ -705,7 +703,7 @@ static void enable_intr_wrapper(uint32_t intr_mask) static void disable_intr_wrapper(uint32_t intr_mask) { int cpuint = __builtin_ffs(intr_mask) - 1; - int irq = esp_get_irq(cpuint); + int irq = esp_cpuint_to_irq(cpuint, this_cpu()); wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); @@ -2326,33 +2324,6 @@ static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits) return false; } -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * This is the callback function for the Wi-Fi interrupt adapter. It - * retrieves the adapter from the argument, then calls the function - * stored in the adapter with its argument. - * - * Input Parameters: - * irq - The IRQ number that caused this interrupt. - * context - The register context at the time of the interrupt. - * arg - A pointer to the interrupt adapter's private data. - * - * Returned Value: - * Always returns 0. - * - ****************************************************************************/ - -static int esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt *adapter = (struct irq_adpt *)arg; - - adapter->func(adapter->arg); - - return 0; -} - /**************************************************************************** * Name: esp_nvs_commit * diff --git a/arch/risc-v/src/esp32c6/hal_esp32c6.mk b/arch/risc-v/src/esp32c6/hal_esp32c6.mk index 80f1c99caecf2..e7835860f51a1 100644 --- a/arch/risc-v/src/esp32c6/hal_esp32c6.mk +++ b/arch/risc-v/src/esp32c6/hal_esp32c6.mk @@ -25,8 +25,6 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include @@ -39,13 +37,61 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)interface INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_blockdev$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)etm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_intr$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include @@ -54,11 +100,13 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private @@ -72,14 +120,20 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)priv_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_flash_chips INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared @@ -87,7 +141,13 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common$(DELIM)include - +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_libc$(DELIM)platform_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include @@ -95,8 +155,6 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)private_include ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include endif @@ -113,7 +171,7 @@ ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM) ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.phy.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.pp.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld -ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.wdt.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)rom.wdt.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.heap.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)ld$(DELIM)rom.api.ld @@ -145,19 +203,23 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)gdma.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src$(DELIM)gdma.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)intr_alloc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)modem_clock.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_console.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_retention.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_system_peripheral.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu.c @@ -166,9 +228,11 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)pau_regdma.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)regdma_link.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)io_mux.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ocode_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)peripheral_domain_pd.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_sleep.c @@ -178,65 +242,71 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)brownout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ext_mem_layout.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)lib_printf.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_impl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_print.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_serial_output.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_hp_regi2c_$(CHIP_SERIES).c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup_funcs.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)apm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)apm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal_ahb_v1.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal_top.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_ahb_v1.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_top.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)lp_timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sdm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal_sja1000.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)pcnt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)i2c_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)i2s_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)twai_hal_v1.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_gpspi.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)mcpwm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)wdt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_gpspi.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_encrypt_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rtc_io_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)rtc_io_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_slave_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_slave_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)modem_clock_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)pau_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)pau_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c @@ -245,28 +315,32 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)instruction_decode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt_plic.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)rv_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)lldesc.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)interrupts.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_hmac.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_lock.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_periph_clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_noos.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_app.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_chip_generic.c @@ -284,13 +358,22 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)lp_core.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared$(DELIM)ulp_lp_core_memory_shared.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)lp_core$(DELIM)shared$(DELIM)ulp_lp_core_lp_timer_shared.c - -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)src$(DELIM)uart_wakeup.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_bytes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_copy.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_simple.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)rtc_io.c CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)esp32c6$(DELIM)sleep_cpu_asm.S +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c + # Bootloader files CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c @@ -306,16 +389,12 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c LDFLAGS += --wrap=bootloader_print_banner diff --git a/arch/risc-v/src/esp32h2/hal_esp32h2.mk b/arch/risc-v/src/esp32h2/hal_esp32h2.mk index d4abd2146cfb9..ab23be666c130 100644 --- a/arch/risc-v/src/esp32h2/hal_esp32h2.mk +++ b/arch/risc-v/src/esp32h2/hal_esp32h2.mk @@ -25,7 +25,6 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include @@ -37,25 +36,75 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)interface INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_blockdev$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)etm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_intr$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)ld INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include @@ -67,24 +116,36 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)priv_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_flash_chips INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)driver$(DELIM)twai$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)driver$(DELIM)spi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_libc$(DELIM)platform_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include endif @@ -98,7 +159,7 @@ ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM) ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.systimer.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld -ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.wdt.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)rom.wdt.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)ld$(DELIM)rom.api.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.heap.ld @@ -127,29 +188,35 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)gdma.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src$(DELIM)gdma.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)intr_alloc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)modem_clock.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_console.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_retention.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_system_peripheral.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_clock.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)regdma_link.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)pau_regdma.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)peripheral_domain_pd.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_sleep.c @@ -160,60 +227,65 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)brownout.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)vbat.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ext_mem_layout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_print.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_serial_output.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_regi2c_$(CHIP_SERIES).c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup_funcs.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)apm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)apm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal_ahb_v1.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gdma_hal_top.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_ahb_v1.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_top.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)lp_timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)pcnt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)i2c_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)i2s_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)mcpwm_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sdm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal_sja1000.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_gpspi.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_encrypt_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_slave_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)twai_hal_v1.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)wdt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_gpspi.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_slave_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)spi_slave_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)modem_clock_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)pau_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)pau_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c @@ -222,28 +294,32 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt_plic.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)rv_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)lldesc.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)uart_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)instruction_decode.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)spi_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)interrupts.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)timer_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)twai_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)uart_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_hmac.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_lock.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_periph_clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_noos.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_app.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_chip_generic.c @@ -257,10 +333,21 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)flash_mmap.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)flash_brownout_hook.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)cache_utils.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_bytes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_copy.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_simple.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)src$(DELIM)uart_wakeup.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)src$(DELIM)uart_wakeup.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)rtc_io.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)lowpower$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sleep_cpu_asm.S @@ -279,16 +366,12 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c LDFLAGS += --wrap=bootloader_print_banner diff --git a/boards/Kconfig b/boards/Kconfig index 0e96b908b667f..9ff85f9b49201 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -251,7 +251,7 @@ config ARCH_BOARD_ESP32_AUDIO_KIT depends on ARCH_CHIP_ESP32_A1S select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The Ai-Thinker ESP32-Audio-Kit is a board with the ESP32-A1S module powered by ESP32-D0WD-V3 with 16MB of SPI Flash and 8MB PSRAM, and an @@ -263,7 +263,7 @@ config ARCH_BOARD_ESP32_DEVKITC depends on ARCH_CHIP_ESP32WROOM32 || ARCH_CHIP_ESP32WROOM32_8MB || ARCH_CHIP_ESP32WROOM32_16MB || ARCH_CHIP_ESP32WROVER || ARCH_CHIP_ESP32SOLO1 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32 is a dual-core system from Espressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory @@ -291,7 +291,7 @@ config ARCH_BOARD_ESP32_ETHERNETKIT bool "Espressif ESP32 Ethernet Kit" depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide @@ -303,7 +303,7 @@ config ARCH_BOARD_ESP32_LYRAT depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-LyraT is an open-source development board for Espressif Systems' Audio Development Framework (ADF). It is designed for smart speakers and smart-home @@ -313,7 +313,7 @@ config ARCH_BOARD_ESP32_PICO_KIT bool "Espressif ESP32-PICO-KIT V4" depends on ARCH_CHIP_ESP32PICOD4 select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-PICO-KIT is an ESP32-based mini development board produced by Espressif. The core of this board is ESP32-PICO-D4, a System-in-Package module with complete @@ -328,7 +328,7 @@ config ARCH_BOARD_ESP32_SPARROWKIT depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-SPARROW-KIT is a custom-made board based on Espressif's ESP32WROVER chip and built upon the ESP32-WROVERKIT board. It is designed for a university @@ -345,7 +345,7 @@ config ARCH_BOARD_ESP32_WROVERKIT depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP-WROVER-KIT is an ESP32-based development board produced by Espressif. ESP-WROVER-KIT features the following integrated components: @@ -364,7 +364,7 @@ config ARCH_BOARD_LILYGO_TBEAM_LORA_GPS depends on ARCH_CHIP_ESP32WROOM32 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- LilyGO_TBeam_V1.1 LoRa/GPS is an ESP32 board with LoRa and GPS. More info: https://github.com/Xinyuan-LilyGO/LilyGo-LoRa-Series/ @@ -374,7 +374,7 @@ config ARCH_BOARD_TTGO_LORA_ESP32 depends on ARCH_CHIP_ESP32WROOM32 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- TTGO-LoRa-SX1276-ESP32 is an ESP32 board with LoRa. Usually it comes with an OLED display, but there are options without @@ -402,7 +402,7 @@ config ARCH_BOARD_TTGO_T_DISPLAY_ESP32 depends on ARCH_CHIP_ESP32WROOM32 || ARCH_CHIP_ESP32WROOM32_8MB || ARCH_CHIP_ESP32WROOM32_16MB || ARCH_CHIP_ESP32WROVER || ARCH_CHIP_ESP32SOLO1 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- TTGO-T-DISPLAY-ESP32 is an ESP32 with a TFT Display. This port is for board version 1.1, more info: @@ -461,7 +461,7 @@ config ARCH_BOARD_ESP32S2_KALUGA_1 depends on ARCH_CHIP_ESP32S2WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- This is the ESP32-S2-Kaluga-1 board @@ -470,7 +470,7 @@ config ARCH_BOARD_ESP32S2_SAOLA_1 depends on ARCH_CHIP_ESP32S2WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- This is the ESP32-S2-Saola-1 board @@ -479,7 +479,7 @@ config ARCH_BOARD_FRANZININHO_WIFI depends on ARCH_CHIP_ESP32S2WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- Franzininho Wi-Fi is a development board to evaluate the ESP32-S2 SoC @@ -488,7 +488,7 @@ config ARCH_BOARD_ESP32S3_DEVKIT depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3MINI1N8 || ARCH_CHIP_ESP32S3WROOM1N8R2 || ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3CUSTOM || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3 DevKit features the ESP32-S3 CPU with dual Xtensa LX7 cores. It comes in two flavors, the ESP32-S3-DevKitM-1 and the ESP32-S3-DevKitC-1. @@ -500,7 +500,7 @@ config ARCH_BOARD_ESP32S3_8048S043 bool "ESP32-S3 8048S043" depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3MINI1N8 || ARCH_CHIP_ESP32S3WROOM1N8R2 || ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3CUSTOM || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3 8048S043 features the ESP32-S3 CPU with dual Xtensa LX7 cores. @@ -509,7 +509,7 @@ config ARCH_BOARD_ESP32S3_EYE depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3-EYE is a small-sized AI development board produced by Espressif featuring the ESP32-S3 CPU with a 2-Megapixel camera, an LCD display, @@ -520,7 +520,7 @@ config ARCH_BOARD_ESP32S3_LCD_EV depends on ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3WROOM1N16R16V || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-S3-LCD-EV is an ESP32-S3-based development board with a touchscreen. Together with different subboards, ESP32-S3-LCD-EV-Board can drive LCDs with IIC, @@ -537,7 +537,7 @@ config ARCH_BOARD_ESP32S3_LHCBIT bool "ESP32-S3 LHCBit" depends on ARCH_CHIP_ESP32S3WROOM1N16R8 select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3 LHCBit features the ESP32-S3 CPU with dual Xtensa LX7 cores. @@ -546,7 +546,7 @@ config ARCH_BOARD_ESP32S3_XIAO depends on ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The XIAO-ESP32S3 from Seeed Studio features the ESP32-S3 CPU with dual Xtensa LX7 cores, with 8MiB Octal SPI PSRAM and 8MiB or 16MiB flash. @@ -556,7 +556,7 @@ config ARCH_BOARD_ESP32S3_BOX depends on ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP-BOX is an advanced AIoT, Edge AI, and IIoT applications development platform released by Espressif Systems. The board is built on Espressif’s powerful ESP32-S3 @@ -570,7 +570,7 @@ config ARCH_BOARD_ESP32S3_KORVO_2 depends on ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3-Korvo-2 is a multimedia development board based on the ESP32-S3 chip. It is equipped with a two-microphone array which is suitable for voice recognition @@ -585,7 +585,7 @@ config ARCH_BOARD_ESP32S3_MEADOW depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3-Meadow is a small-sized board produced by WildernessLabs featuring the ESP32-S3 CPU with 32MiB Octal SPI PSRAM and 64 MiB flash. @@ -595,7 +595,7 @@ config ARCH_BOARD_ESP32S3_LCKFB_SZPI depends on ARCH_CHIP_ESP32S3WROOM1N16R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ config ARCH_BOARD_ESP32C6_DEVKITC bool "Espressif ESP32-C6-DevKitC-1" diff --git a/boards/risc-v/esp32c3/common/include/esp_board_rmt.h b/boards/risc-v/esp32c3/common/include/esp_board_rmt.h index 18494e7bcc9dc..5fc178653e3c9 100644 --- a/boards/risc-v/esp32c3/common/include/esp_board_rmt.h +++ b/boards/risc-v/esp32c3/common/include/esp_board_rmt.h @@ -61,7 +61,6 @@ extern "C" * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -69,7 +68,7 @@ extern "C" * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin); +int board_rmt_rxinitialize(int pin); /**************************************************************************** * Name: board_rmt_txinitialize @@ -78,7 +77,6 @@ int board_rmt_rxinitialize(int ch, int pin); * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -86,7 +84,7 @@ int board_rmt_rxinitialize(int ch, int pin); * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin); +int board_rmt_txinitialize(int pin); #endif /* CONFIG_ESP_RMT */ diff --git a/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld index d347ff867aaa6..ba5aeff2fc4e8 100644 --- a/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld @@ -27,6 +27,7 @@ cache_invalidate_icache_all = Cache_Invalidate_ICache_All; cache_resume_icache = Cache_Resume_ICache; cache_suspend_icache = Cache_Suspend_ICache; cache_invalidate_icache_all = Cache_Invalidate_ICache_All; +_interrupt_handler = exception_common; #ifdef CONFIG_ESPRESSIF_BLE diff --git a/boards/risc-v/esp32c3/common/scripts/esp32c3_sections.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_sections.ld index a17778cd55afc..e3129b0b68fa7 100644 --- a/boards/risc-v/esp32c3/common/scripts/esp32c3_sections.ld +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_sections.ld @@ -183,6 +183,7 @@ SECTIONS *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_utility.*(.text .text.* .literal .literal.*) *libarch.a:*apm_hal.*(.text .text.* .literal .literal.*) *libarch.a:*log.*(.text .text.* .literal .literal.*) *libarch.a:*log_lock.*(.literal .literal.* .text .text.*) @@ -205,8 +206,21 @@ SECTIONS *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:*riscv_modifyreg32.*(.literal .literal.* .text .text.*) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_pd_config* .text.esp_sleep_pd_config*) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_sub_mode_force_disable* .text.esp_sleep_sub_mode_force_disable*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) @@ -324,6 +338,7 @@ SECTIONS *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*efuse_utility.*(.rodata .rodata.*) *libarch.a:*log.*(.rodata .rodata.*) *libarch.a:*log_noos.*(.rodata .rodata.*) *libarch.a:esp_spiflash.*(.rodata .rodata.*) @@ -338,8 +353,15 @@ SECTIONS *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) *libarch.a:cache_utils.*(.rodata .rodata.*) + *libarch.a:startup_funcs.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_pd_config*) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_sub_mode_force_disable*) + esp_head.*(.rodata .rodata.*) esp_start.*(.rodata .rodata.*) @@ -587,6 +609,8 @@ SECTIONS .rtc.data : { + . = ALIGN(4); + *(.rtc.force_slow .rtc.force_slow.*) *(.rtc.data) *(.rtc.data.*) *(.rtc.rodata) diff --git a/boards/risc-v/esp32c3/common/src/esp_board_rmt.c b/boards/risc-v/esp32c3/common/src/esp_board_rmt.c index 5f329c902a767..ddac1b988bd86 100644 --- a/boards/risc-v/esp32c3/common/src/esp_board_rmt.c +++ b/boards/risc-v/esp32c3/common/src/esp_board_rmt.c @@ -77,7 +77,6 @@ * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -85,11 +84,11 @@ * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin) +int board_rmt_rxinitialize(int pin) { int ret; - struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + struct rmt_dev_s *rmt = esp_rmt_rx_init(pin); ret = rmtchar_register(rmt); if (ret < 0) @@ -108,7 +107,6 @@ int board_rmt_rxinitialize(int ch, int pin) * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -116,7 +114,7 @@ int board_rmt_rxinitialize(int ch, int pin) * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin) +int board_rmt_txinitialize(int pin) { int ret; struct rmt_dev_s *rmt; @@ -124,7 +122,7 @@ int board_rmt_txinitialize(int ch, int pin) struct ws2812_dev_s *led; #endif - rmt = esp_rmt_tx_init(ch, pin); + rmt = esp_rmt_tx_init(pin); if (rmt == NULL) { rmterr("ERROR: esp_rmt_tx_init failed\n"); diff --git a/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c b/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c index 2c3875d92ab0e..7b3366d2c2ec2 100644 --- a/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c +++ b/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c @@ -477,8 +477,6 @@ int board_spiflash_init(void) { int ret = OK; - esp_spiflash_init(); - #ifdef CONFIG_ESPRESSIF_HAVE_OTA_PARTITION ret = init_ota_partitions(); if (ret < 0) diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/configs/jumbo/defconfig b/boards/risc-v/esp32c3/esp32-c3-zero/configs/jumbo/defconfig index 03bd912777d64..5ac94ef4ce7a2 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/configs/jumbo/defconfig +++ b/boards/risc-v/esp32c3/esp32-c3-zero/configs/jumbo/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_C3_ZERO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32-c3-zero/configs/nsh/defconfig index 2f4aead1ae112..b4db58c81aa40 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/configs/nsh/defconfig +++ b/boards/risc-v/esp32c3/esp32-c3-zero/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_C3_ZERO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/configs/sta_softap/defconfig b/boards/risc-v/esp32c3/esp32-c3-zero/configs/sta_softap/defconfig index 2df8690ad99b4..858faa6968161 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/configs/sta_softap/defconfig +++ b/boards/risc-v/esp32c3/esp32-c3-zero/configs/sta_softap/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_C3_ZERO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/configs/usbnsh/defconfig b/boards/risc-v/esp32c3/esp32-c3-zero/configs/usbnsh/defconfig index 87358fe3d2c27..1dca055eab442 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/configs/usbnsh/defconfig +++ b/boards/risc-v/esp32c3/esp32-c3-zero/configs/usbnsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_C3_ZERO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/configs/wifi/defconfig b/boards/risc-v/esp32c3/esp32-c3-zero/configs/wifi/defconfig index 0180fb99d06bd..967e64b332d0b 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/configs/wifi/defconfig +++ b/boards/risc-v/esp32c3/esp32-c3-zero/configs/wifi/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_C3_ZERO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c index c2bc6bf853f5b..a4f3f31086518 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c @@ -38,6 +38,8 @@ #include "esp_board_ledc.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_ESPRESSIF_ADC # include "esp_board_adc.h" #endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig index ed8efa0c67f81..7c3ab0e3cc9eb 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig index 34aba669f81ea..3d7ca120dc460 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig index 6a9b4d901e06d..c89e31afd7b5c 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/buttons/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/buttons/defconfig index 103f71379e0fb..557765561db34 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/buttons/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/buttons/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig index 94c0959df1d87..b65b4d153aec6 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig index 22d965277ba8f..a6facb67d64eb 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig index bfbf06ae7a802..c6141a595cea6 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2c/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2c/defconfig index 43e33b34dc2eb..1b6150cb05147 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2c/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2c/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2schar/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2schar/defconfig index 14a7d7e71966d..0bc716f456fe0 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2schar/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/i2schar/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_nsh/defconfig index 3d91936ac0095..8ba5d7f25534d 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_nsh/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_update_agent/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_update_agent/defconfig index 832c8f834f8a8..ae26871ccefb3 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_update_agent/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_update_agent/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nimble/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nimble/defconfig index 493fd20aa43d5..adee132c2b0c0 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nimble/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nimble/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig index b8b58dde7f511..c7c8600f0c1f4 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig index 7c02e84b712f2..b4d371d4ce024 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig index 01e2189cd26ca..7bfbe622d36b6 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -38,6 +41,8 @@ CONFIG_PM_GOVERNOR_GREEDY=y CONFIG_PM_PROCFS=y CONFIG_PREALLOC_TIMERS=0 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=29 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig index f0e95fa2c4911..ab1f81f80a340 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig index eb988d806682e..864b3d5eb7fe3 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rmt/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rmt/defconfig index 29402065a5a01..01335a518b419 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rmt/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rmt/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig index 1135250714cc1..e74e870f8c45f 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig index 875b2b3f1b8cd..891f93d7f23ab 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdm/defconfig index 1945b91ee658d..e47f31949e469 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdm/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdm/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdmmc_spi/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdmmc_spi/defconfig index fd221acf1acb8..26a9e4c728dd0 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdmmc_spi/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sdmmc_spi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spi/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spi/defconfig index 70605e9fd31c1..56e133f0f2fd7 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spi/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spi/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig index a446caa23ad4f..7407ba2b5e9c0 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig index 3e5e9c7203012..07e1f5bf3928a 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/temperature_sensor/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/temperature_sensor/defconfig index 535278357089e..443ea1b8b25ea 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/temperature_sensor/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/temperature_sensor/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig index ac14f39b0dd9e..1a153aa05ae54 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/timers/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/timers/defconfig index 9ae118627186d..ec1a4463c52e5 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/timers/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/timers/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig index 4029f5facaa97..2a325c4a3b689 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig index 96988c184ef24..c72b8696728e2 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig index 6c91993343c71..0926f48b24d7b 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig index 617c353cf3010..18305828a758d 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c index 9bc19ab031a0d..d586caab418ce 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c @@ -41,6 +41,8 @@ #include "esp_board_i2c.h" #include "esp_board_bmp180.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_ESPRESSIF_ADC # include "esp_board_adc.h" #endif @@ -342,13 +344,13 @@ int esp_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_buttons.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_buttons.c index 07df1f25a24ab..802bb6b274624 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_buttons.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_buttons.c @@ -75,7 +75,7 @@ uint32_t board_button_initialize(void) { - esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -164,37 +164,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - - gpioinfo("Attach %p\n", irqhandler); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - /* Configure the interrupt for rising and falling edges */ - - gpioinfo("Enabling the interrupt\n"); - esp_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c index 419a401e0d312..942977790cfbb 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c @@ -385,23 +385,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[espgpint->espgpio.id], + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + gpioinfo("Attach %p\n", callback); espgpint->callback = callback; return OK; @@ -425,7 +429,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); if (enable) { @@ -435,13 +438,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[espgpint->espgpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); } return OK; @@ -474,11 +477,11 @@ static int gpint_setpintype(struct gpio_dev_s *dev, { case GPIO_INTERRUPT_HIGH_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); + INPUT_PULLUP | FALLING); break; case GPIO_INTERRUPT_LOW_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); + INPUT_PULLDOWN | RISING); break; default: return ERROR; @@ -539,9 +542,12 @@ int esp_gpio_init(void) g_gpint[i].espgpio.id = i; gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/configs/ble/defconfig b/boards/risc-v/esp32c3/esp32c3-xiao/configs/ble/defconfig index 0f69698320f04..1c280efd2580d 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/configs/ble/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-xiao/configs/ble/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32C3_XIAO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-xiao/configs/gpio/defconfig index 39aff670781cb..60fa72f251811 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/configs/gpio/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-xiao/configs/gpio/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32C3_XIAO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/configs/nimble/defconfig b/boards/risc-v/esp32c3/esp32c3-xiao/configs/nimble/defconfig index 68838f530911d..bdbf209c7513b 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/configs/nimble/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-xiao/configs/nimble/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_BOARD_ESP32C3_XIAO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-xiao/configs/nsh/defconfig index 083e0d515b19d..c346b93f0d96f 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/configs/nsh/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-xiao/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32C3_XIAO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/configs/usbnsh/defconfig b/boards/risc-v/esp32c3/esp32c3-xiao/configs/usbnsh/defconfig index 1de4ad3dc6ac9..ccbe39afe71b3 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/configs/usbnsh/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-xiao/configs/usbnsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32C3_XIAO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/configs/wifi/defconfig b/boards/risc-v/esp32c3/esp32c3-xiao/configs/wifi/defconfig index 778ef1deaea31..e56f487150d72 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/configs/wifi/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-xiao/configs/wifi/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32C3_XIAO=y CONFIG_ARCH_CHIP="esp32c3" CONFIG_ARCH_CHIP_ESP32C3=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_bringup.c index 57631cb8d4d70..03a958a6a4ace 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_bringup.c @@ -41,6 +41,8 @@ #include "esp_board_i2c.h" #include "esp_board_bmp180.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_WATCHDOG # include "espressif/esp_wdt.h" #endif @@ -304,13 +306,13 @@ int esp_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); diff --git a/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_gpio.c index 702ac4c9a5e61..49ac29e3732f8 100644 --- a/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_gpio.c +++ b/boards/risc-v/esp32c3/esp32c3-xiao/src/esp32c3_gpio.c @@ -346,23 +346,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[espgpint->espgpio.id], + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + gpioinfo("Attach %p\n", callback); espgpint->callback = callback; return OK; @@ -386,7 +390,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); if (enable) { @@ -396,13 +399,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[espgpint->espgpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); } return OK; @@ -435,11 +438,11 @@ static int gpint_setpintype(struct gpio_dev_s *dev, { case GPIO_INTERRUPT_HIGH_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); + INPUT_PULLUP | FALLING); break; case GPIO_INTERRUPT_LOW_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); + INPUT_PULLDOWN | RISING); break; default: return ERROR; @@ -500,9 +503,12 @@ int esp_gpio_init(void) g_gpint[i].espgpio.id = i; gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/risc-v/esp32c6/common/include/esp_board_rmt.h b/boards/risc-v/esp32c6/common/include/esp_board_rmt.h index dd44795d30ab8..1cc8a128163ee 100644 --- a/boards/risc-v/esp32c6/common/include/esp_board_rmt.h +++ b/boards/risc-v/esp32c6/common/include/esp_board_rmt.h @@ -61,7 +61,6 @@ extern "C" * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -69,7 +68,7 @@ extern "C" * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin); +int board_rmt_rxinitialize(int pin); /**************************************************************************** * Name: board_rmt_txinitialize @@ -78,7 +77,6 @@ int board_rmt_rxinitialize(int ch, int pin); * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -86,7 +84,7 @@ int board_rmt_rxinitialize(int ch, int pin); * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin); +int board_rmt_txinitialize(int pin); #endif /* CONFIG_ESP_RMT */ diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld index 5e5efb6ce80c5..809985725d513 100644 --- a/boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld @@ -24,6 +24,7 @@ cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size; cache_resume_icache = Cache_Resume_ICache; cache_suspend_icache = Cache_Suspend_ICache; cache_invalidate_icache_all = Cache_Invalidate_ICache_All; +_interrupt_handler = exception_common; #ifdef CONFIG_ESPRESSIF_BLE diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld index cb0c9459457aa..7665b29b94613 100644 --- a/boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_sections.ld @@ -191,6 +191,7 @@ SECTIONS *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_utility.*(.text .text.* .literal .literal.*) *libarch.a:*apm_hal.*(.text .text.* .literal .literal.*) *libarch.a:*log.*(.text .text.* .literal .literal.*) *libarch.a:*log_lock.*(.literal .literal.* .text .text.*) @@ -200,6 +201,7 @@ SECTIONS *libarch.a:*log_timestamp_common.*(.literal .literal.* .text .text.*) *libarch.a:*log_write.*(.literal.esp_log_write .text.esp_log_write) *libarch.a:*log_write.*(.literal.esp_log_writev .text.esp_log_writev) + *libarch.a:riscv_modifyreg32.*(.literal .literal.* .text .text.*) *libarch.a:*interrupt_plic.*(.literal .literal.* .text .text.*) *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:esp_flash_api.*(.text .text.* .literal .literal.*) @@ -213,8 +215,18 @@ SECTIONS *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_pd_config* .text.esp_sleep_pd_config*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) @@ -371,9 +383,13 @@ SECTIONS *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) *libarch.a:cache_utils.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) - + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_pd_config*) + *libarch.a:*efuse_utility.*(.rodata .rodata.*) esp_head.*(.rodata .rodata.*) esp_start.*(.rodata .rodata.*) diff --git a/boards/risc-v/esp32c6/common/src/esp_board_oa_tc6.c b/boards/risc-v/esp32c6/common/src/esp_board_oa_tc6.c index 60e40c060a6b6..02939c0468032 100644 --- a/boards/risc-v/esp32c6/common/src/esp_board_oa_tc6.c +++ b/boards/risc-v/esp32c6/common/src/esp_board_oa_tc6.c @@ -97,6 +97,7 @@ static int board_oa_tc6_attach(FAR const struct oa_tc6_config_s *config, xcpt_t handler, FAR void *arg) { int pin; + int ret; switch (config->id) { @@ -111,8 +112,16 @@ static int board_oa_tc6_attach(FAR const struct oa_tc6_config_s *config, return ERROR; } - esp_configgpio(pin, INPUT_FUNCTION_2 | PULLUP); - irq_attach(ESP_PIN2IRQ(pin), handler, arg); + esp_configgpio(pin, INPUT_FUNCTION_2 | PULLUP | FALLING); + + ret = esp_gpio_irq(pin, + handler, + arg); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_oa_tc6_attach() failed: %d\n", ret); + return ret; + } return OK; } @@ -153,11 +162,11 @@ static int board_oa_tc6_enable(FAR const struct oa_tc6_config_s *config, if (enable) { - esp_gpioirqenable(ESP_PIN2IRQ(pin), FALLING); + esp_gpioirqenable(pin); } else { - esp_gpioirqdisable(ESP_PIN2IRQ(pin)); + esp_gpioirqdisable(pin); } return OK; diff --git a/boards/risc-v/esp32c6/common/src/esp_board_rmt.c b/boards/risc-v/esp32c6/common/src/esp_board_rmt.c index 2d63c1695b3d8..8094242d2c35a 100644 --- a/boards/risc-v/esp32c6/common/src/esp_board_rmt.c +++ b/boards/risc-v/esp32c6/common/src/esp_board_rmt.c @@ -77,7 +77,6 @@ * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -85,11 +84,11 @@ * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin) +int board_rmt_rxinitialize(int pin) { int ret; - struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + struct rmt_dev_s *rmt = esp_rmt_rx_init(pin); ret = rmtchar_register(rmt); if (ret < 0) @@ -108,7 +107,6 @@ int board_rmt_rxinitialize(int ch, int pin) * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -116,7 +114,7 @@ int board_rmt_rxinitialize(int ch, int pin) * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin) +int board_rmt_txinitialize(int pin) { int ret; struct rmt_dev_s *rmt; @@ -124,7 +122,7 @@ int board_rmt_txinitialize(int ch, int pin) struct ws2812_dev_s *led; #endif - rmt = esp_rmt_tx_init(ch, pin); + rmt = esp_rmt_tx_init(pin); if (rmt == NULL) { rmterr("ERROR: esp_rmt_tx_init failed\n"); diff --git a/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c b/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c index 8879a3013670b..ff05e5d333d8f 100644 --- a/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c +++ b/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c @@ -473,12 +473,6 @@ int board_spiflash_init(void) { int ret = OK; - ret = esp_spiflash_init(); - if (ret != OK) - { - return ret; - } - #ifdef CONFIG_ESPRESSIF_HAVE_OTA_PARTITION ret = init_ota_partitions(); if (ret < 0) diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/adc/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/adc/defconfig index f18e4f634b5a0..f208e17f20029 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/adc/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/adc/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/bmp180/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/bmp180/defconfig index 1e12785c93769..f01eab1af73a7 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/bmp180/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/bmp180/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig index 841f40e172abd..70b23701c9829 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/capture/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/capture/defconfig index 54e56b2c6e874..44f01c6b2b107 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/capture/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/capture/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/coremark/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/coremark/defconfig index a9585332b37ca..323a7ef5a5e1c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/coremark/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/coremark/defconfig @@ -13,6 +13,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_BENCHMARK_COREMARK=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig index 6584f32141dbc..ee6b5d8df2c44 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/efuse/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/efuse/defconfig index 9c387edc9bffa..95a85d56d4313 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/efuse/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/efuse/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig index 028345176a71a..7654ab841992a 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2c/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2c/defconfig index 27d38d5ef19d4..db456b42bd962 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2c/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2c/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2schar/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2schar/defconfig index 37503b617a181..bd5e63c04dd5e 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2schar/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/i2schar/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig index c8356f2b0ef24..3faf6fb3cba45 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_update_agent/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_update_agent/defconfig index eebdcd1211997..0aefb04687783 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_update_agent/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mcuboot_update_agent/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/motor/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/motor/defconfig index 20015a92ff10c..8a8494eaee63e 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/motor/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/motor/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mpu60x0/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mpu60x0/defconfig index ab4c8e3218006..086f149ffdcdd 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mpu60x0/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/mpu60x0/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig index 7a240a40daa34..a8fcec3ec5da5 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/oa_tc6/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/oa_tc6/defconfig index 887c074f078b6..c641965da9717 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/oa_tc6/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/oa_tc6/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig index 3448194ee20c8..56f72ad169178 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pm/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pm/defconfig index cdcf939a68ad0..b74bcb4ab7c8a 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pm/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -30,6 +33,7 @@ CONFIG_LIBC_STRERROR=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_DATE=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NSH_STRERROR=y @@ -39,6 +43,8 @@ CONFIG_PM_GOVERNOR_GREEDY=y CONFIG_PM_PROCFS=y CONFIG_PREALLOC_TIMERS=0 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=29 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig index 707306a71d990..8027a8ce00a1b 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/qencoder/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/qencoder/defconfig index a8698a512d1bb..d7e34c25f9f9a 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/qencoder/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/qencoder/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig index a426fba1739ce..002193248feaa 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig index 02b6f0bcf7f85..8a4aa0b30944c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/romfs/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/romfs/defconfig index 484b7da8ab3dc..a2abdbfb5e318 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/romfs/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/romfs/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -27,6 +30,7 @@ CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig index 2e1cd143422d0..51bc2059ee3b2 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdm/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdm/defconfig index a23b003e56bbc..b429c3349256a 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdm/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdmmc_spi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdmmc_spi/defconfig index 2971a9623c0cf..6267e1b966185 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdmmc_spi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sdmmc_spi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spi/defconfig index 58d0a9ac83bac..c38e615e3c16c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spi/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig index 495d41dd382e2..54fd480bd0612 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spislv/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spislv/defconfig index a339324548c7a..d9b6a90116cc0 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spislv/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spislv/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig index a2f381c41928a..f55f6b7c60f61 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/temperature_sensor/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/temperature_sensor/defconfig index f611e6a84ef99..9c4f84a2c0822 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/temperature_sensor/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/temperature_sensor/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig index 5659226241a52..df497987b1262 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig index a3856272bf704..ce1f58c663fff 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig index c97b030d7e1c0..918f92de18fea 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ulp/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ulp/defconfig index 648953c41e9fd..436801ebf78e4 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ulp/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ulp/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -38,6 +41,8 @@ CONFIG_NSH_READLINE=y CONFIG_NSH_STRERROR=y CONFIG_PREALLOC_TIMERS=0 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=29 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig index da96a7f271232..3935a4988e5a4 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig index e47c7b046f28e..d15dd67fa2290 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig index d63a2687435a4..4abcc4411cbfd 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig @@ -16,16 +16,30 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DEBUG_WIRELESS_INFO=y +CONFIG_DEBUG_WIRELESS_WARN=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_MERGE_BINS=y CONFIG_ESPRESSIF_SPIFLASH=y CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y CONFIG_ESPRESSIF_WIFI=y +CONFIG_ESP_WPA_DEBUG_PRINT=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c index 744ca526ee653..c5ef820693734 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c @@ -41,6 +41,8 @@ #include "esp_board_i2c.h" #include "esp_board_bmp180.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_ESPRESSIF_ADC # include "esp_board_adc.h" #endif @@ -266,13 +268,13 @@ int esp_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c index 8f43500ba47ff..dfc75f3ee13f5 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c @@ -75,7 +75,7 @@ uint32_t board_button_initialize(void) { - esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -164,37 +164,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - - gpioinfo("Attach %p\n", irqhandler); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - /* Configure the interrupt for rising and falling edges */ - - gpioinfo("Enabling the interrupt\n"); - esp_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c index fca1d764a0f34..fecc37487762c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c @@ -461,23 +461,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[espgpint->espgpio.id], + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + gpioinfo("Attach %p\n", callback); espgpint->callback = callback; return OK; @@ -501,7 +505,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); if (enable) { @@ -511,13 +514,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[espgpint->espgpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); } return OK; @@ -550,11 +553,11 @@ static int gpint_setpintype(struct gpio_dev_s *dev, { case GPIO_INTERRUPT_HIGH_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); + INPUT_PULLUP | FALLING); break; case GPIO_INTERRUPT_LOW_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); + INPUT_PULLDOWN | RISING); break; default: return ERROR; @@ -615,9 +618,12 @@ int esp_gpio_init(void) g_gpint[i].espgpio.id = i; gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/bmp180/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/bmp180/defconfig index 9d0dadab5ad88..00156706ae030 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/bmp180/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/bmp180/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig index ff369a7dfa201..283d2e32a4a0c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/efuse/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/efuse/defconfig index 62aece566257d..81516ce71e673 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/efuse/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/efuse/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig index 18f7b524a2073..4c5d934b9d423 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2c/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2c/defconfig index a497cd120cec6..75fea9c2ed5fb 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2c/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2c/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2schar/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2schar/defconfig index adf308f076d13..a12b0b0409cad 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2schar/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/i2schar/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig index 652e4566fc42b..0a3814e8c29c9 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/mcuboot_nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig index c3926cbdc1245..52cba24952601 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/oa_tc6/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/oa_tc6/defconfig index 3016993b5fc36..b26008a0d5d58 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/oa_tc6/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/oa_tc6/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig index 11a92c8506bfe..9afbd8341503a 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig index 471f48e0fc2d9..20ecbbd187037 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig index a0c203dbac5f2..e1373df8fed23 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig index a048f28a43419..b7b9accc8a515 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/romfs/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/romfs/defconfig index d2f82228f7556..9718095b7028c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/romfs/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/romfs/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -25,6 +28,7 @@ CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig index 47ec841d8a564..5a84093a6768e 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sdmmc_spi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sdmmc_spi/defconfig index bd373236508dc..3f921ef3bd84c 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sdmmc_spi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sdmmc_spi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spi/defconfig index e6737ca239969..b7e584501c615 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spi/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig index 24a5313bc6305..96832c93a3232 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spislv/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spislv/defconfig index 1ffa1a673289d..6637edf9a5b1e 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spislv/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spislv/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig index 92bcc73a55112..8263988bf03f8 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig index 4d584e30d18e3..cc9ff5c05ef66 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig index 59ca1a7748fd5..900e39c59bbb1 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig index 1334c29a3cd63..6788919394771 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig index 8da98d0800470..0d26a89d71d86 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig index 767f3b6985c50..a56fb373222cd 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6MINI1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig index 92bcc73a55112..8263988bf03f8 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c index 78093baef17c3..b0d5ca7caa3c2 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c @@ -41,6 +41,8 @@ #include "esp_board_i2c.h" #include "esp_board_bmp180.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_WATCHDOG # include "espressif/esp_wdt.h" #endif @@ -229,13 +231,13 @@ int esp_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c index afec08d150909..cb0bc7956b5a0 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c @@ -75,7 +75,7 @@ uint32_t board_button_initialize(void) { - esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -164,37 +164,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - - gpioinfo("Attach %p\n", irqhandler); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - /* Configure the interrupt for rising and falling edges */ - - gpioinfo("Enabling the interrupt\n"); - esp_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c index f4c02a4e0a3fc..f0e41ec289efb 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c @@ -347,23 +347,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[espgpint->espgpio.id], + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + gpioinfo("Attach %p\n", callback); espgpint->callback = callback; return OK; @@ -387,7 +391,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); if (enable) { @@ -397,13 +400,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[espgpint->espgpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); } return OK; @@ -436,11 +439,11 @@ static int gpint_setpintype(struct gpio_dev_s *dev, { case GPIO_INTERRUPT_HIGH_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); + INPUT_PULLUP | FALLING); break; case GPIO_INTERRUPT_LOW_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); + INPUT_PULLDOWN | RISING); break; default: return ERROR; @@ -501,9 +504,12 @@ int esp_gpio_init(void) g_gpint[i].espgpio.id = i; gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/risc-v/esp32c6/esp32c6-xiao/configs/gpio/defconfig b/boards/risc-v/esp32c6/esp32c6-xiao/configs/gpio/defconfig index 73934a43a1b61..7cea624354026 100644 --- a/boards/risc-v/esp32c6/esp32c6-xiao/configs/gpio/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-xiao/configs/gpio/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-xiao/configs/nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-xiao/configs/nsh/defconfig index da7c32ac3d20d..dcf421fa6696a 100644 --- a/boards/risc-v/esp32c6/esp32c6-xiao/configs/nsh/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-xiao/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-xiao/configs/usbnsh/defconfig b/boards/risc-v/esp32c6/esp32c6-xiao/configs/usbnsh/defconfig index 4daa458bccb7b..4ff67c3f9fb94 100644 --- a/boards/risc-v/esp32c6/esp32c6-xiao/configs/usbnsh/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-xiao/configs/usbnsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32c6/esp32c6-xiao/configs/wifi/defconfig b/boards/risc-v/esp32c6/esp32c6-xiao/configs/wifi/defconfig index a7d3baeef2bd3..d7692a5ae1ad6 100644 --- a/boards/risc-v/esp32c6/esp32c6-xiao/configs/wifi/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-xiao/configs/wifi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32c6" CONFIG_ARCH_CHIP_ESP32C6=y CONFIG_ARCH_CHIP_ESP32C6WROOM1=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_bringup.c index 50f0e3b0fcb80..b7d7aac3b3be7 100644 --- a/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_bringup.c +++ b/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_bringup.c @@ -39,6 +39,8 @@ #include "esp_board_spiflash.h" #include "esp_board_i2c.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_ESPRESSIF_ADC # include "esp_board_adc.h" #endif @@ -211,13 +213,13 @@ int esp_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); diff --git a/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_gpio.c b/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_gpio.c index 658b2af753650..02904fbc1e497 100644 --- a/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_gpio.c +++ b/boards/risc-v/esp32c6/esp32c6-xiao/src/esp32c6_gpio.c @@ -353,23 +353,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[espgpint->espgpio.id], + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + gpioinfo("Attach %p\n", callback); espgpint->callback = callback; return OK; @@ -393,7 +397,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); if (enable) { @@ -403,13 +406,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[espgpint->espgpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); } return OK; @@ -442,11 +445,11 @@ static int gpint_setpintype(struct gpio_dev_s *dev, { case GPIO_INTERRUPT_HIGH_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); + INPUT_PULLUP | FALLING); break; case GPIO_INTERRUPT_LOW_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); + INPUT_PULLDOWN | RISING); break; default: return ERROR; @@ -507,9 +510,12 @@ int esp_gpio_init(void) g_gpint[i].espgpio.id = i; gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/risc-v/esp32h2/common/include/esp_board_rmt.h b/boards/risc-v/esp32h2/common/include/esp_board_rmt.h index e8f9fdee18be0..0dc8af8d169fb 100644 --- a/boards/risc-v/esp32h2/common/include/esp_board_rmt.h +++ b/boards/risc-v/esp32h2/common/include/esp_board_rmt.h @@ -61,7 +61,6 @@ extern "C" * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -69,7 +68,7 @@ extern "C" * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin); +int board_rmt_rxinitialize(int pin); /**************************************************************************** * Name: board_rmt_txinitialize @@ -78,7 +77,6 @@ int board_rmt_rxinitialize(int ch, int pin); * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -86,7 +84,7 @@ int board_rmt_rxinitialize(int ch, int pin); * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin); +int board_rmt_txinitialize(int pin); #endif /* CONFIG_ESP_RMT */ diff --git a/boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld b/boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld index 61681401c17ca..afc7a50c79bfd 100644 --- a/boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld +++ b/boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld @@ -24,6 +24,7 @@ cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size; cache_resume_icache = Cache_Resume_ICache; cache_suspend_icache = Cache_Suspend_ICache; cache_invalidate_icache_all = Cache_Invalidate_ICache_All; +_interrupt_handler = exception_common; #ifdef CONFIG_ESPRESSIF_BLE diff --git a/boards/risc-v/esp32h2/common/scripts/esp32h2_sections.ld b/boards/risc-v/esp32h2/common/scripts/esp32h2_sections.ld index f7c3526db0cad..7d9f5a11054b5 100644 --- a/boards/risc-v/esp32h2/common/scripts/esp32h2_sections.ld +++ b/boards/risc-v/esp32h2/common/scripts/esp32h2_sections.ld @@ -198,6 +198,7 @@ SECTIONS *libarch.a:*log_timestamp_common.*(.literal .literal.* .text .text.*) *libarch.a:*log_write.*(.literal.esp_log_write .text.esp_log_write) *libarch.a:*log_write.*(.literal.esp_log_writev .text.esp_log_writev) + *libarch.a:*riscv_modifyreg32.*(.literal .literal.* .text .text.*) *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:esp_flash_api.*(.text .text.* .literal .literal.*) *libarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*) @@ -209,11 +210,19 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) - *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) *libarch.a:*interrupt_plic.*(.literal .literal.* .text .text.*) - + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_pd_config* .text.esp_sleep_pd_config*) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) esp_head.*(.literal .text .literal.* .text.*) @@ -364,9 +373,12 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.rodata .rodata.*) *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) - *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) *libarch.a:cache_utils.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_pd_config*) esp_head.*(.rodata .rodata.*) esp_start.*(.rodata .rodata.*) diff --git a/boards/risc-v/esp32h2/common/src/esp_board_rmt.c b/boards/risc-v/esp32h2/common/src/esp_board_rmt.c index 6b6a31b8d259e..8c56a262bc07c 100644 --- a/boards/risc-v/esp32h2/common/src/esp_board_rmt.c +++ b/boards/risc-v/esp32h2/common/src/esp_board_rmt.c @@ -77,7 +77,6 @@ * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -85,11 +84,11 @@ * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin) +int board_rmt_rxinitialize(int pin) { int ret; - struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + struct rmt_dev_s *rmt = esp_rmt_rx_init(pin); ret = rmtchar_register(rmt); if (ret < 0) @@ -108,7 +107,6 @@ int board_rmt_rxinitialize(int ch, int pin) * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -116,7 +114,7 @@ int board_rmt_rxinitialize(int ch, int pin) * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin) +int board_rmt_txinitialize(int pin) { int ret; struct rmt_dev_s *rmt; @@ -124,7 +122,7 @@ int board_rmt_txinitialize(int ch, int pin) struct ws2812_dev_s *led; #endif - rmt = esp_rmt_tx_init(ch, pin); + rmt = esp_rmt_tx_init(pin); if (rmt == NULL) { rmterr("ERROR: esp_rmt_tx_init failed\n"); diff --git a/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c b/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c index 152ce7553fd57..cc89b7fec6410 100644 --- a/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c +++ b/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c @@ -472,8 +472,6 @@ int board_spiflash_init(void) { int ret = OK; - esp_spiflash_init(); - #ifdef CONFIG_ESPRESSIF_HAVE_OTA_PARTITION ret = init_ota_partitions(); if (ret < 0) diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/adc/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/adc/defconfig index 855608de52b28..51558539f2a26 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/adc/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/adc/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/bmp180/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/bmp180/defconfig index ff0020345fc64..9c19c2a7476c0 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/bmp180/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/bmp180/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig index b2546f67768b7..b89f24ddb3f4c 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/capture/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/capture/defconfig index 9052db64cf00d..adc0f8b2130f1 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/capture/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/capture/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig index 598016c1919b2..aae7f4f2d51fe 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/efuse/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/efuse/defconfig index ddc6d5199ae28..2a45dd78531f4 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/efuse/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/efuse/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig index 3db945c3dc063..b6fac3c95165b 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2c/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2c/defconfig index 8505cb63e2a54..b90c8a01c0987 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2c/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2c/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2schar/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2schar/defconfig index ddd259c3901ea..7dfe9eba8f2dc 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2schar/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/i2schar/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/mcuboot_nsh/defconfig index dd947a0aab43f..74107f92fe592 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/mcuboot_nsh/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/mcuboot_nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/motor/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/motor/defconfig index 7e55326b117ac..a8b6b0af7e326 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/motor/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/motor/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig index e7ea16299da21..d87e91f91adc5 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig index 1f5d924f0919a..3e9750067180e 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/pm/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/pm/defconfig index 0f14a700b1104..0adee44df66a8 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/pm/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/pm/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y @@ -38,6 +41,8 @@ CONFIG_PM_GOVERNOR_GREEDY=y CONFIG_PM_PROCFS=y CONFIG_PREALLOC_TIMERS=0 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=29 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig index fc57e41aded08..98408b591e79b 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/qencoder/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/qencoder/defconfig index 6f3469f6e0eef..012c34abf8e61 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/qencoder/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/qencoder/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig index a191bec3b585a..705a8a4759e78 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig index 4918cb7636083..53e39e2658b88 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/romfs/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/romfs/defconfig index 74b5a9562b46e..f31c00dc97282 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/romfs/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/romfs/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig index 27bcfb3a4ed36..c8ec0f436aa1a 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdm/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdm/defconfig index 477b53099f839..6c69fad9b19f0 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdm/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdm/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdmmc_spi/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdmmc_spi/defconfig index 3b03b869fe0af..bd5f463e64782 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdmmc_spi/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/sdmmc_spi/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/spi/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/spi/defconfig index 2e87d32faf17f..978f517c788a7 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/spi/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/spi/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig index da3b4112413a4..d79127c2475c2 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/temperature_sensor/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/temperature_sensor/defconfig index 943686448b9ff..5057b04eaae85 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/temperature_sensor/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/temperature_sensor/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig index 133c576b31f07..8bcddd7c6ec19 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig index 488e033481cb6..150cd3ea8ecb9 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig index 441083bd1e252..4e0c55719ef49 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig index 5fc086483799b..5082caf2dfa43 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig index 016f17364eed0..12652632da334 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y CONFIG_ARCH_CHIP="esp32h2" CONFIG_ARCH_CHIP_ESP32H2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15000 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c index ae47ae9ddb1b5..8dae31d1fb461 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c @@ -41,6 +41,8 @@ #include "esp_board_i2c.h" #include "esp_board_bmp180.h" +#include "espressif/esp_start.h" + #ifdef CONFIG_WATCHDOG # include "espressif/esp_wdt.h" #endif @@ -245,16 +247,16 @@ int esp_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { - syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: board_rmt_rxinitialize() failed: %d\n", ret); } #endif diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c index 5f88b9b16936c..c305ebcef4821 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c @@ -75,7 +75,7 @@ uint32_t board_button_initialize(void) { - esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -164,37 +164,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - - gpioinfo("Attach %p\n", irqhandler); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - /* Configure the interrupt for rising and falling edges */ - - gpioinfo("Enabling the interrupt\n"); - esp_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c index 95eaa5ef3f00d..6aaedab56354f 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c @@ -385,23 +385,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[espgpint->espgpio.id], + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); + gpioinfo("Attach %p\n", callback); espgpint->callback = callback; return OK; @@ -425,7 +429,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); if (enable) { @@ -435,13 +438,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[espgpint->espgpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[espgpint->espgpio.id]); } return OK; @@ -474,11 +477,11 @@ static int gpint_setpintype(struct gpio_dev_s *dev, { case GPIO_INTERRUPT_HIGH_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); + INPUT_PULLUP | FALLING); break; case GPIO_INTERRUPT_LOW_PIN: esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); + INPUT_PULLDOWN | RISING); break; default: return ERROR; @@ -539,9 +542,12 @@ int esp_gpio_init(void) g_gpint[i].espgpio.id = i; gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; }