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asicguyasicguy
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Initial Checkin of HDL and Stim directories
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‎hdl/altera_clk_synth/bt_ddr_io.ppf‎

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<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE pinplan>
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<pinplan intended_family="Arria II GX" variation_name="bt_ddr_io" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
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<global>
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<pin name="aclr" direction="input" scope="external" />
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<pin name="datain_h[0..0]" direction="input" scope="external" />
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<pin name="datain_l[0..0]" direction="input" scope="external" />
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<pin name="outclock" direction="input" scope="external" source="clock" />
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<pin name="dataout[0..0]" direction="output" scope="external" />
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</global>
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</pinplan>

‎hdl/altera_clk_synth/bt_ddr_io.qip‎

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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
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set_global_assignment -name IP_TOOL_VERSION "12.1"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "bt_ddr_io.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "bt_ddr_io.ppf"]

‎hdl/altera_clk_synth/bt_ddr_io.v‎

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// megafunction wizard: %ALTDDIO_OUT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: ALTDDIO_OUT
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// ============================================================
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// File Name: bt_ddr_io.v
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// Megafunction Name(s):
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// ALTDDIO_OUT
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 12.1 Build 243 01/31/2013 SP 1.33 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2012 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module bt_ddr_io (
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aclr,
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datain_h,
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datain_l,
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outclock,
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dataout);
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input aclr;
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input [0:0] datain_h;
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input [0:0] datain_l;
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input outclock;
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output [0:0] dataout;
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wire [0:0] sub_wire0;
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wire [0:0] dataout = sub_wire0[0:0];
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altddio_out ALTDDIO_OUT_component (
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.aclr (aclr),
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.datain_h (datain_h),
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.datain_l (datain_l),
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.outclock (outclock),
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.dataout (sub_wire0),
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.aset (1'b0),
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.oe (1'b1),
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.oe_out (),
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.outclocken (1'b1),
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.sclr (1'b0),
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.sset (1'b0));
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defparam
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ALTDDIO_OUT_component.extend_oe_disable = "OFF",
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ALTDDIO_OUT_component.intended_device_family = "Arria II GX",
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ALTDDIO_OUT_component.invert_output = "OFF",
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ALTDDIO_OUT_component.lpm_hint = "UNUSED",
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ALTDDIO_OUT_component.lpm_type = "altddio_out",
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ALTDDIO_OUT_component.oe_reg = "UNREGISTERED",
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ALTDDIO_OUT_component.power_up_high = "OFF",
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ALTDDIO_OUT_component.width = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
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// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
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// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
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// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
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// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
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// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
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// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
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// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
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// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
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// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
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// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
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// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
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// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
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// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
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// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io.v TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io.qip TRUE FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io.bsf FALSE TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io_inst.v FALSE TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io_bb.v FALSE TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io.inc FALSE TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io.cmp FALSE TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL bt_ddr_io.ppf TRUE FALSE
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// Retrieval info: LIB_FILE: altera_mf

‎hdl/altera_clk_synth/build_file‎

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clk_gen_ipll_stim.v
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clk_gen_ipll.v
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pix_pll.v
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pll_config_top.v
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pll_config_intf.v
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pll_config_pll.v
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+libext+.vo+
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+libext+.v+
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-v /home/edatools/altera_12.0/quartus/eda/sim_lib/arriaii_atoms.v
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-v /home/edatools/altera_12.0/quartus/eda/sim_lib/altera_primitives.v
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-v /home/edatools/altera_12.0/quartus/eda/sim_lib/sgate.v
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-v /home/edatools/altera_12.0/quartus/eda/sim_lib/220model.v
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-v /home/edatools/altera_12.0/quartus/eda/sim_lib/altera_mf.v
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‎hdl/altera_clk_synth/clk_gen_ipll.v‎

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/////////////////////////////////////////////////////////////////////////////
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//
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// Silicon Spectrum Corporation - All Rights Reserved
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// Copyright (C) 2005
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//
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// Title : Clock switch module for non programmable PLLs
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// File : clk_switch.v
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// Author : Jim MacLeod
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// Created : 05-Mar-2013
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// RCS File : $Source:$
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// Status : $Id:$
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//
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//
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//////////////////////////////////////////////////////////////////////////////
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//
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// Description :
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// This module takes in up to 6 PLL derived clocks plus a master clock (PCI).
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// This module allows the glitchless switching amongst the clock frequencies.
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// The purpose of this is to allow an FPGA w/o a programmable PLL
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// (ex Cyclone2) to provide us with a variety of frequencies for generating
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// Pixel clock and CRT clocks.
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//
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//////////////////////////////////////////////////////////////////////////////
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//
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// Modules Instantiated:
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//
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///////////////////////////////////////////////////////////////////////////////
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//
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// Modification History:
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//
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// $Log:$
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//
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//
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///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ns / 10 ps
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module clk_gen_ipll
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(
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input hb_clk,
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input hb_resetn,
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input refclk,
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input [1:0] bpp,
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input vga_mode,
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input write_param, // input
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input [3:0] counter_type, // input [3:0]
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input [2:0] counter_param, // input[2:0]
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input [8:0] data_in, // input [8:0],
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input reconfig, // input.
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input pll_areset_in, // input.
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output busy, // Input busy.
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output pix_clk,
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output pix_clk_vga,
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output reg crt_clk,
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output pix_locked
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);
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pix_pll_rc_top u_pix_pll_rc_top
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(
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.hb_clk (hb_clk),
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.hb_rstn (hb_resetn),
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.ref_clk (refclk),
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.reconfig (reconfig),
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.write_param (write_param),
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.counter_param (counter_param),// Input [2:0]
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.counter_type (counter_type), // Input [3:0]
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.data_in (data_in), // Input [8:0]
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.pll_areset_in (pll_areset_in),
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.busy (busy), // output.
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.pix_clk (pix_clk), // output.
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.pix_locked (pix_locked) // output.
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);
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reg [2:0] crt_counter;
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reg [1:0] crt_divider;
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always @*
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begin
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casex({vga_mode, bpp})
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3'b1_xx: crt_divider = 2'b00;
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3'b0_01: crt_divider = 2'b10;
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3'b0_10: crt_divider = 2'b01;
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default: crt_divider = 2'b00;
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endcase
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end
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always @(posedge pix_clk or negedge hb_resetn)
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begin
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if(!hb_resetn)
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begin
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crt_clk <= 1'b1;
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crt_counter <= 3'b000;
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end
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else begin
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crt_counter <= crt_counter + 3'h1;
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case (crt_divider)
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0: crt_clk <= 1'b1;
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1: crt_clk <= ~crt_counter[0];
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2: crt_clk <= ~|crt_counter[1:0];
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3: crt_clk <= ~|crt_counter[2:0];
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endcase
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end
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end
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endmodule
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