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drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case
To support high-resolution cases that exceed the width limitation of a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate, additional pipes are necessary to enable parallel data processing within the SSPP width constraints and MDP clock rate. Request 4 mixers and 4 DSCs for high-resolution cases where both DSC and dual interfaces are enabled. More use cases can be incorporated later if quad-pipe capabilities are required. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/675418/ Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-10-ff6232e3472f@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
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-33
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6 files changed

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lines changed

‎drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
200200
struct dpu_crtc_state *crtc_state)
201201
{
202202
struct dpu_crtc_mixer *m;
203-
u32 crcs[CRTC_DUAL_MIXERS];
203+
u32 crcs[CRTC_QUAD_MIXERS];
204204

205205
int rc = 0;
206206
int i;
@@ -1328,6 +1328,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
13281328
struct drm_display_mode *mode = &crtc_state->adjusted_mode;
13291329
struct msm_display_topology topology = {0};
13301330
struct drm_encoder *drm_enc;
1331+
u32 num_rt_intf;
13311332

13321333
drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
13331334
dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state,
@@ -1341,11 +1342,14 @@ static struct msm_display_topology dpu_crtc_get_topology(
13411342
* Dual display
13421343
* 2 LM, 2 INTF ( Split display using 2 interfaces)
13431344
*
1345+
* If DSC is enabled, try to use 4:4:2 topology if there is enough
1346+
* resource. Otherwise, use 2:2:2 topology.
1347+
*
13441348
* Single display
13451349
* 1 LM, 1 INTF
13461350
* 2 LM, 1 INTF (stream merge to support high resolution interfaces)
13471351
*
1348-
* If DSC is enabled, use 2 LMs for 2:2:1 topology
1352+
* If DSC is enabled, use 2:2:1 topology
13491353
*
13501354
* Add dspps to the reservation requirements if ctm is requested
13511355
*
@@ -1357,14 +1361,23 @@ static struct msm_display_topology dpu_crtc_get_topology(
13571361
* (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
13581362
*/
13591363

1360-
if (topology.num_intf == 2 && !topology.cwb_enabled)
1361-
topology.num_lm = 2;
1362-
else if (topology.num_dsc == 2)
1364+
num_rt_intf = topology.num_intf;
1365+
if (topology.cwb_enabled)
1366+
num_rt_intf--;
1367+
1368+
if (topology.num_dsc) {
1369+
if (dpu_kms->catalog->dsc_count >= num_rt_intf * 2)
1370+
topology.num_dsc = num_rt_intf * 2;
1371+
else
1372+
topology.num_dsc = num_rt_intf;
1373+
topology.num_lm = topology.num_dsc;
1374+
} else if (num_rt_intf == 2) {
13631375
topology.num_lm = 2;
1364-
else if (dpu_kms->catalog->caps->has_3d_merge)
1376+
} else if (dpu_kms->catalog->caps->has_3d_merge) {
13651377
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
1366-
else
1378+
} else {
13671379
topology.num_lm = 1;
1380+
}
13681381

13691382
if (crtc_state->ctm)
13701383
topology.num_dspp = topology.num_lm;

‎drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -210,18 +210,18 @@ struct dpu_crtc_state {
210210

211211
bool bw_control;
212212
bool bw_split_vote;
213-
struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
213+
struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];
214214

215215
uint64_t input_fence_timeout_ns;
216216

217217
struct dpu_core_perf_params new_perf;
218218

219219
/* HW Resources reserved for the crtc */
220220
u32 num_mixers;
221-
struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
221+
struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];
222222

223223
u32 num_ctls;
224-
struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
224+
struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];
225225

226226
enum dpu_crtc_crc_source crc_source;
227227
int crc_frame_skip_count;

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c‎

Lines changed: 9 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@
5555
#define MAX_PHYS_ENCODERS_PER_VIRTUAL \
5656
(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
5757

58-
#define MAX_CHANNELS_PER_ENC 2
58+
#define MAX_CHANNELS_PER_ENC 4
5959
#define MAX_CWB_PER_ENC 2
6060

6161
#define IDLE_SHORT_TIMEOUT 1
@@ -661,7 +661,6 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
661661
struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
662662
struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
663663
struct msm_display_info *disp_info = &dpu_enc->disp_info;
664-
struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
665664
struct drm_connector *connector;
666665
struct drm_connector_state *conn_state;
667666
struct drm_framebuffer *fb;
@@ -675,22 +674,12 @@ void dpu_encoder_update_topology(struct drm_encoder *drm_enc,
675674

676675
dsc = dpu_encoder_get_dsc_config(drm_enc);
677676

678-
/* We only support 2 DSC mode (with 2 LM and 1 INTF) */
679-
if (dsc) {
680-
/*
681-
* Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
682-
* when Display Stream Compression (DSC) is enabled,
683-
* and when enough DSC blocks are available.
684-
* This is power-optimal and can drive up to (including) 4k
685-
* screens.
686-
*/
687-
WARN(topology->num_intf > 2,
688-
"DSC topology cannot support more than 2 interfaces\n");
689-
if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
690-
topology->num_dsc = 2;
691-
else
692-
topology->num_dsc = 1;
693-
}
677+
/*
678+
* Set DSC number as 1 to mark the enabled status, will be adjusted
679+
* in dpu_crtc_get_topology()
680+
*/
681+
if (dsc)
682+
topology->num_dsc = 1;
694683

695684
connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
696685
if (!connector)
@@ -2180,8 +2169,8 @@ static void dpu_encoder_helper_reset_mixers(struct dpu_encoder_phys *phys_enc)
21802169
{
21812170
int i, num_lm;
21822171
struct dpu_global_state *global_state;
2183-
struct dpu_hw_blk *hw_lm[2];
2184-
struct dpu_hw_mixer *hw_mixer[2];
2172+
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
2173+
struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];
21852174
struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
21862175

21872176
/* reset all mixers for this encoder */

‎drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
302302

303303
/* Use merge_3d unless DSC MERGE topology is used */
304304
if (phys_enc->split_role == ENC_ROLE_SOLO &&
305-
dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
305+
(dpu_cstate->num_mixers != 1) &&
306306
!dpu_encoder_use_dsc_merge(phys_enc->parent))
307307
return BLEND_3D_H_ROW_INT;
308308

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
#define DPU_MAX_IMG_WIDTH 0x3fff
2525
#define DPU_MAX_IMG_HEIGHT 0x3fff
2626

27-
#define CRTC_DUAL_MIXERS 2
27+
#define CRTC_QUAD_MIXERS 4
2828

2929
#define MAX_XIN_COUNT 16
3030

‎drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
#define DPU_MAX_PLANES 4
3535
#endif
3636

37-
#define STAGES_PER_PLANE 1
37+
#define STAGES_PER_PLANE 2
3838
#define PIPES_PER_STAGE 2
3939
#define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE)
4040
#ifndef DPU_MAX_DE_CURVES

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