ARM64-SVE: Use non predicated instruction when mask is all true

[a74nh]

Consider:

static void truecndselect1(Vector<int> op1, Vector<int> op2) {
  var result1 = Sve.ConditionalSelect(Sve.CreateTrueMaskInt32(), Sve.Add(op1, op2), op1);
  Consume(result1);
}

G_M21589_IG01:  ;; offset=0x0000
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
						;; size=8 bbWeight=1 PerfScore 1.50
G_M21589_IG02:  ;; offset=0x0008
            add     z0.s, z0.s, z1.s
            movz    x0, #0x72B8      // code for CSharpTutorials.Program:Consume[System.Numerics.Vector`1[int]](System.Numerics.Vector`1[int])
            movk    x0, #0x2218 LSL #16
            movk    x0, #0xE088 LSL #32
            ldr     x0, [x0]
            blr     x0
						;; size=24 bbWeight=1 PerfScore 7.50
G_M21589_IG03:  ;; offset=0x0020
            ldp     fp, lr, [sp], #0x10
            ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00



static void truecndselect2(Vector<int> op1, Vector<int> op2) {
  var result2 = Sve.ConditionalSelect(Vector<int>.AllBitsSet, Sve.Add(op1, op2), op1);
  Consume(result2);
}

G_M25078_IG01:  ;; offset=0x0000
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
						;; size=8 bbWeight=1 PerfScore 1.50
G_M25078_IG02:  ;; offset=0x0008
            ptrue   p0.s
            mvni    v16.4s, #0
            cmpne   p0.s, p0/z, z16.s, #0
            add     z0.s, p0/m, z0.s, z1.s
            movz    x0, #0x72B8      // code for CSharpTutorials.Program:Consume[System.Numerics.Vector`1[int]](System.Numerics.Vector`1[int])
            movk    x0, #0x2218 LSL #16
            movk    x0, #0xE088 LSL #32
            ldr     x0, [x0]
            blr     x0
						;; size=36 bbWeight=1 PerfScore 12.00
G_M25078_IG03:  ;; offset=0x002C
            ldp     fp, lr, [sp], #0x10
            ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00

For both of these, a non-predicated ADD can be used, optimising away the mask. Becoming:

            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
            add     z0.s, z0.s, z1.s
            movz    x0, #0x72B8      // code for CSharpTutorials.Program:Consume[System.Numerics.Vector`1[int]](System.Numerics.Vector`1[int])
            movk    x0, #0x2218 LSL #16
            movk    x0, #0xE088 LSL #32
            ldr     x0, [x0]
            blr     x0
            ldp     fp, lr, [sp], #0x10
            ret     lr

This should be possible for all HW_Flag_OptionalEmbeddedMaskedOperation instructions: ADD, AND, BIC, ORR, SUB, EOR

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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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[JulieLeeMSFT]

@a74nh, I am triaging untriaged issues. Do we plan to work on this item in .NET 10?

[a74nh]

@a74nh, I am triaging untriaged issues. Do we plan to work on this item in .NET 10?

I think this should be part of the list of SVE issues we are looking at for .NET 10

[a74nh]

This will be fixed by #115566

; Assembly listing for method CSharpTutorials.Program:truecndselect1(System.Numerics.Vector`1[int],System.Numerics.Vector`1[int]) (FullOpts)
; Emitting BLENDED_CODE for generic ARM64 - Unix
; FullOpts code
; optimized code
; fp based frame
; partially interruptible
; No PGO data
; Final local variable assignments
;
;  V00 arg0         [V00,T00] (  3,  3   )  simd16  ->   d0         single-def <System.Numerics.Vector`1[int]>
;  V01 arg1         [V01,T01] (  3,  3   )  simd16  ->   d1         single-def <System.Numerics.Vector`1[int]>
;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [sp+0x00]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
;
; Lcl frame size = 0

G_M21589_IG01:  ;; offset=0x0000
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
						;; size=8 bbWeight=1 PerfScore 1.50
G_M21589_IG02:  ;; offset=0x0008
            add     z0.s, z0.s, z1.s
            movz    x0, #0x4480      // code for CSharpTutorials.Program:Consume[int](System.Numerics.Vector`1[int])
            movk    x0, #0xD1F5 LSL #16
            movk    x0, #0xE399 LSL #32
            ldr     x0, [x0]
            blr     x0
						;; size=24 bbWeight=1 PerfScore 7.50
G_M21589_IG03:  ;; offset=0x0020
            ldp     fp, lr, [sp], #0x10
            ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00

; Total bytes of code 40, prolog size 8, PerfScore 11.00, instruction count 10, allocated bytes for code 40 (MethodHash=25b1abaa) for method CSharpTutorials.Program:truecndselect1(System.Numerics.Vector`1[int],System.Numerics.Vector`1[int]) (FullOpts)
; ============================================================

; Assembly listing for method CSharpTutorials.Program:truecndselect2(System.Numerics.Vector`1[int],System.Numerics.Vector`1[int]) (FullOpts)
; Emitting BLENDED_CODE for generic ARM64 - Unix
; FullOpts code
; optimized code
; fp based frame
; partially interruptible
; No PGO data
; Final local variable assignments
;
;  V00 arg0         [V00,T00] (  3,  3   )  simd16  ->   d0         single-def <System.Numerics.Vector`1[int]>
;  V01 arg1         [V01,T01] (  3,  3   )  simd16  ->   d1         single-def <System.Numerics.Vector`1[int]>
;# V02 OutArgs      [V02    ] (  1,  1   )  struct ( 0) [sp+0x00]   do-not-enreg[XS] addr-exposed "OutgoingArgSpace" <Empty>
;
; Lcl frame size = 0

G_M25078_IG01:  ;; offset=0x0000
            stp     fp, lr, [sp, #-0x10]!
            mov     fp, sp
						;; size=8 bbWeight=1 PerfScore 1.50
G_M25078_IG02:  ;; offset=0x0008
            add     z0.s, z0.s, z1.s
            movz    x0, #0x4480      // code for CSharpTutorials.Program:Consume[int](System.Numerics.Vector`1[int])
            movk    x0, #0xD1F5 LSL #16
            movk    x0, #0xE399 LSL #32
            ldr     x0, [x0]
            blr     x0
						;; size=24 bbWeight=1 PerfScore 7.50
G_M25078_IG03:  ;; offset=0x0020
            ldp     fp, lr, [sp], #0x10
            ret     lr
						;; size=8 bbWeight=1 PerfScore 2.00

; Total bytes of code 40, prolog size 8, PerfScore 11.00, instruction count 10, allocated bytes for code 40 (MethodHash=0e3a9e09) for method CSharpTutorials.Program:truecndselect2(System.Numerics.Vector`1[int],System.Numerics.Vector`1[int]) (FullOpts)
; ============================================================