From 300dfc669bfa0df0dbcec06535025e570981c86f Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Mon, 15 Jul 2024 17:05:55 -0700 Subject: [PATCH 1/2] Move GenTreeVecCon and GenTreeMskCon under the respective FEATURE_* defines --- src/coreclr/jit/assertionprop.cpp | 4 +- src/coreclr/jit/codegenarm64.cpp | 4 +- src/coreclr/jit/codegenarmarch.cpp | 4 ++ src/coreclr/jit/codegencommon.cpp | 7 ++ src/coreclr/jit/codegenxarch.cpp | 16 ++--- src/coreclr/jit/compiler.h | 9 ++- src/coreclr/jit/compiler.hpp | 4 ++ src/coreclr/jit/gentree.cpp | 79 ++++++++++++++++------- src/coreclr/jit/gentree.h | 100 ++++++++++++++++++----------- src/coreclr/jit/gtlist.h | 4 ++ src/coreclr/jit/gtstructs.h | 6 +- src/coreclr/jit/importer.cpp | 8 ++- src/coreclr/jit/instr.cpp | 10 ++- src/coreclr/jit/lclvars.cpp | 2 +- src/coreclr/jit/liveness.cpp | 4 ++ src/coreclr/jit/lsra.cpp | 4 ++ src/coreclr/jit/lsraarm64.cpp | 4 ++ src/coreclr/jit/lsraxarch.cpp | 4 ++ src/coreclr/jit/optcse.cpp | 4 ++ 19 files changed, 195 insertions(+), 82 deletions(-) diff --git a/src/coreclr/jit/assertionprop.cpp b/src/coreclr/jit/assertionprop.cpp index 6587421dde380e..d57f19b9a3d63c 100644 --- a/src/coreclr/jit/assertionprop.cpp +++ b/src/coreclr/jit/assertionprop.cpp @@ -2939,7 +2939,7 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G } break; -#if FEATURE_SIMD +#if defined(FEATURE_SIMD) case TYP_SIMD8: { simd8_t value = vnStore->ConstantValue(vnCns); @@ -2998,6 +2998,7 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G break; #endif // TARGET_XARCH +#endif // FEATURE_SIMD #if defined(FEATURE_MASKED_HW_INTRINSICS) case TYP_MASK: @@ -3012,7 +3013,6 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G } break; #endif // FEATURE_MASKED_HW_INTRINSICS -#endif // FEATURE_SIMD case TYP_BYREF: // Do not support const byref optimization. diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 2f6ebaf56fc841..90a15e44a256f7 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2411,6 +2411,7 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre } break; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { GenTreeVecCon* vecCon = tree->AsVecCon(); @@ -2420,7 +2421,6 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre switch (tree->TypeGet()) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: case TYP_SIMD12: case TYP_SIMD16: @@ -2476,7 +2476,6 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre } break; } -#endif // FEATURE_SIMD default: { @@ -2486,6 +2485,7 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre break; } +#endif // FEATURE_SIMD default: unreached(); diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index 16cad5618112b7..9e42c0c718553a 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -186,8 +186,12 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode) case GT_CNS_INT: case GT_CNS_DBL: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS genSetRegToConst(targetReg, targetType, treeNode); genProduceReg(treeNode); break; diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp index dad1ba0b929b89..03e034c6994b95 100644 --- a/src/coreclr/jit/codegencommon.cpp +++ b/src/coreclr/jit/codegencommon.cpp @@ -8327,7 +8327,14 @@ void CodeGen::genCodeForReuseVal(GenTree* treeNode) assert(treeNode->IsReuseRegVal()); // For now, this is only used for constant nodes. +#if defined(FEATURE_MASKED_HW_INTRINSICS) assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL, GT_CNS_VEC, GT_CNS_MSK)); +#elif defined(FEATURE_SIMD) + assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL, GT_CNS_VEC)); +#else + assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL)); +#endif + JITDUMP(" TreeNode is marked ReuseReg\n"); if (treeNode->IsIntegralConst(0) && GetEmitter()->emitCurIGnonEmpty()) diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index dc9dd7c8a249bf..989772707425c1 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -724,27 +724,23 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre } break; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { -#if defined(FEATURE_SIMD) GenTreeVecCon* vecCon = tree->AsVecCon(); genSetRegToConst(vecCon->GetRegNum(), targetType, &vecCon->gtSimdVal); -#else - unreached(); -#endif break; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { -#if defined(FEATURE_MASKED_HW_INTRINSICS) GenTreeMskCon* mskCon = tree->AsMskCon(); genSetRegToConst(mskCon->GetRegNum(), targetType, &mskCon->gtSimdMaskVal); -#else - unreached(); -#endif break; } +#endif // FEATURE_MASKED_HW_INTRINSICS default: unreached(); @@ -1906,8 +1902,12 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode) FALLTHROUGH; case GT_CNS_DBL: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS genSetRegToConst(targetReg, targetType, treeNode); genProduceReg(treeNode); break; diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h index e1db3ad7421ea6..cfaee21a681439 100644 --- a/src/coreclr/jit/compiler.h +++ b/src/coreclr/jit/compiler.h @@ -3051,11 +3051,14 @@ class Compiler GenTree* gtNewSconNode(int CPX, CORINFO_MODULE_HANDLE scpHandle); +#if defined(FEATURE_SIMD) GenTreeVecCon* gtNewVconNode(var_types type); - GenTreeVecCon* gtNewVconNode(var_types type, void* data); +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) GenTreeMskCon* gtNewMskConNode(var_types type); +#endif // FEATURE_MASKED_HW_INTRINSICS GenTree* gtNewAllBitsSetConNode(var_types type); @@ -11680,8 +11683,12 @@ class GenTreeVisitor case GT_CNS_LNG: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_MEMORYBARRIER: case GT_JMP: case GT_JCC: diff --git a/src/coreclr/jit/compiler.hpp b/src/coreclr/jit/compiler.hpp index 1d409190b12470..c5357eb265c683 100644 --- a/src/coreclr/jit/compiler.hpp +++ b/src/coreclr/jit/compiler.hpp @@ -4357,8 +4357,12 @@ void GenTree::VisitOperands(TVisitor visitor) case GT_CNS_LNG: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_MEMORYBARRIER: case GT_JMP: case GT_JCC: diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index f7da7729d23752..2ba05add362932 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -240,9 +240,9 @@ void GenTree::InitNodeSize() // clang-format off GenTree::s_gtNodeSizes[GT_CALL] = TREE_NODE_SZ_LARGE; -#ifdef TARGET_XARCH +#if defined(FEATURE_SIMD) && defined(TARGET_XARCH) GenTree::s_gtNodeSizes[GT_CNS_VEC] = TREE_NODE_SZ_LARGE; -#endif // TARGET_XARCH +#endif // FEATURE_SIMD && TARGET_XARCH GenTree::s_gtNodeSizes[GT_CAST] = TREE_NODE_SZ_LARGE; GenTree::s_gtNodeSizes[GT_FTN_ADDR] = TREE_NODE_SZ_LARGE; GenTree::s_gtNodeSizes[GT_BOX] = TREE_NODE_SZ_LARGE; @@ -285,11 +285,13 @@ void GenTree::InitNodeSize() static_assert_no_msg(sizeof(GenTreeLngCon) <= TREE_NODE_SZ_SMALL); static_assert_no_msg(sizeof(GenTreeDblCon) <= TREE_NODE_SZ_SMALL); static_assert_no_msg(sizeof(GenTreeStrCon) <= TREE_NODE_SZ_SMALL); +#if defined(FEATURE_SIMD) #ifdef TARGET_XARCH static_assert_no_msg(sizeof(GenTreeVecCon) <= TREE_NODE_SZ_LARGE); // *** large node #else static_assert_no_msg(sizeof(GenTreeVecCon) <= TREE_NODE_SZ_SMALL); -#endif +#endif // TARGET_XARCH +#endif // FEATURE_SIMD static_assert_no_msg(sizeof(GenTreeLclVarCommon) <= TREE_NODE_SZ_SMALL); static_assert_no_msg(sizeof(GenTreeLclVar) <= TREE_NODE_SZ_SMALL); static_assert_no_msg(sizeof(GenTreeLclFld) <= TREE_NODE_SZ_SMALL); @@ -2767,6 +2769,7 @@ bool GenTree::Compare(GenTree* op1, GenTree* op2, bool swapOK) } break; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { if (GenTreeVecCon::Equals(op1->AsVecCon(), op2->AsVecCon())) @@ -2775,7 +2778,9 @@ bool GenTree::Compare(GenTree* op1, GenTree* op2, bool swapOK) } break; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { if (GenTreeMskCon::Equals(op1->AsMskCon(), op2->AsMskCon())) @@ -2784,6 +2789,7 @@ bool GenTree::Compare(GenTree* op1, GenTree* op2, bool swapOK) } break; } +#endif // FEATURE_MASKED_HW_INTRINSICS default: break; @@ -3310,6 +3316,7 @@ unsigned Compiler::gtHashValue(GenTree* tree) add = tree->AsStrCon()->gtSconCPX; break; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { GenTreeVecCon* vecCon = tree->AsVecCon(); @@ -3317,7 +3324,6 @@ unsigned Compiler::gtHashValue(GenTree* tree) switch (vecCon->TypeGet()) { -#if defined(FEATURE_SIMD) #if defined(TARGET_XARCH) case TYP_SIMD64: { @@ -3360,7 +3366,6 @@ unsigned Compiler::gtHashValue(GenTree* tree) add = genTreeHashAdd(ulo32(add), vecCon->gtSimdVal.u32[0]); break; } -#endif // FEATURE_SIMD default: { @@ -3369,20 +3374,19 @@ unsigned Compiler::gtHashValue(GenTree* tree) } break; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { GenTreeMskCon* mskCon = tree->AsMskCon(); add = 0; -#if defined(FEATURE_MASKED_HW_INTRINSICS) add = genTreeHashAdd(ulo32(add), mskCon->gtSimdMaskVal.u32[1]); add = genTreeHashAdd(ulo32(add), mskCon->gtSimdMaskVal.u32[0]); -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS break; } +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_JMP: add = tree->AsVal()->gtVal1; @@ -5256,6 +5260,7 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree) } break; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { level = 0; @@ -5279,7 +5284,9 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree) } break; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { level = 0; @@ -5296,6 +5303,7 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree) } break; } +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_LCL_VAR: level = 1; @@ -6522,8 +6530,12 @@ bool GenTree::TryGetUse(GenTree* operand, GenTree*** pUse) case GT_CNS_LNG: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_MEMORYBARRIER: case GT_JMP: case GT_JCC: @@ -7741,6 +7753,7 @@ GenTree* Compiler::gtNewSconNode(int CPX, CORINFO_MODULE_HANDLE scpHandle) return node; } +#if defined(FEATURE_SIMD) GenTreeVecCon* Compiler::gtNewVconNode(var_types type) { GenTreeVecCon* vecCon = new (this, GT_CNS_VEC) GenTreeVecCon(type); @@ -7753,12 +7766,15 @@ GenTreeVecCon* Compiler::gtNewVconNode(var_types type, void* data) memcpy(&vecCon->gtSimdVal, data, genTypeSize(type)); return vecCon; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) GenTreeMskCon* Compiler::gtNewMskConNode(var_types type) { GenTreeMskCon* mskCon = new (this, GT_CNS_MSK) GenTreeMskCon(type); return mskCon; } +#endif // FEATURE_MASKED_HW_INTRINSICS GenTree* Compiler::gtNewAllBitsSetConNode(var_types type) { @@ -8076,6 +8092,7 @@ GenTree* Compiler::gtNewConWithPattern(var_types type, uint8_t pattern) case TYP_BYREF: assert(pattern == 0); return gtNewZeroConNode(type); + #ifdef FEATURE_SIMD case TYP_SIMD8: case TYP_SIMD12: @@ -8084,12 +8101,13 @@ GenTree* Compiler::gtNewConWithPattern(var_types type, uint8_t pattern) case TYP_SIMD32: case TYP_SIMD64: #endif // TARGET_XARCH -#endif // FEATURE_SIMD { GenTreeVecCon* node = gtNewVconNode(type); memset(&node->gtSimdVal, pattern, sizeof(node->gtSimdVal)); return node; } +#endif // FEATURE_SIMD + default: unreached(); } @@ -8262,10 +8280,10 @@ GenTreeLclVar* Compiler::gtNewLclvNode(unsigned lnum, var_types type DEBUGARG(IL LclVarDsc* varDsc = lvaGetDesc(lnum); bool simd12ToSimd16Widening = false; -#if FEATURE_SIMD +#if defined(FEATURE_SIMD) // We can additionally have a SIMD12 that was widened to a SIMD16, generally as part of lowering simd12ToSimd16Widening = (type == TYP_SIMD16) && (varDsc->lvType == TYP_SIMD12); -#endif +#endif // FEATURE_SIMD assert((type == varDsc->lvType) || simd12ToSimd16Widening || (lvaIsImplicitByRefLocal(lnum) && fgGlobalMorph && (varDsc->lvType == TYP_BYREF))); } @@ -8431,9 +8449,18 @@ void Compiler::gtInitializeStoreNode(GenTree* store, GenTree* value) } #else // TARGET_X86 // TODO-Cleanup: merge into the all-arch. - if (varTypeIsSIMD(value) && value->OperIs(GT_HWINTRINSIC, GT_CNS_VEC, GT_CNS_MSK)) + if (varTypeIsSIMD(value) || varTypeIsMask(value)) { - SetOpLclRelatedToSIMDIntrinsic(store); + bool isRelatedToSimdIntrinsic = value->OperIs(GT_HWINTRINSIC, GT_CNS_VEC); + +#if defined(FEATURE_MASKED_HW_INTRINSICS) + isRelatedToSimdIntrinsic |= value->OperIs(GT_CNS_MSK); +#endif // FEATURE_MASKED_HW_INTRINSICS + + if (isRelatedToSimdIntrinsic) + { + SetOpLclRelatedToSIMDIntrinsic(store); + } } #endif // TARGET_X86 #endif // FEATURE_SIMD @@ -9063,6 +9090,7 @@ GenTree* Compiler::gtClone(GenTree* tree, bool complexOK) break; } +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet()); @@ -9070,18 +9098,17 @@ GenTree* Compiler::gtClone(GenTree* tree, bool complexOK) copy = vecCon; break; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { -#if defined(FEATURE_MASKED_HW_INTRINSICS) GenTreeMskCon* mskCon = gtNewMskConNode(tree->TypeGet()); mskCon->gtSimdMaskVal = tree->AsMskCon()->gtSimdMaskVal; copy = mskCon; -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS break; } +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_FTN_ADDR: { @@ -9254,6 +9281,7 @@ GenTree* Compiler::gtCloneExpr(GenTree* tree) copy = gtNewSconNode(tree->AsStrCon()->gtSconCPX, tree->AsStrCon()->gtScpHnd); goto DONE; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { GenTreeVecCon* vecCon = gtNewVconNode(tree->TypeGet()); @@ -9261,18 +9289,17 @@ GenTree* Compiler::gtCloneExpr(GenTree* tree) copy = vecCon; goto DONE; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { -#if defined(FEATURE_MASKED_HW_INTRINSICS) GenTreeMskCon* mskCon = gtNewMskConNode(tree->TypeGet()); mskCon->gtSimdMaskVal = tree->AsMskCon()->gtSimdMaskVal; copy = mskCon; goto DONE; -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS } +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_LCL_VAR: @@ -10060,8 +10087,12 @@ GenTreeUseEdgeIterator::GenTreeUseEdgeIterator(GenTree* node) case GT_CNS_LNG: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_MEMORYBARRIER: case GT_JMP: case GT_JCC: @@ -12096,6 +12127,7 @@ void Compiler::gtDispConst(GenTree* tree) break; } +#endif // FEATURE_SIMD #if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: @@ -12105,7 +12137,6 @@ void Compiler::gtDispConst(GenTree* tree) break; } #endif // FEATURE_MASKED_HW_INTRINSICS -#endif // FEATURE_SIMD default: assert(!"unexpected constant node"); @@ -30519,6 +30550,7 @@ GenTree* Compiler::gtFoldExprHWIntrinsic(GenTreeHWIntrinsic* tree) } resultNode = cnsNode; } +#if defined(FEATURE_MASKED_HW_INTRINSICS) else if (tree->OperIsConvertMaskToVector()) { GenTreeMskCon* mskCon = cnsNode->AsMskCon(); @@ -30575,6 +30607,7 @@ GenTree* Compiler::gtFoldExprHWIntrinsic(GenTreeHWIntrinsic* tree) resultNode = mskCon; } +#endif // FEATURE_MASKED_HW_INTRINSICS else { switch (ni) diff --git a/src/coreclr/jit/gentree.h b/src/coreclr/jit/gentree.h index 757ce23912d732..73ae35360bccea 100644 --- a/src/coreclr/jit/gentree.h +++ b/src/coreclr/jit/gentree.h @@ -895,8 +895,34 @@ struct GenTree bool isUsedFromMemory() const { - return ((isContained() && (isMemoryOp() || OperIs(GT_LCL_VAR, GT_CNS_DBL, GT_CNS_VEC, GT_CNS_MSK))) || - isUsedFromSpillTemp()); + if (isContained()) + { + if (isMemoryOp()) + { + return true; + } + + if (OperIs(GT_LCL_VAR, GT_CNS_DBL)) + { + return true; + } + +#if defined(FEATURE_SIMD) + if (OperIs(GT_CNS_VEC)) + { + return true; + } +#endif // FEATURE_SIMD + +#if defined(FEATURE_MASKED_HW_INTRINSICS) + if (OperIs(GT_CNS_MSK)) + { + return true; + } +#endif // FEATURE_MASKED_HW_INTRINSICS + } + + return isUsedFromSpillTemp(); } bool isUsedFromReg() const @@ -1089,8 +1115,16 @@ struct GenTree static bool OperIsConst(genTreeOps gtOper) { +#if defined(FEATURE_MASKED_HW_INTRINSICS) static_assert_no_msg(AreContiguous(GT_CNS_INT, GT_CNS_LNG, GT_CNS_DBL, GT_CNS_STR, GT_CNS_VEC, GT_CNS_MSK)); return (GT_CNS_INT <= gtOper) && (gtOper <= GT_CNS_MSK); +#elif defined(FEATURE_SIMD) + static_assert_no_msg(AreContiguous(GT_CNS_INT, GT_CNS_LNG, GT_CNS_DBL, GT_CNS_STR, GT_CNS_VEC)); + return (GT_CNS_INT <= gtOper) && (gtOper <= GT_CNS_VEC); +#else + static_assert_no_msg(AreContiguous(GT_CNS_INT, GT_CNS_LNG, GT_CNS_DBL, GT_CNS_STR)); + return (GT_CNS_INT <= gtOper) && (gtOper <= GT_CNS_STR); +#endif } bool OperIsConst() const @@ -6641,6 +6675,7 @@ struct GenTreeHWIntrinsic : public GenTreeJitIntrinsic }; #endif // FEATURE_HW_INTRINSICS +#if defined(FEATURE_SIMD) // GenTreeVecCon -- vector constant (GT_CNS_VEC) // struct GenTreeVecCon : public GenTree @@ -6883,7 +6918,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { simd8_t result = {}; @@ -6925,7 +6959,6 @@ struct GenTreeVecCon : public GenTree break; } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -6941,7 +6974,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { simd8_t result = {}; @@ -6983,7 +7015,6 @@ struct GenTreeVecCon : public GenTree break; } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -6996,7 +7027,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { simd8_t result = {}; @@ -7038,7 +7068,6 @@ struct GenTreeVecCon : public GenTree break; } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -7051,7 +7080,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { return gtSimd8Val.IsAllBitsSet(); @@ -7079,7 +7107,6 @@ struct GenTreeVecCon : public GenTree } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -7101,7 +7128,6 @@ struct GenTreeVecCon : public GenTree switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { return left->gtSimd8Val == right->gtSimd8Val; @@ -7129,7 +7155,6 @@ struct GenTreeVecCon : public GenTree } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -7146,7 +7171,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { return gtSimd8Val.IsZero(); @@ -7174,7 +7198,6 @@ struct GenTreeVecCon : public GenTree } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -7187,7 +7210,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { return EvaluateGetElementFloating(simdBaseType, gtSimd8Val, index); @@ -7214,7 +7236,6 @@ struct GenTreeVecCon : public GenTree return EvaluateGetElementFloating(simdBaseType, gtSimd64Val, index); } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -7227,7 +7248,6 @@ struct GenTreeVecCon : public GenTree { switch (gtType) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { return EvaluateGetElementIntegral(simdBaseType, gtSimd8Val, index); @@ -7254,7 +7274,6 @@ struct GenTreeVecCon : public GenTree return EvaluateGetElementIntegral(simdBaseType, gtSimd64Val, index); } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -7345,13 +7364,12 @@ struct GenTreeVecCon : public GenTree #endif }; +#if defined(FEATURE_MASKED_HW_INTRINSICS) // GenTreeMskCon -- mask constant (GT_CNS_MSK) // struct GenTreeMskCon : public GenTree { -#if defined(FEATURE_MASKED_HW_INTRINSICS) simdmask_t gtSimdMaskVal; -#endif // FEATURE_MASKED_HW_INTRINSICS void EvaluateUnaryInPlace(genTreeOps oper, bool scalar, var_types baseType, unsigned simdSize); void EvaluateBinaryInPlace( @@ -7359,29 +7377,17 @@ struct GenTreeMskCon : public GenTree bool IsAllBitsSet() const { -#if defined(FEATURE_MASKED_HW_INTRINSICS) return gtSimdMaskVal.IsAllBitsSet(); -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS } static bool Equals(const GenTreeMskCon* left, const GenTreeMskCon* right) { -#if defined(FEATURE_MASKED_HW_INTRINSICS) return left->gtSimdMaskVal == right->gtSimdMaskVal; -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS } bool IsZero() const { -#if defined(FEATURE_MASKED_HW_INTRINSICS) return gtSimdMaskVal.IsZero(); -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS } GenTreeMskCon(var_types type) @@ -7389,13 +7395,9 @@ struct GenTreeMskCon : public GenTree { assert(varTypeIsMask(type)); -#if defined(FEATURE_MASKED_HW_INTRINSICS) // Some uses of GenTreeMskCon do not specify all bits in the mask they are using but failing to zero out the // buffer will cause determinism issues with the compiler. memset(>SimdMaskVal, 0, sizeof(gtSimdMaskVal)); -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS } #if DEBUGGABLE_GENTREE @@ -7405,6 +7407,8 @@ struct GenTreeMskCon : public GenTree } #endif }; +#endif // FEATURE_MASKED_HW_INTRINSICS +#endif // FEATURE_SIMD // GenTreeIndexAddr: Given an array object and an index, checks that the index is within the bounds of the array if // necessary and produces the address of the value at that index of the array. @@ -9597,7 +9601,11 @@ inline bool GenTree::IsFloatPositiveZero() const // inline bool GenTree::IsVectorZero() const { +#if defined(FEATURE_SIMD) return IsCnsVec() && AsVecCon()->IsZero(); +#else + return false; +#endif // FEATURE_SIMD } //------------------------------------------------------------------- @@ -9611,8 +9619,12 @@ inline bool GenTree::IsVectorZero() const // inline bool GenTree::IsVectorNegativeZero(var_types simdBaseType) const { +#if defined(FEATURE_SIMD) assert(varTypeIsFloating(simdBaseType)); return IsCnsVec() && AsVecCon()->IsNegativeZero(simdBaseType); +#else + return false; +#endif // FEATURE_SIMD } //------------------------------------------------------------------- @@ -9626,8 +9638,12 @@ inline bool GenTree::IsVectorNegativeZero(var_types simdBaseType) const // inline bool GenTree::IsVectorNaN(var_types simdBaseType) const { +#if defined(FEATURE_SIMD) assert(varTypeIsFloating(simdBaseType)); return IsCnsVec() && AsVecCon()->IsNaN(simdBaseType); +#else + return false; +#endif // FEATURE_SIMD } //------------------------------------------------------------------- @@ -10506,12 +10522,20 @@ inline bool GenTree::IsCnsNonZeroFltOrDbl() const inline bool GenTree::IsCnsVec() const { +#if defined(FEATURE_SIMD) return OperIs(GT_CNS_VEC); +#else + return false; +#endif // FEATURE_SIMD } inline bool GenTree::IsCnsMsk() const { +#if defined(FEATURE_MASKED_HW_INTRINSICS) return OperIs(GT_CNS_MSK); +#else + return false; +#endif // FEATURE_MASKED_HW_INTRINSICS } inline bool GenTree::IsHelperCall() @@ -10580,8 +10604,12 @@ const size_t TREE_NODE_SZ_SMALL = sizeof(GenTreeLclFld); // the largest by a small margin due to needing to carry a simd64_t // constant value. Otherwise, GenTreeCall is the largest. +#if defined(FEATURE_SIMD) const size_t TREE_NODE_SZ_LARGE = (sizeof(GenTreeVecCon) < sizeof(GenTreeCall)) ? sizeof(GenTreeCall) : sizeof(GenTreeVecCon); +#else +const size_t TREE_NODE_SZ_LARGE = sizeof(GenTreeCall); +#endif // FEATURE_SIMD enum varRefKinds { diff --git a/src/coreclr/jit/gtlist.h b/src/coreclr/jit/gtlist.h index e1e1f909896276..8c6c67fd6a3273 100644 --- a/src/coreclr/jit/gtlist.h +++ b/src/coreclr/jit/gtlist.h @@ -46,8 +46,12 @@ GTNODE(CNS_INT , GenTreeIntCon ,0,0,GTK_LEAF) GTNODE(CNS_LNG , GenTreeLngCon ,0,0,GTK_LEAF) GTNODE(CNS_DBL , GenTreeDblCon ,0,0,GTK_LEAF) GTNODE(CNS_STR , GenTreeStrCon ,0,0,GTK_LEAF) +#if defined(FEATURE_SIMD) GTNODE(CNS_VEC , GenTreeVecCon ,0,0,GTK_LEAF) +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) GTNODE(CNS_MSK , GenTreeMskCon ,0,0,GTK_LEAF) +#endif // FEATURE_MASKED_HW_INTRINSICS //----------------------------------------------------------------------------- // Unary operators (1 operand): diff --git a/src/coreclr/jit/gtstructs.h b/src/coreclr/jit/gtstructs.h index 7dbf6af39c5d01..26f88d17909974 100644 --- a/src/coreclr/jit/gtstructs.h +++ b/src/coreclr/jit/gtstructs.h @@ -60,8 +60,12 @@ GTSTRUCT_1(IntCon , GT_CNS_INT) GTSTRUCT_1(LngCon , GT_CNS_LNG) GTSTRUCT_1(DblCon , GT_CNS_DBL) GTSTRUCT_1(StrCon , GT_CNS_STR) +#if defined(FEATURE_SIMD) GTSTRUCT_1(VecCon , GT_CNS_VEC) +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) GTSTRUCT_1(MskCon , GT_CNS_MSK) +#endif // FEATURE_MASKED_HW_INTRINSICS GTSTRUCT_N(LclVarCommon, GT_LCL_VAR, GT_LCL_FLD, GT_PHI_ARG, GT_STORE_LCL_VAR, GT_STORE_LCL_FLD, GT_LCL_ADDR) GTSTRUCT_2(LclVar , GT_LCL_VAR, GT_STORE_LCL_VAR) GTSTRUCT_3(LclFld , GT_LCL_FLD, GT_STORE_LCL_FLD, GT_LCL_ADDR) @@ -76,7 +80,7 @@ GTSTRUCT_1(Intrinsic , GT_INTRINSIC) GTSTRUCT_1(IndexAddr , GT_INDEX_ADDR) #if defined(FEATURE_HW_INTRINSICS) GTSTRUCT_N(MultiOp , GT_HWINTRINSIC) -#endif +#endif // FEATURE_HW_INTRINSICS GTSTRUCT_1(BoundsChk , GT_BOUNDS_CHECK) GTSTRUCT_3_SPECIAL(ArrCommon , GT_ARR_LENGTH, GT_MDARR_LENGTH, GT_MDARR_LOWER_BOUND) GTSTRUCT_1(ArrLen , GT_ARR_LENGTH) diff --git a/src/coreclr/jit/importer.cpp b/src/coreclr/jit/importer.cpp index d22721824939d1..49ffc744718297 100644 --- a/src/coreclr/jit/importer.cpp +++ b/src/coreclr/jit/importer.cpp @@ -232,8 +232,12 @@ void Compiler::impSaveStackState(SavedStack* savePtr, bool copy) case GT_CNS_LNG: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_LCL_VAR: table->val = gtCloneExpr(tree); break; @@ -3626,7 +3630,7 @@ GenTree* Compiler::impImportStaticReadOnlyField(CORINFO_FIELD_HANDLE field, CORI hwAccelerated = compOpportunisticallyDependsOn(InstructionSet_AVX); } else -#endif +#endif // TARGET_XARCH { // SIMD8, SIMD12, SIMD16 are covered by IsBaselineSimdIsaSupported check assert((simdType == TYP_SIMD8) || (simdType == TYP_SIMD12) || (simdType == TYP_SIMD16)); @@ -3639,7 +3643,7 @@ GenTree* Compiler::impImportStaticReadOnlyField(CORINFO_FIELD_HANDLE field, CORI return vec; } } -#endif +#endif // FEATURE_SIMD for (unsigned i = 0; i < totalSize; i++) { diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp index f31e8b364c6ed1..b4cb9983311a66 100644 --- a/src/coreclr/jit/instr.cpp +++ b/src/coreclr/jit/instr.cpp @@ -950,11 +950,11 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op) return OperandDesc(op->AsIntCon()->IconValue(), op->AsIntCon()->ImmedValNeedsReloc(compiler)); } +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { switch (op->TypeGet()) { -#if defined(FEATURE_SIMD) case TYP_SIMD8: { simd8_t constValue; @@ -991,7 +991,6 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op) } #endif // TARGET_XARCH -#endif // FEATURE_SIMD default: { @@ -999,17 +998,16 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op) } } } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { -#if defined(FEATURE_MASKED_HW_INTRINSICS) simdmask_t constValue; memcpy(&constValue, &op->AsMskCon()->gtSimdMaskVal, sizeof(simdmask_t)); return OperandDesc(emit->emitSimdMaskConst(constValue)); -#else - unreached(); -#endif // FEATURE_MASKED_HW_INTRINSICS } +#endif // FEATURE_MASKED_HW_INTRINSICS default: unreached(); diff --git a/src/coreclr/jit/lclvars.cpp b/src/coreclr/jit/lclvars.cpp index 62d3769879b20a..9e23af37bcf628 100644 --- a/src/coreclr/jit/lclvars.cpp +++ b/src/coreclr/jit/lclvars.cpp @@ -82,7 +82,7 @@ void Compiler::lvaInit() gsShadowVarInfo = nullptr; lvaPSPSym = BAD_VAR_NUM; -#if FEATURE_SIMD +#if defined(FEATURE_SIMD) lvaSIMDInitTempVarNum = BAD_VAR_NUM; #endif // FEATURE_SIMD lvaCurEpoch = 0; diff --git a/src/coreclr/jit/liveness.cpp b/src/coreclr/jit/liveness.cpp index d0ce193114529b..4e7a9305f0d308 100644 --- a/src/coreclr/jit/liveness.cpp +++ b/src/coreclr/jit/liveness.cpp @@ -1406,8 +1406,12 @@ void Compiler::fgComputeLifeLIR(VARSET_TP& life, BasicBlock* block, VARSET_VALAR case GT_CNS_LNG: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_PHYSREG: // These are all side-effect-free leaf nodes. if (node->IsUnusedValue()) diff --git a/src/coreclr/jit/lsra.cpp b/src/coreclr/jit/lsra.cpp index 763a28989b3a8e..cd29a4a71b4c7c 100644 --- a/src/coreclr/jit/lsra.cpp +++ b/src/coreclr/jit/lsra.cpp @@ -2982,6 +2982,7 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo break; } +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { return @@ -2990,11 +2991,14 @@ bool LinearScan::isMatchingConstant(RegRecord* physRegRecord, RefPosition* refPo #endif GenTreeVecCon::Equals(refPosition->treeNode->AsVecCon(), otherTreeNode->AsVecCon()); } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { return GenTreeMskCon::Equals(refPosition->treeNode->AsMskCon(), otherTreeNode->AsMskCon()); } +#endif // FEATURE_MASKED_HW_INTRINSICS) default: break; diff --git a/src/coreclr/jit/lsraarm64.cpp b/src/coreclr/jit/lsraarm64.cpp index 7a02286440df26..ed05d0fcb833bd 100644 --- a/src/coreclr/jit/lsraarm64.cpp +++ b/src/coreclr/jit/lsraarm64.cpp @@ -704,6 +704,7 @@ int LinearScan::BuildNode(GenTree* tree) } break; +#if defined(FEATURE_SIMD) case GT_CNS_VEC: { GenTreeVecCon* vecCon = tree->AsVecCon(); @@ -726,7 +727,9 @@ int LinearScan::BuildNode(GenTree* tree) def->getInterval()->isConstant = true; break; } +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: { GenTreeMskCon* mskCon = tree->AsMskCon(); @@ -749,6 +752,7 @@ int LinearScan::BuildNode(GenTree* tree) def->getInterval()->isConstant = true; break; } +#endif // FEATURE_MASKED_HW_INTRINSICS case GT_BOX: case GT_COMMA: diff --git a/src/coreclr/jit/lsraxarch.cpp b/src/coreclr/jit/lsraxarch.cpp index 9352b819d236cd..ab1143d82f5fa4 100644 --- a/src/coreclr/jit/lsraxarch.cpp +++ b/src/coreclr/jit/lsraxarch.cpp @@ -151,8 +151,12 @@ int LinearScan::BuildNode(GenTree* tree) case GT_CNS_INT: case GT_CNS_LNG: case GT_CNS_DBL: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS { srcCount = 0; diff --git a/src/coreclr/jit/optcse.cpp b/src/coreclr/jit/optcse.cpp index f633a5e3272bb5..ddff55eb033378 100644 --- a/src/coreclr/jit/optcse.cpp +++ b/src/coreclr/jit/optcse.cpp @@ -1905,8 +1905,12 @@ bool CSE_HeuristicCommon::CanConsiderTree(GenTree* tree, bool isReturn) case GT_CNS_INT: case GT_CNS_DBL: case GT_CNS_STR: +#if defined(FEATURE_SIMD) case GT_CNS_VEC: +#endif // FEATURE_SIMD +#if defined(FEATURE_MASKED_HW_INTRINSICS) case GT_CNS_MSK: +#endif // FEATURE_MASKED_HW_INTRINSICS break; case GT_ARR_ELEM: From 4560ef51e4c018c562a506b827c887735fd2a228 Mon Sep 17 00:00:00 2001 From: Tanner Gooding Date: Mon, 15 Jul 2024 17:18:44 -0700 Subject: [PATCH 2/2] Apply formatting patch --- src/coreclr/jit/gentree.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index 2ba05add362932..7e822aefada0be 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -8447,7 +8447,7 @@ void Compiler::gtInitializeStoreNode(GenTree* store, GenTree* value) SetOpLclRelatedToSIMDIntrinsic(value); } } -#else // TARGET_X86 +#else // TARGET_X86 // TODO-Cleanup: merge into the all-arch. if (varTypeIsSIMD(value) || varTypeIsMask(value)) {