diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp index cadcf0bddd8882..416c99d85d3584 100644 --- a/src/coreclr/jit/emitxarch.cpp +++ b/src/coreclr/jit/emitxarch.cpp @@ -66,11 +66,6 @@ bool emitter::IsKInstructionWithLBit(instruction ins) return (flags & KInstructionWithLBit) != 0; } -bool emitter::IsAVXOnlyInstruction(instruction ins) -{ - return (ins >= FIRST_AVX_INSTRUCTION) && (ins <= LAST_AVX_INSTRUCTION); -} - //------------------------------------------------------------------------ // IsAvx512OnlyInstruction: Is this an Avx512 instruction? // @@ -8591,29 +8586,6 @@ void emitter::emitIns_R_R_A_I(instruction ins, emitCurIGsize += sz; } -void emitter::emitIns_R_R_AR_I( - instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber base, int offs, int ival) -{ - assert(IsSimdInstruction(ins)); - assert(IsThreeOperandAVXInstruction(ins)); - - instrDesc* id = emitNewInstrAmdCns(attr, offs, ival); - - id->idIns(ins); - id->idReg1(reg1); - id->idReg2(reg2); - - id->idInsFmt(IF_RWR_RRD_ARD_CNS); - id->idAddr()->iiaAddrMode.amBaseReg = base; - id->idAddr()->iiaAddrMode.amIndxReg = REG_NA; - - UNATIVE_OFFSET sz = emitInsSizeAM(id, insCodeRM(ins), ival); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - void emitter::emitIns_R_R_C_I(instruction ins, emitAttr attr, regNumber reg1, @@ -9105,61 +9077,6 @@ void emitter::emitIns_C_I( emitCurIGsize += sz; } -void emitter::emitIns_J_S(instruction ins, emitAttr attr, BasicBlock* dst, int varx, int offs) -{ - assert(ins == INS_mov); - assert(dst->HasFlag(BBF_HAS_LABEL)); - - instrDescLbl* id = emitNewInstrLbl(); - - id->idIns(ins); - id->idInsFmt(IF_SWR_LABEL); - id->idAddr()->iiaBBlabel = dst; - - /* The label reference is always long */ - - id->idjShort = 0; - id->idjKeepLong = 1; - - /* Record the current IG and offset within it */ - - id->idjIG = emitCurIG; - id->idjOffs = emitCurIGsize; - - /* Append this instruction to this IG's jump list */ - - id->idjNext = emitCurIGjmpList; - emitCurIGjmpList = id; - - UNATIVE_OFFSET sz = sizeof(INT32) + emitInsSizeSV(id, insCodeMI(ins), varx, offs); - id->dstLclVar.initLclVarAddr(varx, offs); -#ifdef DEBUG - id->idDebugOnlyInfo()->idVarRefOffs = emitVarRefOffs; -#endif - -#if EMITTER_STATS - emitTotalIGjmps++; -#endif - -#ifndef TARGET_AMD64 - // Storing the address of a basicBlock will need a reloc - // as the instruction uses the absolute address, - // not a relative address. - // - // On Amd64, Absolute code addresses should always go through a reloc to - // to be encoded as RIP rel32 offset. - if (m_compiler->opts.compReloc) -#endif - { - id->idSetIsDspReloc(); - } - - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - /***************************************************************************** * * Add a label instruction. @@ -9341,62 +9258,6 @@ void emitter::emitIns_I_AR(instruction ins, emitAttr attr, int val, regNumber re emitCurIGsize += sz; } -void emitter::emitIns_I_AI(instruction ins, emitAttr attr, int val, ssize_t disp) -{ - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE)); - -#ifdef TARGET_AMD64 - // mov reg, imm64 is the only opcode which takes a full 8 byte immediate - // all other opcodes take a sign-extended 4-byte immediate - noway_assert(EA_SIZE(attr) < EA_8BYTE || !EA_IS_CNS_RELOC(attr)); -#endif - - insFormat fmt; - - switch (ins) - { - case INS_rcl_N: - case INS_rcr_N: - case INS_rol_N: - case INS_ror_N: - case INS_shl_N: - case INS_shr_N: - case INS_sar_N: - assert(val != 1); - fmt = IF_ARW_SHF; - val &= 0x7F; - break; - - default: - fmt = emitInsModeFormat(ins, IF_ARD_CNS); - break; - } - - /* - Useful if you want to trap moves with 0 constant - if (ins == INS_mov && val == 0 && EA_SIZE(attr) >= EA_4BYTE) - { - printf("MOV 0\n"); - } - */ - - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmdCns(attr, disp, val); - id->idIns(ins); - id->idInsFmt(fmt); - - id->idAddr()->iiaAddrMode.amBaseReg = REG_NA; - id->idAddr()->iiaAddrMode.amIndxReg = REG_NA; - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeMI(ins), val); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - void emitter::emitIns_R_AR(instruction ins, emitAttr attr, regNumber reg, regNumber base, int disp) { emitIns_R_ARX(ins, attr, reg, base, REG_NA, 1, disp); @@ -9543,92 +9404,6 @@ void emitter::emitIns_A_R_I(instruction ins, emitAttr attr, GenTreeIndir* indir, emitCurIGsize += size; } -void emitter::emitIns_AI_R(instruction ins, emitAttr attr, regNumber ireg, ssize_t disp) -{ - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmd(attr, disp); - insFormat fmt; - - if (ireg == REG_NA) - { - fmt = emitInsModeFormat(ins, IF_ARD); - } - else - { - fmt = emitInsModeFormat(ins, IF_ARD_RRD); - - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE)); - noway_assert(emitVerifyEncodable(ins, EA_SIZE(attr), ireg)); - - id->idReg1(ireg); - } - - id->idIns(ins); - id->idInsFmt(fmt); - - id->idAddr()->iiaAddrMode.amBaseReg = REG_NA; - id->idAddr()->iiaAddrMode.amIndxReg = REG_NA; - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeMR(ins)); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; - - emitAdjustStackDepthPushPop(ins); -} - -void emitter::emitIns_I_ARR(instruction ins, emitAttr attr, int val, regNumber reg, regNumber rg2, int disp) -{ - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE)); - -#ifdef TARGET_AMD64 - // mov reg, imm64 is the only opcode which takes a full 8 byte immediate - // all other opcodes take a sign-extended 4-byte immediate - noway_assert(EA_SIZE(attr) < EA_8BYTE || !EA_IS_CNS_RELOC(attr)); -#endif - - insFormat fmt; - - switch (ins) - { - case INS_rcl_N: - case INS_rcr_N: - case INS_rol_N: - case INS_ror_N: - case INS_shl_N: - case INS_shr_N: - case INS_sar_N: - assert(val != 1); - fmt = IF_ARW_SHF; - val &= 0x7F; - break; - - default: - fmt = emitInsModeFormat(ins, IF_ARD_CNS); - break; - } - - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmdCns(attr, disp, val); - id->idIns(ins); - id->idInsFmt(fmt); - - id->idAddr()->iiaAddrMode.amBaseReg = reg; - id->idAddr()->iiaAddrMode.amIndxReg = rg2; - id->idAddr()->iiaAddrMode.amScale = emitter::OPSZ1; - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeMI(ins), val); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - void emitter::emitIns_R_ARR(instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, int disp) { emitIns_R_ARX(ins, attr, reg, base, index, 1, disp); @@ -9639,57 +9414,6 @@ void emitter::emitIns_ARR_R(instruction ins, emitAttr attr, regNumber reg, regNu emitIns_ARX_R(ins, attr, reg, base, index, 1, disp); } -void emitter::emitIns_I_ARX( - instruction ins, emitAttr attr, int val, regNumber reg, regNumber rg2, unsigned mul, int disp) -{ - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE)); - -#ifdef TARGET_AMD64 - // mov reg, imm64 is the only opcode which takes a full 8 byte immediate - // all other opcodes take a sign-extended 4-byte immediate - noway_assert(EA_SIZE(attr) < EA_8BYTE || !EA_IS_CNS_RELOC(attr)); -#endif - - insFormat fmt; - - switch (ins) - { - case INS_rcl_N: - case INS_rcr_N: - case INS_rol_N: - case INS_ror_N: - case INS_shl_N: - case INS_shr_N: - case INS_sar_N: - assert(val != 1); - fmt = IF_ARW_SHF; - val &= 0x7F; - break; - - default: - fmt = emitInsModeFormat(ins, IF_ARD_CNS); - break; - } - - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmdCns(attr, disp, val); - - id->idIns(ins); - id->idInsFmt(fmt); - - id->idAddr()->iiaAddrMode.amBaseReg = reg; - id->idAddr()->iiaAddrMode.amIndxReg = rg2; - id->idAddr()->iiaAddrMode.amScale = emitEncodeScale(mul); - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeMI(ins), val); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - void emitter::emitIns_R_ARX( instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, unsigned scale, int disp) { @@ -9777,118 +9501,6 @@ void emitter::emitIns_ARX_R(instruction ins, emitAdjustStackDepthPushPop(ins); } -void emitter::emitIns_I_AX(instruction ins, emitAttr attr, int val, regNumber reg, unsigned mul, int disp) -{ - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE)); - -#ifdef TARGET_AMD64 - // mov reg, imm64 is the only opcode which takes a full 8 byte immediate - // all other opcodes take a sign-extended 4-byte immediate - noway_assert(EA_SIZE(attr) < EA_8BYTE || !EA_IS_CNS_RELOC(attr)); -#endif - - insFormat fmt; - - switch (ins) - { - case INS_rcl_N: - case INS_rcr_N: - case INS_rol_N: - case INS_ror_N: - case INS_shl_N: - case INS_shr_N: - case INS_sar_N: - assert(val != 1); - fmt = IF_ARW_SHF; - val &= 0x7F; - break; - - default: - fmt = emitInsModeFormat(ins, IF_ARD_CNS); - break; - } - - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmdCns(attr, disp, val); - id->idIns(ins); - id->idInsFmt(fmt); - - id->idAddr()->iiaAddrMode.amBaseReg = REG_NA; - id->idAddr()->iiaAddrMode.amIndxReg = reg; - id->idAddr()->iiaAddrMode.amScale = emitEncodeScale(mul); - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeMI(ins), val); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - -void emitter::emitIns_R_AX(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp) -{ - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE) && (ireg != REG_NA)); - noway_assert(emitVerifyEncodable(ins, EA_SIZE(attr), ireg)); - - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmd(attr, disp); - insFormat fmt = emitInsModeFormat(ins, IF_RRD_ARD); - - id->idIns(ins); - id->idInsFmt(fmt); - id->idReg1(ireg); - - id->idAddr()->iiaAddrMode.amBaseReg = REG_NA; - id->idAddr()->iiaAddrMode.amIndxReg = reg; - id->idAddr()->iiaAddrMode.amScale = emitEncodeScale(mul); - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeRM(ins)); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; -} - -void emitter::emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp) -{ - UNATIVE_OFFSET sz; - instrDesc* id = emitNewInstrAmd(attr, disp); - insFormat fmt; - - if (ireg == REG_NA) - { - fmt = emitInsModeFormat(ins, IF_ARD); - } - else - { - fmt = (ins == INS_xchg) ? IF_ARW_RRW : emitInsModeFormat(ins, IF_ARD_RRD); - noway_assert(emitVerifyEncodable(ins, EA_SIZE(attr), ireg)); - assert((CodeGen::instIsFP(ins) == false) && (EA_SIZE(attr) <= EA_8BYTE)); - - id->idReg1(ireg); - } - - id->idIns(ins); - id->idInsFmt(fmt); - - id->idAddr()->iiaAddrMode.amBaseReg = REG_NA; - id->idAddr()->iiaAddrMode.amIndxReg = reg; - id->idAddr()->iiaAddrMode.amScale = emitEncodeScale(mul); - - assert(emitGetInsAmdAny(id) == disp); // make sure "disp" is stored properly - - sz = emitInsSizeAM(id, insCodeMR(ins)); - id->idCodeSize(sz); - - dispIns(id); - emitCurIGsize += sz; - - emitAdjustStackDepthPushPop(ins); -} - //------------------------------------------------------------------------ // emitIns_SIMD_R_R_I: emits the code for an instruction that takes a register operand, an immediate operand // and that returns a value in register diff --git a/src/coreclr/jit/emitxarch.h b/src/coreclr/jit/emitxarch.h index f7e76209eb8239..038f6bd29177cf 100644 --- a/src/coreclr/jit/emitxarch.h +++ b/src/coreclr/jit/emitxarch.h @@ -99,7 +99,6 @@ unsigned emitGetEvexPrefixSize(instrDesc* id) const; unsigned emitGetPrefixSize(instrDesc* id, code_t code, bool includeRexPrefixSize); unsigned emitGetAdjustedSize(instrDesc* id, code_t code) const; -code_t emitExtractRex2Prefix(instruction ins, code_t& code) const; code_t emitExtractVexPrefix(instruction ins, code_t& code) const; code_t emitExtractEvexPrefix(instruction ins, code_t& code) const; @@ -118,7 +117,6 @@ unsigned insSSval(unsigned scale); static bool IsSSEInstruction(instruction ins); static bool IsSSEOrAVXInstruction(instruction ins); -static bool IsAVXOnlyInstruction(instruction ins); static bool IsAvx512OnlyInstruction(instruction ins); static bool IsKMOVInstruction(instruction ins); static bool IsAVXVNNIFamilyInstruction(instruction ins); @@ -149,7 +147,6 @@ bool DoJitUseApxNDD(instruction ins) const; code_t insEncodeMIreg(const instrDesc* id, regNumber reg, emitAttr size, code_t code); code_t AddRexWPrefix(const instrDesc* id, code_t code); -code_t AddRex2WPrefix(const instrDesc* id, code_t code); code_t AddRexRPrefix(const instrDesc* id, code_t code); code_t AddRexXPrefix(const instrDesc* id, code_t code); code_t AddRexBPrefix(const instrDesc* id, code_t code); @@ -210,25 +207,8 @@ bool hasVexPrefix(code_t code) return (code & VEX_PREFIX_MASK_3BYTE) == VEX_PREFIX_CODE_3BYTE; } code_t AddVexPrefix(instruction ins, code_t code, emitAttr attr); -code_t AddVexPrefixIfNeeded(instruction ins, code_t code, emitAttr size) -{ - if (TakesVexPrefix(ins)) - { - code = AddVexPrefix(ins, code, size); - } - return code; -} -code_t AddVexPrefixIfNeededAndNotPresent(instruction ins, code_t code, emitAttr size) -{ - if (TakesVexPrefix(ins) && !hasVexPrefix(code)) - { - code = AddVexPrefix(ins, code, size); - } - return code; -} static insTupleType insTupleTypeInfo(instruction ins); -static unsigned insKMaskBaseSize(instruction ins); // 2-byte REX2 prefix starts with byte 0xD5 #define REX2_PREFIX_MASK_2BYTE 0xFF0000000000ULL @@ -667,36 +647,6 @@ void SetEvexDFVIfNeeded(instrDesc* id, insOpts instOptions) #endif } -//------------------------------------------------------------------------ -// AddSimdPrefixIfNeeded: Add the correct SIMD prefix. -// Check if the prefix already exists befpre adding. -// -// Arguments: -// ins - the instruction being encoded. -// code - opcode + prefixes bits at some stage of encoding. -// size - operand size -// -// Returns: -// TRUE if code has an Evex prefix. -// TODO-XARCH-AVX512 come back and check whether we can id `id` directly (no need) -// to pass emitAttr size -code_t AddSimdPrefixIfNeededAndNotPresent(const instrDesc* id, code_t code, emitAttr size) -{ - if (TakesEvexPrefix(id)) - { - return !hasEvexPrefix(code) ? AddEvexPrefix(id, code, size) : code; - } - - instruction ins = id->idIns(); - - if (TakesVexPrefix(ins)) - { - return !hasVexPrefix(code) ? AddVexPrefix(ins, code, size) : code; - } - - return code; -} - bool TakesSimdPrefix(const instrDesc* id) const; //------------------------------------------------------------------------ @@ -1022,8 +972,6 @@ void emitIns_R_R_A_I(instruction ins, int ival, insFormat fmt, insOpts instOptions = INS_OPTS_NONE); -void emitIns_R_R_AR_I( - instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber base, int offs, int ival); void emitIns_C_R_I(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fldHnd, int offs, regNumber reg, int ival); void emitIns_S_R_I(instruction ins, emitAttr attr, int varNum, int offs, regNumber reg, int ival); @@ -1115,8 +1063,6 @@ void emitIns_C_I(instruction ins, int val, insOpts instOptions = INS_OPTS_NONE); -void emitIns_J_S(instruction ins, emitAttr attr, BasicBlock* dst, int varx, int offs); - void emitIns_R_L(instruction ins, emitAttr attr, BasicBlock* dst, regNumber reg); void emitIns_R_L(instruction ins, emitAttr attr, insGroup* dst, regNumber reg); @@ -1125,8 +1071,6 @@ void emitIns_R_D(instruction ins, emitAttr attr, unsigned offs, regNumber reg); void emitIns_I_AR( instruction ins, emitAttr attr, int val, regNumber reg, int offs, insOpts instOptions = INS_OPTS_NONE); -void emitIns_I_AI(instruction ins, emitAttr attr, int val, ssize_t disp); - void emitIns_R_AR(instruction ins, emitAttr attr, regNumber reg, regNumber base, int disp); void emitIns_R_AI(instruction ins, @@ -1141,16 +1085,10 @@ void emitIns_AR_R(instruction ins, cnsval_ssize_t disp, insOpts instOptions = INS_OPTS_NONE); -void emitIns_AI_R(instruction ins, emitAttr attr, regNumber ireg, ssize_t disp); - -void emitIns_I_ARR(instruction ins, emitAttr attr, int val, regNumber reg, regNumber rg2, int disp); - void emitIns_R_ARR(instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, int disp); void emitIns_ARR_R(instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, int disp); -void emitIns_I_ARX(instruction ins, emitAttr attr, int val, regNumber reg, regNumber rg2, unsigned mul, int disp); - void emitIns_R_ARX( instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, unsigned scale, int disp); @@ -1163,12 +1101,6 @@ void emitIns_ARX_R(instruction ins, cnsval_ssize_t disp, insOpts instOptions = INS_OPTS_NONE); -void emitIns_I_AX(instruction ins, emitAttr attr, int val, regNumber reg, unsigned mul, int disp); - -void emitIns_R_AX(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp); - -void emitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp); - void emitIns_SIMD_R_R_I( instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, int ival, insOpts instOptions);