From 6c4a8bd1ac0682aa722d66893dbe28557f4452b2 Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Thu, 28 Jan 2021 17:04:21 -0800 Subject: [PATCH 1/4] In AOT scenarios the VM reports to the JIT the minimal supported page size in src/coreclr/vm/jitinterface.cpp --- src/coreclr/vm/jitinterface.cpp | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/coreclr/vm/jitinterface.cpp b/src/coreclr/vm/jitinterface.cpp index 7f4fee170d3f22..661e9c9470706c 100644 --- a/src/coreclr/vm/jitinterface.cpp +++ b/src/coreclr/vm/jitinterface.cpp @@ -10227,7 +10227,16 @@ void CEEInfo::getEEInfo(CORINFO_EE_INFO *pEEInfoOut) _ASSERTE(sizeof(ReversePInvokeFrame) <= pEEInfoOut->sizeOfReversePInvokeFrame); #endif - pEEInfoOut->osPageSize = GetOsPageSize(); + if (!IsReadyToRunCompilation()) + { + pEEInfoOut->osPageSize = GetOsPageSize(); + } + else + { + // In AOT scenarios the VM reports to the JIT the minimal supported page size. + pEEInfoOut->osPageSize = 0x1000; + } + pEEInfoOut->maxUncheckedOffsetForNullObject = MAX_UNCHECKED_OFFSET_FOR_NULL_OBJECT; pEEInfoOut->targetAbi = CORINFO_CORECLR_ABI; From 0c55b92563b77213a10f88dd46d929ef071985d5 Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Wed, 3 Feb 2021 12:43:59 -0800 Subject: [PATCH 2/4] Have genStackPointerConstantAdjustment accept regTmp argument on Arm32 and Arm64 The temporary register is going to be used when sub sp,sp,#spDelta can not be encoded. For example, this happens when spDelta corresponds to OsPageSize and the OsPageSize is larger than 0x1000 bytes. The following code needs to be generated in such cases mov regTmp,#spDelta sub sp,sp,regTmp --- src/coreclr/jit/codegen.h | 5 ----- src/coreclr/jit/codegenarm.cpp | 2 +- src/coreclr/jit/codegenarm64.cpp | 8 +++++--- src/coreclr/jit/codegenarmarch.cpp | 11 ++++++++--- 4 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/coreclr/jit/codegen.h b/src/coreclr/jit/codegen.h index 9deffd0883a5e5..7f40326afd2e71 100644 --- a/src/coreclr/jit/codegen.h +++ b/src/coreclr/jit/codegen.h @@ -1301,12 +1301,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX void genReturn(GenTree* treeNode); -#ifdef TARGET_ARMARCH - void genStackPointerConstantAdjustment(ssize_t spDelta); -#else // !TARGET_ARMARCH void genStackPointerConstantAdjustment(ssize_t spDelta, regNumber regTmp); -#endif // !TARGET_ARMARCH - void genStackPointerConstantAdjustmentWithProbe(ssize_t spDelta, regNumber regTmp); target_ssize_t genStackPointerConstantAdjustmentLoopWithProbe(ssize_t spDelta, regNumber regTmp); diff --git a/src/coreclr/jit/codegenarm.cpp b/src/coreclr/jit/codegenarm.cpp index 6cc322a794a69d..4eae6d636ae8da 100644 --- a/src/coreclr/jit/codegenarm.cpp +++ b/src/coreclr/jit/codegenarm.cpp @@ -581,7 +581,7 @@ void CodeGen::genLclHeap(GenTree* tree) } else { - genStackPointerConstantAdjustment(-(ssize_t)stackAdjustment); + genStackPointerConstantAdjustment(-(ssize_t)stackAdjustment, regTmp); } // Return the stackalloc'ed address in result register. diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 7bff14693a486b..ed4be1c4ec6359 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2363,21 +2363,23 @@ void CodeGen::genLclHeap(GenTree* tree) assert((stackAdjustment % STACK_ALIGN) == 0); // This must be true for the stack to remain aligned assert((lastTouchDelta == ILLEGAL_LAST_TOUCH_DELTA) || (lastTouchDelta >= 0)); + const regNumber tmpReg = rsGetRsvdReg(); + if ((lastTouchDelta == ILLEGAL_LAST_TOUCH_DELTA) || (stackAdjustment + (unsigned)lastTouchDelta + STACK_PROBE_BOUNDARY_THRESHOLD_BYTES > compiler->eeGetPageSize())) { - genStackPointerConstantAdjustmentLoopWithProbe(-(ssize_t)stackAdjustment, REG_ZR); + genStackPointerConstantAdjustmentLoopWithProbe(-(ssize_t)stackAdjustment, tmpReg); } else { - genStackPointerConstantAdjustment(-(ssize_t)stackAdjustment); + genStackPointerConstantAdjustment(-(ssize_t)stackAdjustment, tmpReg); } // Return the stackalloc'ed address in result register. // TargetReg = SP + stackAdjustment. // - genInstrWithConstant(INS_add, EA_PTRSIZE, targetReg, REG_SPBASE, (ssize_t)stackAdjustment, rsGetRsvdReg()); + genInstrWithConstant(INS_add, EA_PTRSIZE, targetReg, REG_SPBASE, (ssize_t)stackAdjustment, tmpReg); } else // stackAdjustment == 0 { diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index b6530172251426..3108ad9cbd37eb 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -27,11 +27,12 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // // Arguments: // spDelta - the value to add to SP. Must be negative or zero. +// regTmp - an available temporary register. // // Return Value: // None. // -void CodeGen::genStackPointerConstantAdjustment(ssize_t spDelta) +void CodeGen::genStackPointerConstantAdjustment(ssize_t spDelta, regNumber regTmp) { assert(spDelta < 0); @@ -39,7 +40,11 @@ void CodeGen::genStackPointerConstantAdjustment(ssize_t spDelta) // function that does a probe, which will in turn call this function. assert((target_size_t)(-spDelta) <= compiler->eeGetPageSize()); - inst_RV_IV(INS_sub, REG_SPBASE, (target_ssize_t)-spDelta, EA_PTRSIZE); +#ifdef TARGET_ARM64 + genInstrWithConstant(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, -spDelta, regTmp); +#else + genInstrWithConstant(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, -spDelta, INS_FLAGS_DONT_CARE, regTmp); +#endif } //------------------------------------------------------------------------ @@ -58,7 +63,7 @@ void CodeGen::genStackPointerConstantAdjustment(ssize_t spDelta) void CodeGen::genStackPointerConstantAdjustmentWithProbe(ssize_t spDelta, regNumber regTmp) { GetEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, regTmp, REG_SP, 0); - genStackPointerConstantAdjustment(spDelta); + genStackPointerConstantAdjustment(spDelta, regTmp); } //------------------------------------------------------------------------ From d0fdc3e16beae72ad09d81d0098b25d3cf28b019 Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Thu, 4 Feb 2021 18:43:48 -0800 Subject: [PATCH 3/4] Use genInstrWithConstant(INS_sub) and rsGetRsvdReg() as temporary register to encode amount of sp adjustment in src/coreclr/jit/codegenarm64.cpp --- src/coreclr/jit/codegenarm64.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index ed4be1c4ec6359..0406fb2b70e4c1 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2234,7 +2234,7 @@ void CodeGen::genLclHeap(GenTree* tree) // ldr wz, [SP, #0] GetEmitter()->emitIns_R_R_I(INS_ldr, EA_4BYTE, REG_ZR, REG_SP, 0); - inst_RV_IV(INS_sub, REG_SP, amount, EA_PTRSIZE); + genInstrWithConstant(INS_sub, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, amount, rsGetRsvdReg()); lastTouchDelta = amount; From b661ac0123156456ecc8e034e5eea1177c156290 Mon Sep 17 00:00:00 2001 From: Egor Chesakov Date: Mon, 8 Feb 2021 13:41:13 -0800 Subject: [PATCH 4/4] Update comment to reflect that REG_NA can be passed for regTmp in genStackPointerConstantAdjustment in src/coreclr/jit/codegenarmarch.cpp --- src/coreclr/jit/codegenarmarch.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/codegenarmarch.cpp b/src/coreclr/jit/codegenarmarch.cpp index 3108ad9cbd37eb..ed7277ea31a852 100644 --- a/src/coreclr/jit/codegenarmarch.cpp +++ b/src/coreclr/jit/codegenarmarch.cpp @@ -27,7 +27,10 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // // Arguments: // spDelta - the value to add to SP. Must be negative or zero. -// regTmp - an available temporary register. +// regTmp - an available temporary register that is used if 'spDelta' cannot be encoded by +// 'sub sp, sp, #spDelta' instruction. +// Can be REG_NA if the caller knows for certain that 'spDelta' fits into the immediate +// value range. // // Return Value: // None.