From b3d8eec6c9232a6d4ab5a87a4aff6fbd2fb0f873 Mon Sep 17 00:00:00 2001 From: Adeel Mujahid <3840695+am11@users.noreply.github.com> Date: Wed, 15 Feb 2023 20:29:29 +0200 Subject: [PATCH 1/4] Fix clr build on illumos-x64 --- src/coreclr/nativeaot/Runtime/startup.cpp | 58 +++++++++++------------ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/src/coreclr/nativeaot/Runtime/startup.cpp b/src/coreclr/nativeaot/Runtime/startup.cpp index d1e240378e8024..ca4ed9e8be0c89 100644 --- a/src/coreclr/nativeaot/Runtime/startup.cpp +++ b/src/coreclr/nativeaot/Runtime/startup.cpp @@ -189,63 +189,63 @@ bool DetectCPUFeatures() int cpuidInfo[4]; - const int EAX = 0; - const int EBX = 1; - const int ECX = 2; - const int EDX = 3; + const int R_EAX = 0; + const int R_EBX = 1; + const int R_ECX = 2; + const int R_EDX = 3; __cpuid(cpuidInfo, 0x00000000); - uint32_t maxCpuId = static_cast(cpuidInfo[EAX]); + uint32_t maxCpuId = static_cast(cpuidInfo[R_EAX]); if (maxCpuId >= 1) { __cpuid(cpuidInfo, 0x00000001); - if (((cpuidInfo[EDX] & (1 << 25)) != 0) && ((cpuidInfo[EDX] & (1 << 26)) != 0)) // SSE & SSE2 + if (((cpuidInfo[R_EDX] & (1 << 25)) != 0) && ((cpuidInfo[R_EDX] & (1 << 26)) != 0)) // SSE & SSE2 { - if ((cpuidInfo[ECX] & (1 << 25)) != 0) // AESNI + if ((cpuidInfo[R_ECX] & (1 << 25)) != 0) // AESNI { g_cpuFeatures |= XArchIntrinsicConstants_Aes; } - if ((cpuidInfo[ECX] & (1 << 1)) != 0) // PCLMULQDQ + if ((cpuidInfo[R_ECX] & (1 << 1)) != 0) // PCLMULQDQ { g_cpuFeatures |= XArchIntrinsicConstants_Pclmulqdq; } - if ((cpuidInfo[ECX] & (1 << 0)) != 0) // SSE3 + if ((cpuidInfo[R_ECX] & (1 << 0)) != 0) // SSE3 { g_cpuFeatures |= XArchIntrinsicConstants_Sse3; - if ((cpuidInfo[ECX] & (1 << 9)) != 0) // SSSE3 + if ((cpuidInfo[R_ECX] & (1 << 9)) != 0) // SSSE3 { g_cpuFeatures |= XArchIntrinsicConstants_Ssse3; - if ((cpuidInfo[ECX] & (1 << 19)) != 0) // SSE4.1 + if ((cpuidInfo[R_ECX] & (1 << 19)) != 0) // SSE4.1 { g_cpuFeatures |= XArchIntrinsicConstants_Sse41; - if ((cpuidInfo[ECX] & (1 << 20)) != 0) // SSE4.2 + if ((cpuidInfo[R_ECX] & (1 << 20)) != 0) // SSE4.2 { g_cpuFeatures |= XArchIntrinsicConstants_Sse42; - if ((cpuidInfo[ECX] & (1 << 22)) != 0) // MOVBE + if ((cpuidInfo[R_ECX] & (1 << 22)) != 0) // MOVBE { g_cpuFeatures |= XArchIntrinsicConstants_Movbe; } - if ((cpuidInfo[ECX] & (1 << 23)) != 0) // POPCNT + if ((cpuidInfo[R_ECX] & (1 << 23)) != 0) // POPCNT { g_cpuFeatures |= XArchIntrinsicConstants_Popcnt; } - if (((cpuidInfo[ECX] & (1 << 27)) != 0) && ((cpuidInfo[ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX + if (((cpuidInfo[R_ECX] & (1 << 27)) != 0) && ((cpuidInfo[R_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX { if (PalIsAvxEnabled() && (xmmYmmStateSupport() == 1)) { g_cpuFeatures |= XArchIntrinsicConstants_Avx; - if ((cpuidInfo[ECX] & (1 << 12)) != 0) // FMA + if ((cpuidInfo[R_ECX] & (1 << 12)) != 0) // FMA { g_cpuFeatures |= XArchIntrinsicConstants_Fma; } @@ -254,30 +254,30 @@ bool DetectCPUFeatures() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[EBX] & (1 << 5)) != 0) // AVX2 + if ((cpuidInfo[R_EBX] & (1 << 5)) != 0) // AVX2 { g_cpuFeatures |= XArchIntrinsicConstants_Avx2; __cpuidex(cpuidInfo, 0x00000007, 0x00000001); - if ((cpuidInfo[EAX] & (1 << 4)) != 0) // AVX-VNNI + if ((cpuidInfo[R_EAX] & (1 << 4)) != 0) // AVX-VNNI { g_cpuFeatures |= XArchIntrinsicConstants_AvxVnni; } if (PalIsAvx512Enabled() && (avx512StateSupport() == 1)) // XGETBV XRC0[7:5] == 111 { - if ((cpuidInfo[EBX] & (1 << 16)) != 0) // AVX512F + if ((cpuidInfo[R_EBX] & (1 << 16)) != 0) // AVX512F { g_cpuFeatures |= XArchIntrinsicConstants_Avx512f; bool isAVX512_VLSupported = false; - if ((cpuidInfo[EBX] & (1 << 31)) != 0) // AVX512VL + if ((cpuidInfo[R_EBX] & (1 << 31)) != 0) // AVX512VL { g_cpuFeatures |= XArchIntrinsicConstants_Avx512f_vl; isAVX512_VLSupported = true; } - if ((cpuidInfo[EBX] & (1 << 30)) != 0) // AVX512BW + if ((cpuidInfo[R_EBX] & (1 << 30)) != 0) // AVX512BW { g_cpuFeatures |= XArchIntrinsicConstants_Avx512bw; if (isAVX512_VLSupported) @@ -286,7 +286,7 @@ bool DetectCPUFeatures() } } - if ((cpuidInfo[EBX] & (1 << 28)) != 0) // AVX512CD + if ((cpuidInfo[R_EBX] & (1 << 28)) != 0) // AVX512CD { g_cpuFeatures |= XArchIntrinsicConstants_Avx512cd; if (isAVX512_VLSupported) @@ -295,7 +295,7 @@ bool DetectCPUFeatures() } } - if ((cpuidInfo[EBX] & (1 << 17)) != 0) // AVX512DQ + if ((cpuidInfo[R_EBX] & (1 << 17)) != 0) // AVX512DQ { g_cpuFeatures |= XArchIntrinsicConstants_Avx512dq; if (isAVX512_VLSupported) @@ -319,12 +319,12 @@ bool DetectCPUFeatures() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[EBX] & (1 << 3)) != 0) // BMI1 + if ((cpuidInfo[R_EBX] & (1 << 3)) != 0) // BMI1 { g_cpuFeatures |= XArchIntrinsicConstants_Bmi1; } - if ((cpuidInfo[EBX] & (1 << 8)) != 0) // BMI2 + if ((cpuidInfo[R_EBX] & (1 << 8)) != 0) // BMI2 { g_cpuFeatures |= XArchIntrinsicConstants_Bmi2; } @@ -332,13 +332,13 @@ bool DetectCPUFeatures() } __cpuid(cpuidInfo, 0x80000000); - uint32_t maxCpuIdEx = static_cast(cpuidInfo[EAX]); + uint32_t maxCpuIdEx = static_cast(cpuidInfo[R_EAX]); if (maxCpuIdEx >= 0x80000001) { __cpuid(cpuidInfo, 0x80000001); - if ((cpuidInfo[ECX] & (1 << 5)) != 0) // LZCNT + if ((cpuidInfo[R_ECX] & (1 << 5)) != 0) // LZCNT { g_cpuFeatures |= XArchIntrinsicConstants_Lzcnt; } @@ -346,8 +346,8 @@ bool DetectCPUFeatures() #ifdef HOST_AMD64 // AMD has a "fast" mode for fxsave/fxrstor, which omits the saving of xmm registers. The OS will enable this mode // if it is supported. So if we continue to use fxsave/fxrstor, we must manually save/restore the xmm registers. - // fxsr_opt is bit 25 of EDX - if ((cpuidInfo[EDX] & (1 << 25)) != 0) + // fxsr_opt is bit 25 of R_EDX + if ((cpuidInfo[R_EDX] & (1 << 25)) != 0) g_fHasFastFxsave = true; #endif } From e3fd88bb43b042e01072beb88a1a79b1136a02aa Mon Sep 17 00:00:00 2001 From: Adeel <3840695+am11@users.noreply.github.com> Date: Thu, 16 Feb 2023 18:32:41 +0200 Subject: [PATCH 2/4] Keep in sync with codeman --- src/coreclr/vm/codeman.cpp | 56 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index c041c60dd8af7d..587b47492ac064 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1442,66 +1442,66 @@ void EEJitManager::SetCpuInfo() int cpuidInfo[4]; - const int EAX = CPUID_EAX; - const int EBX = CPUID_EBX; - const int ECX = CPUID_ECX; - const int EDX = CPUID_EDX; + const int R_EAX = CPUID_EAX; + const int R_EBX = CPUID_EBX; + const int R_ECX = CPUID_ECX; + const int R_EDX = CPUID_EDX; __cpuid(cpuidInfo, 0x00000000); - uint32_t maxCpuId = static_cast(cpuidInfo[EAX]); + uint32_t maxCpuId = static_cast(cpuidInfo[R_EAX]); if (maxCpuId >= 1) { __cpuid(cpuidInfo, 0x00000001); - if (((cpuidInfo[EDX] & (1 << 25)) != 0) && ((cpuidInfo[EDX] & (1 << 26)) != 0)) // SSE & SSE2 + if (((cpuidInfo[R_EDX] & (1 << 25)) != 0) && ((cpuidInfo[R_EDX] & (1 << 26)) != 0)) // SSE & SSE2 { CPUCompileFlags.Set(InstructionSet_SSE); CPUCompileFlags.Set(InstructionSet_SSE2); - if ((cpuidInfo[ECX] & (1 << 25)) != 0) // AESNI + if ((cpuidInfo[R_ECX] & (1 << 25)) != 0) // AESNI { CPUCompileFlags.Set(InstructionSet_AES); } - if ((cpuidInfo[ECX] & (1 << 1)) != 0) // PCLMULQDQ + if ((cpuidInfo[R_ECX] & (1 << 1)) != 0) // PCLMULQDQ { CPUCompileFlags.Set(InstructionSet_PCLMULQDQ); } - if ((cpuidInfo[ECX] & (1 << 0)) != 0) // SSE3 + if ((cpuidInfo[R_ECX] & (1 << 0)) != 0) // SSE3 { CPUCompileFlags.Set(InstructionSet_SSE3); - if ((cpuidInfo[ECX] & (1 << 9)) != 0) // SSSE3 + if ((cpuidInfo[R_ECX] & (1 << 9)) != 0) // SSSE3 { CPUCompileFlags.Set(InstructionSet_SSSE3); - if ((cpuidInfo[ECX] & (1 << 19)) != 0) // SSE4.1 + if ((cpuidInfo[R_ECX] & (1 << 19)) != 0) // SSE4.1 { CPUCompileFlags.Set(InstructionSet_SSE41); - if ((cpuidInfo[ECX] & (1 << 20)) != 0) // SSE4.2 + if ((cpuidInfo[R_ECX] & (1 << 20)) != 0) // SSE4.2 { CPUCompileFlags.Set(InstructionSet_SSE42); - if ((cpuidInfo[ECX] & (1 << 22)) != 0) // MOVBE + if ((cpuidInfo[R_ECX] & (1 << 22)) != 0) // MOVBE { CPUCompileFlags.Set(InstructionSet_MOVBE); } - if ((cpuidInfo[ECX] & (1 << 23)) != 0) // POPCNT + if ((cpuidInfo[R_ECX] & (1 << 23)) != 0) // POPCNT { CPUCompileFlags.Set(InstructionSet_POPCNT); } - if (((cpuidInfo[ECX] & (1 << 27)) != 0) && ((cpuidInfo[ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX + if (((cpuidInfo[R_ECX] & (1 << 27)) != 0) && ((cpuidInfo[R_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX { if(DoesOSSupportAVX() && (xmmYmmStateSupport() == 1)) // XGETBV == 11 { CPUCompileFlags.Set(InstructionSet_AVX); - if ((cpuidInfo[ECX] & (1 << 12)) != 0) // FMA + if ((cpuidInfo[R_ECX] & (1 << 12)) != 0) // FMA { CPUCompileFlags.Set(InstructionSet_FMA); } @@ -1510,24 +1510,24 @@ void EEJitManager::SetCpuInfo() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[EBX] & (1 << 5)) != 0) // AVX2 + if ((cpuidInfo[R_EBX] & (1 << 5)) != 0) // AVX2 { CPUCompileFlags.Set(InstructionSet_AVX2); if (DoesOSSupportAVX512() && (avx512StateSupport() == 1)) // XGETBV XRC0[7:5] == 111 { - if ((cpuidInfo[EBX] & (1 << 16)) != 0) // AVX512F + if ((cpuidInfo[R_EBX] & (1 << 16)) != 0) // AVX512F { CPUCompileFlags.Set(InstructionSet_AVX512F); bool isAVX512_VLSupported = false; - if ((cpuidInfo[EBX] & (1 << 31)) != 0) // AVX512VL + if ((cpuidInfo[R_EBX] & (1 << 31)) != 0) // AVX512VL { CPUCompileFlags.Set(InstructionSet_AVX512F_VL); isAVX512_VLSupported = true; } - if ((cpuidInfo[EBX] & (1 << 30)) != 0) // AVX512BW + if ((cpuidInfo[R_EBX] & (1 << 30)) != 0) // AVX512BW { CPUCompileFlags.Set(InstructionSet_AVX512BW); if (isAVX512_VLSupported) // AVX512BW_VL @@ -1536,7 +1536,7 @@ void EEJitManager::SetCpuInfo() } } - if ((cpuidInfo[EBX] & (1 << 28)) != 0) // AVX512CD + if ((cpuidInfo[R_EBX] & (1 << 28)) != 0) // AVX512CD { CPUCompileFlags.Set(InstructionSet_AVX512CD); if (isAVX512_VLSupported) // AVX512CD_VL @@ -1545,7 +1545,7 @@ void EEJitManager::SetCpuInfo() } } - if ((cpuidInfo[EBX] & (1 << 17)) != 0) // AVX512DQ + if ((cpuidInfo[R_EBX] & (1 << 17)) != 0) // AVX512DQ { CPUCompileFlags.Set(InstructionSet_AVX512DQ); if (isAVX512_VLSupported) // AVX512DQ_VL @@ -1557,7 +1557,7 @@ void EEJitManager::SetCpuInfo() } __cpuidex(cpuidInfo, 0x00000007, 0x00000001); - if ((cpuidInfo[EAX] & (1 << 4)) != 0) // AVX-VNNI + if ((cpuidInfo[R_EAX] & (1 << 4)) != 0) // AVX-VNNI { CPUCompileFlags.Set(InstructionSet_AVXVNNI); } @@ -1580,17 +1580,17 @@ void EEJitManager::SetCpuInfo() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[EBX] & (1 << 3)) != 0) // BMI1 + if ((cpuidInfo[R_EBX] & (1 << 3)) != 0) // BMI1 { CPUCompileFlags.Set(InstructionSet_BMI1); } - if ((cpuidInfo[EBX] & (1 << 8)) != 0) // BMI2 + if ((cpuidInfo[R_EBX] & (1 << 8)) != 0) // BMI2 { CPUCompileFlags.Set(InstructionSet_BMI2); } - if ((cpuidInfo[EDX] & (1 << 14)) != 0) + if ((cpuidInfo[R_EDX] & (1 << 14)) != 0) { CPUCompileFlags.Set(InstructionSet_X86Serialize); // SERIALIZE } @@ -1598,13 +1598,13 @@ void EEJitManager::SetCpuInfo() } __cpuid(cpuidInfo, 0x80000000); - uint32_t maxCpuIdEx = static_cast(cpuidInfo[EAX]); + uint32_t maxCpuIdEx = static_cast(cpuidInfo[R_EAX]); if (maxCpuIdEx >= 0x80000001) { __cpuid(cpuidInfo, 0x80000001); - if ((cpuidInfo[ECX] & (1 << 5)) != 0) // LZCNT + if ((cpuidInfo[R_ECX] & (1 << 5)) != 0) // LZCNT { CPUCompileFlags.Set(InstructionSet_LZCNT); } From 4bbc3f788534d5bf35a020cf7a5fc01372197a60 Mon Sep 17 00:00:00 2001 From: Adeel <3840695+am11@users.noreply.github.com> Date: Thu, 16 Feb 2023 19:06:12 +0200 Subject: [PATCH 3/4] Use CPUID_XXX --- src/coreclr/nativeaot/Runtime/startup.cpp | 58 +++++++++++------------ src/coreclr/vm/cgensys.h | 5 -- src/coreclr/vm/codeman.cpp | 56 +++++++++++----------- 3 files changed, 57 insertions(+), 62 deletions(-) diff --git a/src/coreclr/nativeaot/Runtime/startup.cpp b/src/coreclr/nativeaot/Runtime/startup.cpp index ca4ed9e8be0c89..773991eb93548f 100644 --- a/src/coreclr/nativeaot/Runtime/startup.cpp +++ b/src/coreclr/nativeaot/Runtime/startup.cpp @@ -189,63 +189,63 @@ bool DetectCPUFeatures() int cpuidInfo[4]; - const int R_EAX = 0; - const int R_EBX = 1; - const int R_ECX = 2; - const int R_EDX = 3; + const int CPUID_EAX = 0; + const int CPUID_EBX = 1; + const int CPUID_ECX = 2; + const int CPUID_EDX = 3; __cpuid(cpuidInfo, 0x00000000); - uint32_t maxCpuId = static_cast(cpuidInfo[R_EAX]); + uint32_t maxCpuId = static_cast(cpuidInfo[CPUID_EAX]); if (maxCpuId >= 1) { __cpuid(cpuidInfo, 0x00000001); - if (((cpuidInfo[R_EDX] & (1 << 25)) != 0) && ((cpuidInfo[R_EDX] & (1 << 26)) != 0)) // SSE & SSE2 + if (((cpuidInfo[CPUID_EDX] & (1 << 25)) != 0) && ((cpuidInfo[CPUID_EDX] & (1 << 26)) != 0)) // SSE & SSE2 { - if ((cpuidInfo[R_ECX] & (1 << 25)) != 0) // AESNI + if ((cpuidInfo[CPUID_ECX] & (1 << 25)) != 0) // AESNI { g_cpuFeatures |= XArchIntrinsicConstants_Aes; } - if ((cpuidInfo[R_ECX] & (1 << 1)) != 0) // PCLMULQDQ + if ((cpuidInfo[CPUID_ECX] & (1 << 1)) != 0) // PCLMULQDQ { g_cpuFeatures |= XArchIntrinsicConstants_Pclmulqdq; } - if ((cpuidInfo[R_ECX] & (1 << 0)) != 0) // SSE3 + if ((cpuidInfo[CPUID_ECX] & (1 << 0)) != 0) // SSE3 { g_cpuFeatures |= XArchIntrinsicConstants_Sse3; - if ((cpuidInfo[R_ECX] & (1 << 9)) != 0) // SSSE3 + if ((cpuidInfo[CPUID_ECX] & (1 << 9)) != 0) // SSSE3 { g_cpuFeatures |= XArchIntrinsicConstants_Ssse3; - if ((cpuidInfo[R_ECX] & (1 << 19)) != 0) // SSE4.1 + if ((cpuidInfo[CPUID_ECX] & (1 << 19)) != 0) // SSE4.1 { g_cpuFeatures |= XArchIntrinsicConstants_Sse41; - if ((cpuidInfo[R_ECX] & (1 << 20)) != 0) // SSE4.2 + if ((cpuidInfo[CPUID_ECX] & (1 << 20)) != 0) // SSE4.2 { g_cpuFeatures |= XArchIntrinsicConstants_Sse42; - if ((cpuidInfo[R_ECX] & (1 << 22)) != 0) // MOVBE + if ((cpuidInfo[CPUID_ECX] & (1 << 22)) != 0) // MOVBE { g_cpuFeatures |= XArchIntrinsicConstants_Movbe; } - if ((cpuidInfo[R_ECX] & (1 << 23)) != 0) // POPCNT + if ((cpuidInfo[CPUID_ECX] & (1 << 23)) != 0) // POPCNT { g_cpuFeatures |= XArchIntrinsicConstants_Popcnt; } - if (((cpuidInfo[R_ECX] & (1 << 27)) != 0) && ((cpuidInfo[R_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX + if (((cpuidInfo[CPUID_ECX] & (1 << 27)) != 0) && ((cpuidInfo[CPUID_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX { if (PalIsAvxEnabled() && (xmmYmmStateSupport() == 1)) { g_cpuFeatures |= XArchIntrinsicConstants_Avx; - if ((cpuidInfo[R_ECX] & (1 << 12)) != 0) // FMA + if ((cpuidInfo[CPUID_ECX] & (1 << 12)) != 0) // FMA { g_cpuFeatures |= XArchIntrinsicConstants_Fma; } @@ -254,30 +254,30 @@ bool DetectCPUFeatures() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[R_EBX] & (1 << 5)) != 0) // AVX2 + if ((cpuidInfo[CPUID_EBX] & (1 << 5)) != 0) // AVX2 { g_cpuFeatures |= XArchIntrinsicConstants_Avx2; __cpuidex(cpuidInfo, 0x00000007, 0x00000001); - if ((cpuidInfo[R_EAX] & (1 << 4)) != 0) // AVX-VNNI + if ((cpuidInfo[CPUID_EAX] & (1 << 4)) != 0) // AVX-VNNI { g_cpuFeatures |= XArchIntrinsicConstants_AvxVnni; } if (PalIsAvx512Enabled() && (avx512StateSupport() == 1)) // XGETBV XRC0[7:5] == 111 { - if ((cpuidInfo[R_EBX] & (1 << 16)) != 0) // AVX512F + if ((cpuidInfo[CPUID_EBX] & (1 << 16)) != 0) // AVX512F { g_cpuFeatures |= XArchIntrinsicConstants_Avx512f; bool isAVX512_VLSupported = false; - if ((cpuidInfo[R_EBX] & (1 << 31)) != 0) // AVX512VL + if ((cpuidInfo[CPUID_EBX] & (1 << 31)) != 0) // AVX512VL { g_cpuFeatures |= XArchIntrinsicConstants_Avx512f_vl; isAVX512_VLSupported = true; } - if ((cpuidInfo[R_EBX] & (1 << 30)) != 0) // AVX512BW + if ((cpuidInfo[CPUID_EBX] & (1 << 30)) != 0) // AVX512BW { g_cpuFeatures |= XArchIntrinsicConstants_Avx512bw; if (isAVX512_VLSupported) @@ -286,7 +286,7 @@ bool DetectCPUFeatures() } } - if ((cpuidInfo[R_EBX] & (1 << 28)) != 0) // AVX512CD + if ((cpuidInfo[CPUID_EBX] & (1 << 28)) != 0) // AVX512CD { g_cpuFeatures |= XArchIntrinsicConstants_Avx512cd; if (isAVX512_VLSupported) @@ -295,7 +295,7 @@ bool DetectCPUFeatures() } } - if ((cpuidInfo[R_EBX] & (1 << 17)) != 0) // AVX512DQ + if ((cpuidInfo[CPUID_EBX] & (1 << 17)) != 0) // AVX512DQ { g_cpuFeatures |= XArchIntrinsicConstants_Avx512dq; if (isAVX512_VLSupported) @@ -319,12 +319,12 @@ bool DetectCPUFeatures() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[R_EBX] & (1 << 3)) != 0) // BMI1 + if ((cpuidInfo[CPUID_EBX] & (1 << 3)) != 0) // BMI1 { g_cpuFeatures |= XArchIntrinsicConstants_Bmi1; } - if ((cpuidInfo[R_EBX] & (1 << 8)) != 0) // BMI2 + if ((cpuidInfo[CPUID_EBX] & (1 << 8)) != 0) // BMI2 { g_cpuFeatures |= XArchIntrinsicConstants_Bmi2; } @@ -332,13 +332,13 @@ bool DetectCPUFeatures() } __cpuid(cpuidInfo, 0x80000000); - uint32_t maxCpuIdEx = static_cast(cpuidInfo[R_EAX]); + uint32_t maxCpuIdEx = static_cast(cpuidInfo[CPUID_EAX]); if (maxCpuIdEx >= 0x80000001) { __cpuid(cpuidInfo, 0x80000001); - if ((cpuidInfo[R_ECX] & (1 << 5)) != 0) // LZCNT + if ((cpuidInfo[CPUID_ECX] & (1 << 5)) != 0) // LZCNT { g_cpuFeatures |= XArchIntrinsicConstants_Lzcnt; } @@ -346,8 +346,8 @@ bool DetectCPUFeatures() #ifdef HOST_AMD64 // AMD has a "fast" mode for fxsave/fxrstor, which omits the saving of xmm registers. The OS will enable this mode // if it is supported. So if we continue to use fxsave/fxrstor, we must manually save/restore the xmm registers. - // fxsr_opt is bit 25 of R_EDX - if ((cpuidInfo[R_EDX] & (1 << 25)) != 0) + // fxsr_opt is bit 25 of CPUID_EDX + if ((cpuidInfo[CPUID_EDX] & (1 << 25)) != 0) g_fHasFastFxsave = true; #endif } diff --git a/src/coreclr/vm/cgensys.h b/src/coreclr/vm/cgensys.h index 5e378c485332d5..9512568dd816b7 100644 --- a/src/coreclr/vm/cgensys.h +++ b/src/coreclr/vm/cgensys.h @@ -104,11 +104,6 @@ extern "C" DWORD __stdcall xmmYmmStateSupport(); extern "C" DWORD __stdcall avx512StateSupport(); #endif -const int CPUID_EAX = 0; -const int CPUID_EBX = 1; -const int CPUID_ECX = 2; -const int CPUID_EDX = 3; - inline bool TargetHasAVXSupport() { #if (defined(TARGET_X86) || defined(TARGET_AMD64)) diff --git a/src/coreclr/vm/codeman.cpp b/src/coreclr/vm/codeman.cpp index 587b47492ac064..471bd1628d32a3 100644 --- a/src/coreclr/vm/codeman.cpp +++ b/src/coreclr/vm/codeman.cpp @@ -1442,66 +1442,66 @@ void EEJitManager::SetCpuInfo() int cpuidInfo[4]; - const int R_EAX = CPUID_EAX; - const int R_EBX = CPUID_EBX; - const int R_ECX = CPUID_ECX; - const int R_EDX = CPUID_EDX; + const int CPUID_EAX = 0; + const int CPUID_EBX = 1; + const int CPUID_ECX = 2; + const int CPUID_EDX = 3; __cpuid(cpuidInfo, 0x00000000); - uint32_t maxCpuId = static_cast(cpuidInfo[R_EAX]); + uint32_t maxCpuId = static_cast(cpuidInfo[CPUID_EAX]); if (maxCpuId >= 1) { __cpuid(cpuidInfo, 0x00000001); - if (((cpuidInfo[R_EDX] & (1 << 25)) != 0) && ((cpuidInfo[R_EDX] & (1 << 26)) != 0)) // SSE & SSE2 + if (((cpuidInfo[CPUID_EDX] & (1 << 25)) != 0) && ((cpuidInfo[CPUID_EDX] & (1 << 26)) != 0)) // SSE & SSE2 { CPUCompileFlags.Set(InstructionSet_SSE); CPUCompileFlags.Set(InstructionSet_SSE2); - if ((cpuidInfo[R_ECX] & (1 << 25)) != 0) // AESNI + if ((cpuidInfo[CPUID_ECX] & (1 << 25)) != 0) // AESNI { CPUCompileFlags.Set(InstructionSet_AES); } - if ((cpuidInfo[R_ECX] & (1 << 1)) != 0) // PCLMULQDQ + if ((cpuidInfo[CPUID_ECX] & (1 << 1)) != 0) // PCLMULQDQ { CPUCompileFlags.Set(InstructionSet_PCLMULQDQ); } - if ((cpuidInfo[R_ECX] & (1 << 0)) != 0) // SSE3 + if ((cpuidInfo[CPUID_ECX] & (1 << 0)) != 0) // SSE3 { CPUCompileFlags.Set(InstructionSet_SSE3); - if ((cpuidInfo[R_ECX] & (1 << 9)) != 0) // SSSE3 + if ((cpuidInfo[CPUID_ECX] & (1 << 9)) != 0) // SSSE3 { CPUCompileFlags.Set(InstructionSet_SSSE3); - if ((cpuidInfo[R_ECX] & (1 << 19)) != 0) // SSE4.1 + if ((cpuidInfo[CPUID_ECX] & (1 << 19)) != 0) // SSE4.1 { CPUCompileFlags.Set(InstructionSet_SSE41); - if ((cpuidInfo[R_ECX] & (1 << 20)) != 0) // SSE4.2 + if ((cpuidInfo[CPUID_ECX] & (1 << 20)) != 0) // SSE4.2 { CPUCompileFlags.Set(InstructionSet_SSE42); - if ((cpuidInfo[R_ECX] & (1 << 22)) != 0) // MOVBE + if ((cpuidInfo[CPUID_ECX] & (1 << 22)) != 0) // MOVBE { CPUCompileFlags.Set(InstructionSet_MOVBE); } - if ((cpuidInfo[R_ECX] & (1 << 23)) != 0) // POPCNT + if ((cpuidInfo[CPUID_ECX] & (1 << 23)) != 0) // POPCNT { CPUCompileFlags.Set(InstructionSet_POPCNT); } - if (((cpuidInfo[R_ECX] & (1 << 27)) != 0) && ((cpuidInfo[R_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX + if (((cpuidInfo[CPUID_ECX] & (1 << 27)) != 0) && ((cpuidInfo[CPUID_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX { if(DoesOSSupportAVX() && (xmmYmmStateSupport() == 1)) // XGETBV == 11 { CPUCompileFlags.Set(InstructionSet_AVX); - if ((cpuidInfo[R_ECX] & (1 << 12)) != 0) // FMA + if ((cpuidInfo[CPUID_ECX] & (1 << 12)) != 0) // FMA { CPUCompileFlags.Set(InstructionSet_FMA); } @@ -1510,24 +1510,24 @@ void EEJitManager::SetCpuInfo() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[R_EBX] & (1 << 5)) != 0) // AVX2 + if ((cpuidInfo[CPUID_EBX] & (1 << 5)) != 0) // AVX2 { CPUCompileFlags.Set(InstructionSet_AVX2); if (DoesOSSupportAVX512() && (avx512StateSupport() == 1)) // XGETBV XRC0[7:5] == 111 { - if ((cpuidInfo[R_EBX] & (1 << 16)) != 0) // AVX512F + if ((cpuidInfo[CPUID_EBX] & (1 << 16)) != 0) // AVX512F { CPUCompileFlags.Set(InstructionSet_AVX512F); bool isAVX512_VLSupported = false; - if ((cpuidInfo[R_EBX] & (1 << 31)) != 0) // AVX512VL + if ((cpuidInfo[CPUID_EBX] & (1 << 31)) != 0) // AVX512VL { CPUCompileFlags.Set(InstructionSet_AVX512F_VL); isAVX512_VLSupported = true; } - if ((cpuidInfo[R_EBX] & (1 << 30)) != 0) // AVX512BW + if ((cpuidInfo[CPUID_EBX] & (1 << 30)) != 0) // AVX512BW { CPUCompileFlags.Set(InstructionSet_AVX512BW); if (isAVX512_VLSupported) // AVX512BW_VL @@ -1536,7 +1536,7 @@ void EEJitManager::SetCpuInfo() } } - if ((cpuidInfo[R_EBX] & (1 << 28)) != 0) // AVX512CD + if ((cpuidInfo[CPUID_EBX] & (1 << 28)) != 0) // AVX512CD { CPUCompileFlags.Set(InstructionSet_AVX512CD); if (isAVX512_VLSupported) // AVX512CD_VL @@ -1545,7 +1545,7 @@ void EEJitManager::SetCpuInfo() } } - if ((cpuidInfo[R_EBX] & (1 << 17)) != 0) // AVX512DQ + if ((cpuidInfo[CPUID_EBX] & (1 << 17)) != 0) // AVX512DQ { CPUCompileFlags.Set(InstructionSet_AVX512DQ); if (isAVX512_VLSupported) // AVX512DQ_VL @@ -1557,7 +1557,7 @@ void EEJitManager::SetCpuInfo() } __cpuidex(cpuidInfo, 0x00000007, 0x00000001); - if ((cpuidInfo[R_EAX] & (1 << 4)) != 0) // AVX-VNNI + if ((cpuidInfo[CPUID_EAX] & (1 << 4)) != 0) // AVX-VNNI { CPUCompileFlags.Set(InstructionSet_AVXVNNI); } @@ -1580,17 +1580,17 @@ void EEJitManager::SetCpuInfo() { __cpuidex(cpuidInfo, 0x00000007, 0x00000000); - if ((cpuidInfo[R_EBX] & (1 << 3)) != 0) // BMI1 + if ((cpuidInfo[CPUID_EBX] & (1 << 3)) != 0) // BMI1 { CPUCompileFlags.Set(InstructionSet_BMI1); } - if ((cpuidInfo[R_EBX] & (1 << 8)) != 0) // BMI2 + if ((cpuidInfo[CPUID_EBX] & (1 << 8)) != 0) // BMI2 { CPUCompileFlags.Set(InstructionSet_BMI2); } - if ((cpuidInfo[R_EDX] & (1 << 14)) != 0) + if ((cpuidInfo[CPUID_EDX] & (1 << 14)) != 0) { CPUCompileFlags.Set(InstructionSet_X86Serialize); // SERIALIZE } @@ -1598,13 +1598,13 @@ void EEJitManager::SetCpuInfo() } __cpuid(cpuidInfo, 0x80000000); - uint32_t maxCpuIdEx = static_cast(cpuidInfo[R_EAX]); + uint32_t maxCpuIdEx = static_cast(cpuidInfo[CPUID_EAX]); if (maxCpuIdEx >= 0x80000001) { __cpuid(cpuidInfo, 0x80000001); - if ((cpuidInfo[R_ECX] & (1 << 5)) != 0) // LZCNT + if ((cpuidInfo[CPUID_ECX] & (1 << 5)) != 0) // LZCNT { CPUCompileFlags.Set(InstructionSet_LZCNT); } From 8be8f504f727e114b18d119d18bc9aa401bfe6e7 Mon Sep 17 00:00:00 2001 From: Adeel <3840695+am11@users.noreply.github.com> Date: Thu, 16 Feb 2023 19:39:49 +0200 Subject: [PATCH 4/4] . --- src/coreclr/vm/cgensys.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/coreclr/vm/cgensys.h b/src/coreclr/vm/cgensys.h index 9512568dd816b7..760827ccfb8b4e 100644 --- a/src/coreclr/vm/cgensys.h +++ b/src/coreclr/vm/cgensys.h @@ -109,6 +109,7 @@ inline bool TargetHasAVXSupport() #if (defined(TARGET_X86) || defined(TARGET_AMD64)) int cpuInfo[4]; __cpuid(cpuInfo, 0x00000001); // All x86/AMD64 targets support cpuid. + const int CPUID_ECX = 2; return ((cpuInfo[CPUID_ECX] & (1 << 28)) != 0); // The AVX feature is ECX bit 28. #endif // (defined(TARGET_X86) || defined(TARGET_AMD64)) return false;