From d04beb3d87bd51d45025f637e48b4a47edfd4659 Mon Sep 17 00:00:00 2001 From: EgorBo Date: Mon, 24 Apr 2023 18:28:32 +0200 Subject: [PATCH 1/2] Optimize >>> to ShiftRightLogical on arm64 --- src/coreclr/jit/hwintrinsicarm64.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index c6c175b0f5ce12..8e484df6bf6398 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -1531,6 +1531,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, case NI_Vector64_ShiftRightArithmetic: case NI_Vector128_ShiftRightArithmetic: + case NI_Vector64_op_RightShift: + case NI_Vector128_op_RightShift: { assert(sig->numArgs == 2); genTreeOps op = varTypeIsUnsigned(simdBaseType) ? GT_RSZ : GT_RSH; @@ -1544,6 +1546,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, case NI_Vector64_ShiftRightLogical: case NI_Vector128_ShiftRightLogical: + case NI_Vector64_op_UnsignedRightShift: + case NI_Vector128_op_UnsignedRightShift: { assert(sig->numArgs == 2); From d6a0beab0856865bf3a545def64b94a17b25b89e Mon Sep 17 00:00:00 2001 From: EgorBo Date: Mon, 24 Apr 2023 18:46:08 +0200 Subject: [PATCH 2/2] Add LeftShift --- src/coreclr/jit/hwintrinsicarm64.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 8e484df6bf6398..66ad884abe3bcf 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -1519,6 +1519,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, case NI_Vector64_ShiftLeft: case NI_Vector128_ShiftLeft: + case NI_Vector64_op_LeftShift: + case NI_Vector128_op_LeftShift: { assert(sig->numArgs == 2);