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.TH "X86-BLSR" "7" "May 2019" "TTMO" "Intel x86-64 ISA Manual"
.SH NAME
BLSR - RESET LOWEST SET BIT
.TS
allbox;
l l l l l
l l l l l .
\fBOpcode/Instruction\fP	\fBOp/En\fP	\fB64/32-bit Mode\fP	\fBCPUID Feature Flag\fP	\fBDescription\fP
T{
VEX.LZ.0F38.W0 F3 /1 BLSR r32, r/m32
T}	VM	V/V	BMI1	T{
Reset lowest set bit of r/m32, keep all other bits of r/m32 and write result to r32.
T}
T{
VEX.LZ.0F38.W1 F3 /1 BLSR r64, r/m64
T}	VM	V/N.E.	BMI1	T{
Reset lowest set bit of r/m64, keep all other bits of r/m64 and write result to r64.
T}
.TE

.SH INSTRUCTION OPERAND ENCODING
.TS
allbox;
l l l l l
l l l l l .
\fBOp/En\fP	\fBOperand 1\fP	\fBOperand 2\fP	\fBOperand 3\fP	\fBOperand 4\fP
VM	VEX.vvvv (w)	ModRM:r/m (r)	N/A	N/A
.TE

.SH DESCRIPTION
Copies all bits from the source operand to the destination operand and
resets (=0) the bit position in the destination operand that corresponds
to the lowest set bit of the source operand. If the source operand is
zero BLSR sets CF.

.PP
This instruction is not supported in real mode and virtual-8086 mode.
The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode
operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes.
An attempt to execute this instruction with VEX.L not equal to 0 will
cause #UD.

.SH OPERATION
.EX
temp := (SRC-1) bitwiseAND ( SRC );
SF := temp[OperandSize -1];
ZF := (temp = 0);
IF SRC = 0
    CF := 1;
ELSE
    CF := 0;
FI
DEST := temp;
.EE

.SH FLAGS AFFECTED
ZF and SF flags are updated based on the result. CF is set if the source
is zero. OF flag is cleared. AF and PF flags are undefined.

.SH INTEL C/C++ COMPILER INTRINSIC EQUIVALENT
.EX
BLSR unsigned __int32 _blsr_u32(unsigned __int32 src);

BLSR unsigned __int64 _blsr_u64(unsigned __int64 src);
.EE

.SH SIMD FLOATING-POINT EXCEPTIONS
None.

.SH OTHER EXCEPTIONS
See Table 2-29, “Type 13 Class
Exception Conditions.”

.SH SEE ALSO
x86-manpages(7) for a list of other x86-64 man pages.

.SH COLOPHON
This UNOFFICIAL, mechanically-separated, non-verified reference is
provided for convenience, but it may be
incomplete or
broken in various obvious or non-obvious ways.
Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual
for anything serious.

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