cvtdq2pd.x86

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.TH "X86-CVTDQ2PD" "7" "May 2019" "TTMO" "Intel x86-64 ISA Manual"
.SH NAME
CVTDQ2PD - CONVERT PACKED DOUBLEWORD INTEGERS TO PACKED DOUBLE PRECISION FLOATING-POINTVALUES
.TS
allbox;
l l l l l 
l l l l l .
\fBOpcode/Instruction\fP	\fBOp / En\fP	\fB64/32 bit Mode Support\fP	\fBCPUID Feature Flag\fP	\fBDescription\fP
T{
F3 0F E6 /r CVTDQ2PD xmm1, xmm2/m64
T}	A	V/V	SSE2	T{
Convert two packed signed doubleword integers from xmm2/mem to two packed double precision floating-point values in xmm1.
T}
T{
VEX.128.F3.0F.WIG E6 /r VCVTDQ2PD xmm1, xmm2/m64
T}	A	V/V	AVX	T{
Convert two packed signed doubleword integers from xmm2/mem to two packed double precision floating-point values in xmm1.
T}
T{
VEX.256.F3.0F.WIG E6 /r VCVTDQ2PD ymm1, xmm2/m128
T}	A	V/V	AVX	T{
Convert four packed signed doubleword integers from xmm2/mem to four packed double precision floating-point values in ymm1.
T}
T{
EVEX.128.F3.0F.W0 E6 /r VCVTDQ2PD xmm1 {k1}{z}, xmm2/m64/m32bcst
T}	B	V/V	AVX512VL AVX512F	T{
Convert 2 packed signed doubleword integers from xmm2/m64/m32bcst to eight packed double precision floating-point values in xmm1 with writemask k1.
T}
T{
EVEX.256.F3.0F.W0 E6 /r VCVTDQ2PD ymm1 {k1}{z}, xmm2/m128/m32bcst
T}	B	V/V	AVX512VL AVX512F	T{
Convert 4 packed signed doubleword integers from xmm2/m128/m32bcst to 4 packed double precision floating-point values in ymm1 with writemask k1.
T}
T{
EVEX.512.F3.0F.W0 E6 /r VCVTDQ2PD zmm1 {k1}{z}, ymm2/m256/m32bcst
T}	B	V/V	AVX512F	T{
Convert eight packed signed doubleword integers from ymm2/m256/m32bcst to eight packed double precision floating-point values in zmm1 with writemask k1.
T}
.TE

.SH INSTRUCTION OPERAND ENCODING
.TS
allbox;
l l l l l l 
l l l l l l .
\fBOp/En\fP	\fBTuple Type\fP	\fBOperand 1\fP	\fBOperand 2\fP	\fBOperand 3\fP	\fBOperand 4\fP
A	N/A	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A
B	Half	ModRM:reg (w)	ModRM:r/m (r)	N/A	N/A
.TE

.SH DESCRIPTION
Converts two, four or eight packed signed doubleword integers in the
source operand (the second operand) to two, four or eight packed double
precision floating-point values in the destination operand (the first
operand).

.PP
EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64
bits) register, a 256/128/64-bit memory location or a 256/128/64-bit
vector broadcasted from a 32-bit memory location. The destination
operand is a ZMM/YMM/XMM register conditionally updated with writemask
k1. Attempt to encode this instruction with EVEX embedded rounding is
ignored.

.PP
VEX.256 encoded version: The source operand is an XMM register or 128-
bit memory location. The destination operand is a YMM register.

.PP
VEX.128 encoded version: The source operand is an XMM register or 64-
bit memory location. The destination operand is a XMM register. The
upper Bits (MAXVL-1:128) of the corresponding ZMM register destination
are zeroed.

.PP
128-bit Legacy SSE version: The source operand is an XMM register or 64-
bit memory location. The destination operand is an XMM register. The
upper Bits (MAXVL-1:128) of the corresponding ZMM register destination
are unmodified.

.PP
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise
instructions will #UD.

.SH OPERATION
.SS VCVTDQ2PD (EVEX Encoded Versions) When SRC Operand is a Register
.EX
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
    i := j * 64
    k := j * 32
    IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] :=
            Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
        ELSE
            IF *merging-masking* ; merging-masking
                THEN *DEST[i+63:i] remains unchanged*
                ELSE ; zeroing-masking
                    DEST[i+63:i] := 0
            FI
    FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
.EE

.SS VCVTDQ2PD (EVEX Encoded Versions) When SRC Operand is a Memory Source
.EX
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j := 0 TO KL-1
    i := j * 64
    k := j * 32
    IF k1[j] OR *no writemask*
        THEN
            IF (EVEX.b = 1)
                THEN
                    DEST[i+63:i] :=
            Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
                ELSE
                    DEST[i+63:i] :=
            Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
            FI;
        ELSE
            IF *merging-masking* ; merging-masking
                THEN *DEST[i+63:i] remains unchanged*
                ELSE ; zeroing-masking
                    DEST[i+63:i] := 0
            FI
    FI;
ENDFOR
DEST[MAXVL-1:VL] := 0
.EE

.SS VCVTDQ2PD (VEX.256 Encoded Version)
.EX
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAXVL-1:256] := 0
.EE

.SS VCVTDQ2PD (VEX.128 Encoded Version)
.EX
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAXVL-1:128] := 0
.EE

.SS CVTDQ2PD (128-bit Legacy SSE Version)
.EX
DEST[63:0] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] := Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAXVL-1:128] (unmodified)
.EE

.SH INTEL C/C++ COMPILER INTRINSIC EQUIVALENT
.EX
VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);

VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);

VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);

VCVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src);

VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);

VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);

VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);

VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);

CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)
.EE

.SH OTHER EXCEPTIONS
VEX-encoded instructions, see Table
2-22, “Type 5 Class Exception Conditions.”

.PP
EVEX-encoded instructions, see Table
2-51, “Type E5 Class Exception Conditions.”

.PP
Additionally:

.TS
allbox;
l l 
l l .
\fB\fP	\fB\fP
#UD	T{
If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
T}
.TE

.SH SEE ALSO
x86-manpages(7) for a list of other x86-64 man pages.

.SH COLOPHON
This UNOFFICIAL, mechanically-separated, non-verified reference is
provided for convenience, but it may be
incomplete or
broken in various obvious or non-obvious ways.
Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual
for anything serious.

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