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‎manx86/aaa.x86‎

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'\" t
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.nh
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.TH "X86-AAA" "7" "May 2019" "TTMO" "Intel x86-64 ISA Manual"
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.SH NAME
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AAA - ASCII ADJUST AFTER ADDITION
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.TS
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allbox;
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l l l l l l
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l l l l l l .
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\fBOpcode\fP \fBInstruction\fP \fBOp/En\fP \fB64-bit Mode\fP \fBCompat/Leg Mode\fP \fBDescription\fP
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37 AAA ZO Invalid Valid T{
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ASCII adjust AL after addition.
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T}
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.TE
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.SH INSTRUCTION OPERAND ENCODING
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.TS
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allbox;
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l l l l l
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l l l l l .
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\fBOp/En\fP \fBOperand 1\fP \fBOperand 2\fP \fBOperand 3\fP \fBOperand 4\fP
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ZO N/A N/A N/A N/A
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.TE
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.SH DESCRIPTION
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Adjusts the sum of two unpacked BCD values to create an unpacked BCD
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result. The AL register is the implied source and destination operand
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for this instruction. The AAA instruction is only useful when it follows
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an ADD instruction that adds (binary addition) two unpacked BCD values
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and stores a byte result in the AL register. The AAA instruction then
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adjusts the contents of the AL register to contain the correct 1-digit
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unpacked BCD result.
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.PP
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If the addition produces a decimal carry, the AH register increments by
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1, and the CF and AF flags are set. If there was no decimal carry, the
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CF and AF flags are cleared and the AH register is unchanged. In either
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case, bits 4 through 7 of the AL register are set to 0.
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.PP
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This instruction executes as described in compatibility mode and legacy
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mode. It is not valid in 64-bit mode.
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.SH OPERATION
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.EX
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IF 64-Bit Mode
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THEN
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#UD;
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ELSE
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IF ((AL AND 0FH) > 9) or (AF = 1)
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THEN
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AX := AX + 106H;
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AF := 1;
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CF := 1;
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ELSE
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AF := 0;
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CF := 0;
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FI;
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AL := AL AND 0FH;
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FI;
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.EE
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.SH FLAGS AFFECTED
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The AF and CF flags are set to 1 if the adjustment results in a decimal
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carry; otherwise they are set to 0. The OF, SF, ZF, and PF flags are
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undefined.
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.SH PROTECTED MODE EXCEPTIONS
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.TS
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allbox;
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l l
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l l .
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\fB\fP \fB\fP
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#UD If the LOCK prefix is used.
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.TE
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.SH REAL-ADDRESS MODE EXCEPTIONS
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Same exceptions as protected mode.
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.SH VIRTUAL-8086 MODE EXCEPTIONS
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Same exceptions as protected mode.
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.SH COMPATIBILITY MODE EXCEPTIONS
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Same exceptions as protected mode.
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.SH 64-BIT MODE EXCEPTIONS
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.TS
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allbox;
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l l
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l l .
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\fB\fP \fB\fP
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#UD If in 64-bit mode.
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.TE
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.SH SEE ALSO
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x86-manpages(7) for a list of other x86-64 man pages.
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.SH COLOPHON
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This UNOFFICIAL, mechanically-separated, non-verified reference is
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provided for convenience, but it may be
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incomplete or
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broken in various obvious or non-obvious ways.
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Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual
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for anything serious.
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.br
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This page is generated by scripts; therefore may contain visual or semantical bugs. Please report them (or better, fix them) on https://github.com/ttmo-O/x86-manpages.
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.br
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MIT licensed by TTMO 2025 (Turkish Unofficial Chamber of Reverse Engineers - https://ttmo.re).

‎manx86/aad.x86‎

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'\" t
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.nh
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.TH "X86-AAD" "7" "May 2019" "TTMO" "Intel x86-64 ISA Manual"
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.SH NAME
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AAD - ASCII ADJUST AX BEFORE DIVISION
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.TS
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allbox;
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l l l l l l
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l l l l l l .
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\fBOpcode\fP \fBInstruction\fP \fBOp/En\fP \fB64-bit Mode\fP \fBCompat/Leg Mode\fP \fBDescription\fP
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D5 0A AAD ZO Invalid Valid T{
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ASCII adjust AX before division.
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T}
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D5 ib AAD imm8 ZO Invalid Valid T{
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Adjust AX before division to number base imm8.
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T}
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.TE
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.SH INSTRUCTION OPERAND ENCODING
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.TS
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allbox;
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l l l l l
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l l l l l .
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\fBOp/En\fP \fBOperand 1\fP \fBOperand 2\fP \fBOperand 3\fP \fBOperand 4\fP
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ZO N/A N/A N/A N/A
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.TE
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.SH DESCRIPTION
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Adjusts two unpacked BCD digits (the least-significant digit in the AL
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register and the most-significant digit in the AH register) so that a
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division operation performed on the result will yield a correct unpacked
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BCD value. The AAD instruction is only useful when it precedes a DIV
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instruction that divides (binary division) the adjusted value in the AX
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register by an unpacked BCD value.
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.PP
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The AAD instruction sets the value in the AL register to (AL + (10 *
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AH)), and then clears the AH register to 00H. The value in the AX
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register is then equal to the binary equivalent of the original unpacked
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two-digit (base 10) number in registers AH and AL.
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.PP
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The generalized version of this instruction allows adjustment of two
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unpacked digits of any number base (see the “Operation” section below),
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by setting the imm8).
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.PP
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This instruction executes as described in compatibility mode and legacy
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mode. It is not valid in 64-bit mode.
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.SH OPERATION
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.EX
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IF 64-Bit Mode
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THEN
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#UD;
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ELSE
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tempAL := AL;
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tempAH := AH;
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AL := (tempAL + (tempAH ∗ imm8)) AND FFH;
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(* imm8 is set to 0AH for the AAD mnemonic.*)
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AH := 0;
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FI;
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The immediate value (imm8) is taken from the second byte of the instruction.
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.EE
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.SH FLAGS AFFECTED
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The SF, ZF, and PF flags are set according to the resulting binary value
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in the AL register; the OF, AF, and CF flags are undefined.
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.SH PROTECTED MODE EXCEPTIONS
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.TS
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allbox;
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l l
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l l .
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\fB\fP \fB\fP
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#UD If the LOCK prefix is used.
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.TE
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.SH REAL-ADDRESS MODE EXCEPTIONS
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Same exceptions as protected mode.
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.SH VIRTUAL-8086 MODE EXCEPTIONS
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Same exceptions as protected mode.
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.SH COMPATIBILITY MODE EXCEPTIONS
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Same exceptions as protected mode.
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.SH 64-BIT MODE EXCEPTIONS
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.TS
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allbox;
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l l
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l l .
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\fB\fP \fB\fP
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#UD If in 64-bit mode.
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.TE
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.SH SEE ALSO
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x86-manpages(7) for a list of other x86-64 man pages.
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.SH COLOPHON
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This UNOFFICIAL, mechanically-separated, non-verified reference is
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provided for convenience, but it may be
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incomplete or
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broken in various obvious or non-obvious ways.
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Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual
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for anything serious.
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.br
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This page is generated by scripts; therefore may contain visual or semantical bugs. Please report them (or better, fix them) on https://github.com/ttmo-O/x86-manpages.
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.br
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MIT licensed by TTMO 2025 (Turkish Unofficial Chamber of Reverse Engineers - https://ttmo.re).

‎manx86/aam.x86‎

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'\" t
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.nh
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.TH "X86-AAM" "7" "May 2019" "TTMO" "Intel x86-64 ISA Manual"
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.SH NAME
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AAM - ASCII ADJUST AX AFTER MULTIPLY
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.TS
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allbox;
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l l l l l l
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l l l l l l .
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\fBOpcode\fP \fBInstruction\fP \fBOp/En\fP \fB64-bit Mode\fP \fBCompat/Leg Mode\fP \fBDescription\fP
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D4 0A AAM ZO Invalid Valid T{
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ASCII adjust AX after multiply.
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T}
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D4 ib AAM imm8 ZO Invalid Valid T{
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Adjust AX after multiply to number base imm8.
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T}
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.TE
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.SH INSTRUCTION OPERAND ENCODING
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.TS
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allbox;
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l l l l l
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l l l l l .
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\fBOp/En\fP \fBOperand 1\fP \fBOperand 2\fP \fBOperand 3\fP \fBOperand 4\fP
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ZO N/A N/A N/A N/A
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.TE
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.SH DESCRIPTION
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Adjusts the result of the multiplication of two unpacked BCD values to
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create a pair of unpacked (base 10) BCD values. The AX register is the
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implied source and destination operand for this instruction. The AAM
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instruction is only useful when it follows an MUL instruction that
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multiplies (binary multiplication) two unpacked BCD values and stores a
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word result in the AX register. The AAM instruction then adjusts the
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contents of the AX register to contain the correct 2-digit unpacked
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(base 10) BCD result.
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.PP
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The generalized version of this instruction allows adjustment of the
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contents of the AX to create two unpacked digits of any number base (see
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the “Operation” section below). Here, the imm8).
42+
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.PP
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This instruction executes as described in compatibility mode and legacy
45+
mode. It is not valid in 64-bit mode.
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.SH OPERATION
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.EX
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IF 64-Bit Mode
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THEN
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#UD;
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ELSE
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tempAL := AL;
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AH := tempAL / imm8 is set to 0AH for the AAM mnemonic *)
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AL := tempAL MOD imm8;
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FI;
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The immediate value (imm8) is taken from the second byte of the instruction.
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.EE
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.SH FLAGS AFFECTED
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The SF, ZF, and PF flags are set according to the resulting binary value
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in the AL register. The OF, AF, and CF flags are undefined.
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.SH PROTECTED MODE EXCEPTIONS
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.TS
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allbox;
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l l
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l l .
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\fB\fP \fB\fP
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#DE T{
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If an immediate value of 0 is used.
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T}
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#UD If the LOCK prefix is used.
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.TE
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.SH REAL-ADDRESS MODE EXCEPTIONS
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Same exceptions as protected mode.
78+
79+
.SH VIRTUAL-8086 MODE EXCEPTIONS
80+
Same exceptions as protected mode.
81+
82+
.SH COMPATIBILITY MODE EXCEPTIONS
83+
Same exceptions as protected mode.
84+
85+
.SH 64-BIT MODE EXCEPTIONS
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.TS
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allbox;
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l l
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l l .
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\fB\fP \fB\fP
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#UD If in 64-bit mode.
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.TE
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.SH SEE ALSO
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x86-manpages(7) for a list of other x86-64 man pages.
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.SH COLOPHON
98+
This UNOFFICIAL, mechanically-separated, non-verified reference is
99+
provided for convenience, but it may be
100+
incomplete or
101+
broken in various obvious or non-obvious ways.
102+
Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual
103+
for anything serious.
104+
105+
.br
106+
This page is generated by scripts; therefore may contain visual or semantical bugs. Please report them (or better, fix them) on https://github.com/ttmo-O/x86-manpages.
107+
108+
.br
109+
MIT licensed by TTMO 2025 (Turkish Unofficial Chamber of Reverse Engineers - https://ttmo.re).

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