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wave-36e: t27c add gen-dma-controller for BitNet DDR<->BRAM activation streaming (R-BN-5, Closes #768)#769

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wave-36e: t27c add gen-dma-controller for BitNet DDR<->BRAM activation streaming (R-BN-5, Closes #768)#769
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@gHashTag gHashTag commented May 23, 2026

Closes #768

This wave (R-BN-5) ports writeDmaController from gHashTag/vibee-lang (src/vibeec/verilog_codegen.zig, lines 1452-1548) into the t27c bootstrap CLI as a parameterised emitter for the BitNet HLS pipeline's DDR <-> on-chip-BRAM data mover. With this module the host can program DDR base addresses via the AXI-Lite CSR aperture emitted in W36d, then have the DMA engine stream 64-bit beats into the local BRAM that the compute pipeline (W36b) and double-buffer storage (W36c) already consume. The interrupt controller and engine top-level are intentionally deferred to W36f to keep the L4 test surface manageable.

What changed

  • bootstrap/src/bitnet_dma.rs (new, ~395 lines): build_dma_controller(module_name) pure string emitter + Verilog-ident validator with safe fallback + 15 inline unit tests.
  • bootstrap/src/main.rs (additive only): mod bitnet_dma;, new Commands::GenDmaController { module_name, output } variant, run_gen_dma_controller(...) helper routed through the shared write_verilog_to_output(...), dispatch in both HTTP-server and CLI match arms.
  • bootstrap/tests/bitnet_dma.rs (new, 22 integration tests via CARGO_BIN_EXE_t27c, no tempfile crate — uses std::env::temp_dir()).
  • docs/NOW.md prepended with the W36e section.

CLI surface

t27c gen-dma-controller --module-name dma_ddr_to_bram
t27c gen-dma-controller --module-name dma_ddr_to_bram --output /tmp/dma.sv

Invalid Verilog identifiers ("", "9bad", "has space", "dash-name", ...) fall back to the default name dma_controller.

Sample output

// ===========================================================================
// DMA CONTROLLER - High-bandwidth data transfer
// ===========================================================================
// Generated by t27c gen-dma-controller (Wave 36e, R-BN-5).
// AXI4 master DMA between off-chip DDR and on-chip local memory.
// direction = 0 -> DDR (src_addr) read into local memory.
// direction = 1 -> local memory written out to DDR (dst_addr).
// One beat = 8 bytes (64-bit). length is byte-count.

module dma_ddr_to_bram (
    input  wire        clk,
    input  wire        rst_n,
    // Control
    input  wire        start,
    input  wire [63:0] src_addr,
    input  wire [63:0] dst_addr,
    input  wire [31:0] length,
    input  wire        direction,  // 0=read, 1=write
    output reg         busy,
    output reg         done,
    // AXI4 Master Read
    output reg  [63:0] m_axi_araddr,
    output reg  [7:0]  m_axi_arlen,
    output reg         m_axi_arvalid,
    input  wire        m_axi_arready,
    input  wire [63:0] m_axi_rdata,
    input  wire        m_axi_rlast,
    input  wire        m_axi_rvalid,
    output wire        m_axi_rready,
    // AXI4 Master Write
    output reg  [63:0] m_axi_awaddr,
    output reg  [7:0]  m_axi_awlen,
    output reg         m_axi_awvalid,
    input  wire        m_axi_awready,
    output reg  [63:0] m_axi_wdata,
    output reg         m_axi_wlast,
    output reg         m_axi_wvalid,
    input  wire        m_axi_wready,
    input  wire        m_axi_bvalid,
    output wire        m_axi_bready,
    // Local memory interface
    output reg  [11:0] local_addr,
    output reg  [63:0] local_wdata,
    output reg         local_we,
    input  wire [63:0] local_rdata
);

    localparam IDLE       = 3'd0;
    localparam READ_ADDR  = 3'd1;
    localparam READ_DATA  = 3'd2;
    localparam WRITE_ADDR = 3'd3;
    localparam WRITE_DATA = 3'd4;
    localparam DONE_ST    = 3'd5;
    ...

Constitutional gates (L1-L7)

  • L1 TRACEABILITY: Closes #768 in title + body + commit message
  • L2 SCOPE: edits confined to bootstrap/src/{bitnet_dma.rs,main.rs}, bootstrap/tests/bitnet_dma.rs, docs/NOW.md. Zero changes under gen/, coq/, trios-coq/, proofs/, specs/, conformance/, architecture/, rings/, root Cargo.toml.
  • L3 ASCII: source ASCII-only, English doc-comments, emitted Verilog ASCII-only (asserted by test dma_output_is_pure_ascii).
  • L4 TESTS: 22 integration + 15 inline unit = 37 new tests; full regression sweep (116 tests across 12 existing suites) re-runs green. Total 138/138.
  • L5 KERNEL UNTOUCHED: numeric kernel and trinity invariant phi^2 + 1/phi^2 = 3 not touched -- this emitter is a data-mover only.
  • L6 SPEC FROZEN: zero spec / kernel changes.
  • *L7 NO NEW .sh: no shell scripts added.

Tests

  • W36e integration: 22 / 22 passed (cargo test -p t27c --release --test bitnet_dma).
  • W36e inline unit: 15 / 15 (compiled and embedded; verified locally).
  • Regression sweep: behavior_sva 8, bitnet_axi 18, bitnet_buffers 22, bitnet_pipeline 20, phi_selfcheck 11, trit_stdlib 14, verilog_array_literal_expr 2, verilog_const_array 2, verilog_initial_decl 2, verilog_r_si_1 2, verilog_translate_off 2, weight_bram 13 = 116 / 116.
  • Total: 138 / 138.

Source attribution

Ported from gHashTag/vibee-lang, file src/vibeec/verilog_codegen.zig, function writeDmaController (lines 1452-1548). Original author: Dmitrii Vasilev (@gHashTag). Bit-level equivalence with the upstream emitter is the explicit goal of this wave.

Known orthogonal CI failures

The fpga-formal, fpga-synthesis-arty, and fpga-bitstream jobs are expected to fail on every PR until their upstream toolchains are wired in — they are not gated by anything this wave changes. All other required gates (check, coverage, fpga-conformance, fpga-smoke, fpga-lint, fpga-synthesis, phi-loop-check, Check L1 TRACEABILITY, NotebookLM, validate, pr-dashboard) are expected to pass.

Roadmap

After this wave, the BitNet HLS pipeline stands at 7 / 9 modules: weight_bram (W36a), pipeline_stage2_compute + layer_sequencer (W36b), double_buffer_ctrl + weight_prefetch_ctrl (W36c), axi_lite_slave (W36d), and now dma_controller (W36e). Remaining: interrupt_controller + bitnet_engine_top (W36f). Beyond W36f the program moves on to W37 (richer behavior-DSL — multi-clause antecedents, ##N, s_eventually) and W38+ (wiring stdlib + behavior emitter into the existing gen_verilog_* spec emits, which will be the first wave that needs L2 / L6 reconsideration).

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github-actions Bot commented May 23, 2026

📓 NotebookLM Notebook linked to this PR

This notebook contains session context, decisions, and artifacts for this work.

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github-actions Bot commented May 23, 2026

PR Dashboard

Generated at: 2026-05-23 12:51:07 UTC

Summary

Status Count
Total Open PRs 22
PRs with Failing Checks 20
PRs with All Checks Green 2
READY 1
FAILING 20
PENDING 0

@gHashTag gHashTag merged commit b38784d into master May 23, 2026
20 of 23 checks passed
@gHashTag gHashTag deleted the wave-36e/dma-controller branch May 23, 2026 12:55
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Wave 36e (R-BN-5): t27c add gen-dma-controller for BitNet DDR<->BRAM activation streaming

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