From d3de28866f3bfd2304f6b206dff3f07fc2657c2c Mon Sep 17 00:00:00 2001 From: Andrew Kurushin Date: Fri, 22 Jul 2022 16:41:21 +0300 Subject: [PATCH 1/4] add intel goldmont plus --- include/cpuinfo_x86.h | 1 + src/impl_x86__base_implementation.inl | 3 +++ test/cpuinfo_x86_test.cc | 15 +++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 9cb56e56..f888756e 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -138,6 +138,7 @@ typedef enum { INTEL_BDW, // BROADWELL INTEL_SKL, // SKYLAKE INTEL_ATOM_GMT, // GOLDMONT + INTEL_ATOM_GMT_P, // GOLDMONT+ INTEL_KBL, // KABY LAKE INTEL_CFL, // COFFEE LAKE INTEL_WHL, // WHISKEY LAKE diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index fb295470..8122f45d 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -463,6 +463,9 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { case CPUID(0x06, 0x5C): // https://en.wikipedia.org/wiki/Goldmont return INTEL_ATOM_GMT; + case CPUID(0x06, 0x7A): + // https://en.wikichip.org/wiki/intel/microarchitectures/goldmont_plus + return INTEL_ATOM_GMT_P; case CPUID(0x06, 0x0F): case CPUID(0x06, 0x16): // https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture) diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index 3306333a..b14c4f88 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -1138,6 +1138,21 @@ TEST_F(CpuidX86Test, INTEL_LAKEMONT) { X86Microarchitecture::INTEL_LAKEMONT); } +// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00706A8_GoldmontPlus_CPUID.txt +TEST_F(CpuidX86Test, INTEL_GOLDMONT_PLUS) { + cpu().SetLeaves({ + {{0x00000000, 0}, Leaf{0x00000018, 0x756E6547, 0x6c65746E, 0x49656E69}}, + {{0x00000001, 0}, Leaf{0x000706A8, 0x00400800, 0x4FF8EBBF, 0xBFEBFBFF}}, + }); + const auto info = GetX86Info(); + + EXPECT_STREQ(info.vendor, "GenuineIntel"); + EXPECT_EQ(info.family, 0x06); + EXPECT_EQ(info.model, 0x7A); + EXPECT_EQ(GetX86Microarchitecture(&info), + X86Microarchitecture::INTEL_ATOM_GMT_P); +} + // https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel0050670_KnightsLanding_CPUID.txt TEST_F(CpuidX86Test, INTEL_KNIGHTS_LANDING) { cpu().SetLeaves({ From 757b5241271a7c095ca1f163fb33f68350febc17 Mon Sep 17 00:00:00 2001 From: Andrew Kurushin Date: Sat, 23 Jul 2022 01:09:07 +0300 Subject: [PATCH 2/4] update names macro --- src/impl_x86__base_implementation.inl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index 8122f45d..a85361b6 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -1784,6 +1784,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(INTEL_BDW) \ LINE(INTEL_SKL) \ LINE(INTEL_ATOM_GMT) \ + LINE(INTEL_ATOM_GMT_P) \ LINE(INTEL_KBL) \ LINE(INTEL_CFL) \ LINE(INTEL_WHL) \ From c8bca33bfdb93cf234bfa121b872e307d1070c16 Mon Sep 17 00:00:00 2001 From: Andrew Kurushin Date: Fri, 5 Aug 2022 16:30:04 +0300 Subject: [PATCH 3/4] use CPU_FEATURES_VENDOR_GENUINE_INTEL --- test/cpuinfo_x86_test.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index b14c4f88..33a4dbfc 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -1146,7 +1146,7 @@ TEST_F(CpuidX86Test, INTEL_GOLDMONT_PLUS) { }); const auto info = GetX86Info(); - EXPECT_STREQ(info.vendor, "GenuineIntel"); + EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL); EXPECT_EQ(info.family, 0x06); EXPECT_EQ(info.model, 0x7A); EXPECT_EQ(GetX86Microarchitecture(&info), From d7f601a4a34c12d12410495f604919678e88aa38 Mon Sep 17 00:00:00 2001 From: Andrew Kurushin Date: Fri, 5 Aug 2022 17:09:35 +0300 Subject: [PATCH 4/4] INTEL_ATOM_GMT_P->INTEL_ATOM_GMT_PLUS --- include/cpuinfo_x86.h | 2 +- src/impl_x86__base_implementation.inl | 4 ++-- test/cpuinfo_x86_test.cc | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 06569fd6..108c9b1d 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -140,7 +140,7 @@ typedef enum { INTEL_BDW, // BROADWELL INTEL_SKL, // SKYLAKE INTEL_ATOM_GMT, // GOLDMONT - INTEL_ATOM_GMT_P, // GOLDMONT+ + INTEL_ATOM_GMT_PLUS, // GOLDMONT+ INTEL_ATOM_TMT, // TREMONT INTEL_KBL, // KABY LAKE INTEL_CFL, // COFFEE LAKE diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index 07f328e4..cfde9074 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -468,7 +468,7 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { return INTEL_ATOM_GMT; case CPUID(0x06, 0x7A): // https://en.wikichip.org/wiki/intel/microarchitectures/goldmont_plus - return INTEL_ATOM_GMT_P; + return INTEL_ATOM_GMT_PLUS; case CPUID(0x06, 0x8A): case CPUID(0x06, 0x96): case CPUID(0x06, 0x9C): @@ -1795,7 +1795,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(INTEL_BDW) \ LINE(INTEL_SKL) \ LINE(INTEL_ATOM_GMT) \ - LINE(INTEL_ATOM_GMT_P) \ + LINE(INTEL_ATOM_GMT_PLUS) \ LINE(INTEL_ATOM_TMT) \ LINE(INTEL_KBL) \ LINE(INTEL_CFL) \ diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index f52f33e8..c9210830 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -1158,7 +1158,7 @@ TEST_F(CpuidX86Test, INTEL_GOLDMONT_PLUS) { EXPECT_EQ(info.family, 0x06); EXPECT_EQ(info.model, 0x7A); EXPECT_EQ(GetX86Microarchitecture(&info), - X86Microarchitecture::INTEL_ATOM_GMT_P); + X86Microarchitecture::INTEL_ATOM_GMT_PLUS); } // https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel0050670_KnightsLanding_CPUID.txt