From 333fa0bc0703c663f766304ef97e62b7e857e8b0 Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Tue, 26 Jul 2022 15:26:48 +0200 Subject: [PATCH 1/8] added some missing amd uarch --- include/cpuinfo_x86.h | 1 + src/impl_x86__base_implementation.inl | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 9cb56e56..ef117a0d 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -157,6 +157,7 @@ typedef enum { AMD_K10, // K10 AMD_K11, // K11 AMD_K12, // K12 + AMD_LLANO, // LLANO AMD_BOBCAT, // K14 BOBCAT AMD_PILEDRIVER, // K15 PILEDRIVER AMD_STREAMROLLER, // K15 STREAMROLLER diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index fb295470..12703ea7 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -667,6 +667,9 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { case CPUID(0x12, 0x01): // https://www.amd.com/system/files/TechDocs/44739_12h_Rev_Gd.pdf return AMD_K12; + case CPUID(0x12, 0x00): + // https://www.amd.com/system/files/TechDocs/44739_12h_Rev_Gd.pdf + return AMD_LLANO; case CPUID(0x14, 0x00): case CPUID(0x14, 0x01): case CPUID(0x14, 0x02): @@ -676,6 +679,7 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { // https://en.wikichip.org/wiki/amd/microarchitectures/bulldozer return AMD_BULLDOZER; case CPUID(0x15, 0x02): + case CPUID(0x15, 0x10): case CPUID(0x15, 0x11): case CPUID(0x15, 0x13): // https://en.wikichip.org/wiki/amd/microarchitectures/piledriver @@ -695,11 +699,12 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { return AMD_PUMA; case CPUID(0x17, 0x01): case CPUID(0x17, 0x11): - case CPUID(0x17, 0x18): case CPUID(0x17, 0x20): + case CPUID(0x18, 0x00): // https://en.wikichip.org/wiki/amd/microarchitectures/zen return AMD_ZEN; case CPUID(0x17, 0x08): + case CPUID(0x17, 0x18): // https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B return AMD_ZEN_PLUS; case CPUID(0x17, 0x31): @@ -1800,6 +1805,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(AMD_K10) \ LINE(AMD_K11) \ LINE(AMD_K12) \ + LINE(AMD_LLANO) \ LINE(AMD_BOBCAT) \ LINE(AMD_PILEDRIVER) \ LINE(AMD_STREAMROLLER) \ From 3d56e463dfeb87bd7779c88f32fcdf5b8bc1f9cc Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Wed, 27 Jul 2022 23:23:00 +0200 Subject: [PATCH 2/8] removed llano uarch --- src/impl_x86__base_implementation.inl | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index 12703ea7..3f7206f8 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -664,12 +664,10 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { case CPUID(0x11, 0x03): // http://developer.amd.com/wordpress/media/2012/10/41788.pdf return AMD_K11; + case CPUID(0x12, 0x00): case CPUID(0x12, 0x01): // https://www.amd.com/system/files/TechDocs/44739_12h_Rev_Gd.pdf return AMD_K12; - case CPUID(0x12, 0x00): - // https://www.amd.com/system/files/TechDocs/44739_12h_Rev_Gd.pdf - return AMD_LLANO; case CPUID(0x14, 0x00): case CPUID(0x14, 0x01): case CPUID(0x14, 0x02): @@ -699,12 +697,11 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { return AMD_PUMA; case CPUID(0x17, 0x01): case CPUID(0x17, 0x11): + case CPUID(0x17, 0x18): case CPUID(0x17, 0x20): - case CPUID(0x18, 0x00): // https://en.wikichip.org/wiki/amd/microarchitectures/zen return AMD_ZEN; case CPUID(0x17, 0x08): - case CPUID(0x17, 0x18): // https://en.wikichip.org/wiki/amd/microarchitectures/zen%2B return AMD_ZEN_PLUS; case CPUID(0x17, 0x31): @@ -1804,8 +1801,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(AMD_HAMMER) \ LINE(AMD_K10) \ LINE(AMD_K11) \ - LINE(AMD_K12) \ - LINE(AMD_LLANO) \ + LINE(AMD_K12) /* K12 LLANO */ \ LINE(AMD_BOBCAT) \ LINE(AMD_PILEDRIVER) \ LINE(AMD_STREAMROLLER) \ From 891a2f675006db532a969d08f5d45a6f3c249c42 Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Wed, 27 Jul 2022 23:26:44 +0200 Subject: [PATCH 3/8] removed llano definition --- include/cpuinfo_x86.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index ef117a0d..9cb56e56 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -157,7 +157,6 @@ typedef enum { AMD_K10, // K10 AMD_K11, // K11 AMD_K12, // K12 - AMD_LLANO, // LLANO AMD_BOBCAT, // K14 BOBCAT AMD_PILEDRIVER, // K15 PILEDRIVER AMD_STREAMROLLER, // K15 STREAMROLLER From 3087eec45f9cf1e61bac16b7d277417e9ba663d9 Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Fri, 29 Jul 2022 10:18:29 +0200 Subject: [PATCH 4/8] moved comment --- include/cpuinfo_x86.h | 2 +- src/impl_x86__base_implementation.inl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 9cb56e56..14406cdc 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -156,7 +156,7 @@ typedef enum { AMD_HAMMER, // K8 HAMMER AMD_K10, // K10 AMD_K11, // K11 - AMD_K12, // K12 + AMD_K12, // K12 LLANO AMD_BOBCAT, // K14 BOBCAT AMD_PILEDRIVER, // K15 PILEDRIVER AMD_STREAMROLLER, // K15 STREAMROLLER diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index 3f7206f8..562c2e23 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -1801,7 +1801,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(AMD_HAMMER) \ LINE(AMD_K10) \ LINE(AMD_K11) \ - LINE(AMD_K12) /* K12 LLANO */ \ + LINE(AMD_K12) \ LINE(AMD_BOBCAT) \ LINE(AMD_PILEDRIVER) \ LINE(AMD_STREAMROLLER) \ From b9e5202c7529071c4c16d7088e956ebb965e4b25 Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Thu, 4 Aug 2022 21:15:46 +0200 Subject: [PATCH 5/8] Removed duplicate of #256 --- src/impl_x86__base_implementation.inl | 1 - 1 file changed, 1 deletion(-) diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index 562c2e23..0678e47f 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -677,7 +677,6 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { // https://en.wikichip.org/wiki/amd/microarchitectures/bulldozer return AMD_BULLDOZER; case CPUID(0x15, 0x02): - case CPUID(0x15, 0x10): case CPUID(0x15, 0x11): case CPUID(0x15, 0x13): // https://en.wikichip.org/wiki/amd/microarchitectures/piledriver From e72f7ec482d31984825f25def8e023129244fcf3 Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Sun, 7 Aug 2022 22:42:47 +0200 Subject: [PATCH 6/8] RISC-V feature detection --- include/cpuinfo_riscv.h | 90 ++++++++++++++++++++++ include/internal/hwcaps.h | 3 + src/impl_riscv_linux_or_android.c | 120 ++++++++++++++++++++++++++++++ 3 files changed, 213 insertions(+) create mode 100644 include/cpuinfo_riscv.h create mode 100644 src/impl_riscv_linux_or_android.c diff --git a/include/cpuinfo_riscv.h b/include/cpuinfo_riscv.h new file mode 100644 index 00000000..942f021b --- /dev/null +++ b/include/cpuinfo_riscv.h @@ -0,0 +1,90 @@ +// Copyright 2022 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ +#define CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ + +#include "cpu_features_cache_info.h" +#include "cpu_features_macros.h" + +//#if !defined(CPU_FEATURES_ARCH_RISCV) +//#error "Including cpuinfo_riscv.h from a non-riscv target." +//#endif + +CPU_FEATURES_START_CPP_NAMESPACE + +typedef struct { + int riscv32 : 1; // Is a 32 bit architecture + int riscv64 : 1; // Is a 64 bit architecture + int riscv128 : 1; // Is a 128 bit architecture + int a : 1; // Atomic Instructions + int c : 1; // Compressed Instructions + int d : 1; // Double Precision Floating Point + int e : 1; // Base Integer Reduced + int f : 1; // Single Precision Floating Point + int i : 1; // Base Integer + int m : 1; // Integer Multiplication and Division + int v : 1; // Vector Operations + int q : 1; // Quad Precision Floating Point +} RiscvFeatures; + +typedef enum +{ + RISCV_UNKNOWN, + N25, + CODIX_BK3, + CODIX_BK5, + CODIX_BK7, + ET_MINION, + ET_MAXION, + BOTTLEROCKET, + MI_V, + NV_RISCV, + E31, + E51, + E54_MC, + _7_SERIES, + VANILLA_5, + ROCKET, + RISCV_MICROARCHITECTURE_LAST_ +} RiscvMicroarchitecture; + +typedef struct { + RiscvFeatures features; + RiscvMicroarchitecture uarch; + //Address space size (32, 64, 128)? +} RiscvInfo; + +typedef enum { + RISCV_32, + RISCV_64, + RISCV_128, + RISCV_A, + RISCV_C, + RISCV_D, + RISCV_E, + RISCV_F, + RISCV_I, + RISCV_M, + RISCV_V, + RISCV_Q, + RISCV_LAST_, +} RiscvFeaturesEnum; + +RiscvInfo GetRiscvInfo(void); + +CPU_FEATURES_END_CPP_NAMESPACE + +#endif // CPU_FEATURES_INCLUDE_CPUINFO_RISCV_H_ + diff --git a/include/internal/hwcaps.h b/include/internal/hwcaps.h index f916b81c..ff7c16a5 100644 --- a/include/internal/hwcaps.h +++ b/include/internal/hwcaps.h @@ -177,6 +177,9 @@ CPU_FEATURES_START_CPP_NAMESPACE #endif // https://elixir.bootlin.com/linux/latest/source/arch/riscv/include/uapi/asm/hwcap.h +#define RISCV_HWCAP_32 0x32 +#define RISCV_HWCAP_64 0x64 +#define RISCV_HWCAP_128 0x128 #define RISCV_HWCAP_A (1UL << ('A' - 'A')) #define RISCV_HWCAP_C (1UL << ('C' - 'A')) #define RISCV_HWCAP_D (1UL << ('D' - 'A')) diff --git a/src/impl_riscv_linux_or_android.c b/src/impl_riscv_linux_or_android.c new file mode 100644 index 00000000..54140d6d --- /dev/null +++ b/src/impl_riscv_linux_or_android.c @@ -0,0 +1,120 @@ +// Copyright 2022 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "cpu_features_macros.h" + +//#ifndef CPU_FEATURES_ARCH_RISCV +//#if defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) + +#include "cpuinfo_riscv.h" + +//////////////////////////////////////////////////////////////////////////////// +// Definitions for introspection. +//////////////////////////////////////////////////////////////////////////////// +#define INTROSPECTION_TABLE \ + LINE(RISCV_32, riscv32, "32", RISCV_HWCAP_32, 0) \ + LINE(RISCV_64, riscv64, "64", RISCV_HWCAP_64, 0) \ + LINE(RISCV_128, riscv128, "128", RISCV_HWCAP_128, 0) \ + LINE(RISCV_A, a, "a", RISCV_HWCAP_A, 0) \ + LINE(RISCV_C, c, "c", RISCV_HWCAP_C, 0) \ + LINE(RISCV_D, d, "d", RISCV_HWCAP_D, 0) \ + LINE(RISCV_E, e, "e", RISCV_HWCAP_E, 0) \ + LINE(RISCV_F, f, "f", RISCV_HWCAP_F, 0) \ + LINE(RISCV_I, i, "i", RISCV_HWCAP_I, 0) \ + LINE(RISCV_M, m, "m", RISCV_HWCAP_M, 0) \ + LINE(RISCV_V, v, "v", RISCV_HWCAP_V, 0) \ + LINE(RISCV_Q, q, "q", RISCV_HWCAP_Q, 0) +#define INTROSPECTION_PREFIX Riscv +#define INTROSPECTION_ENUM_PREFIX RISCV +#include "define_introspection_and_hwcaps.inl" + +//////////////////////////////////////////////////////////////////////////////// +// Implementation. +//////////////////////////////////////////////////////////////////////////////// + +/* + UARCH FOUND: + sifive,bullet0 -> Series 7 +*/ + +#include "internal/stack_line_reader.h" +#include "internal/filesystem.h" + +#include +#include + +static const RiscvInfo kEmptyRiscvInfo; + +static bool HandleRiscVLine(const LineResult result, + RiscvInfo* const info) { + StringView line = result.line; + StringView key, value; + if (CpuFeatures_StringView_GetAttributeKeyValue(line, &key, &value)) { + if (CpuFeatures_StringView_IsEquals(key, str("isa"))) { + //CpuFeatures_StringView_IndexOf + StringView tmp_sv; + for (size_t i = 0; i < RISCV_LAST_; ++i){ + tmp_sv.ptr = kCpuInfoFlags[i]; + tmp_sv.size = strlen(kCpuInfoFlags[i]); + + kSetters[i](&info->features, + CpuFeatures_StringView_IndexOf(value, tmp_sv) > 1); + + } + } + if (CpuFeatures_StringView_IsEquals(key, str("uarch"))){ + //TODO + } + } + return !result.eof; +} + +static void FillProcCpuInfoData(RiscvInfo* const info) { + const int fd = CpuFeatures_OpenFile("/Users/danieleaffinita/Desktop/cpu/infocpu"); + if (fd >= 0) { + StackLineReader reader; + StackLineReader_Initialize(&reader, fd); + + for(;;){ + if(!HandleRiscVLine(StackLineReader_NextLine(&reader), info)) + break; + } + + CpuFeatures_CloseFile(fd); + } +} + +RiscvInfo GetRiscvInfo(void){ + RiscvInfo info = kEmptyRiscvInfo; + FillProcCpuInfoData(&info); + + //just testing + printf("PRETEST\n"); + printf("32 -> %d\n",info.features.riscv32); + printf("64 -> %d\n",info.features.riscv64); + printf("128 -> %d\n",info.features.riscv128); + printf("a -> %d\n",info.features.a); + printf("c -> %d\n",info.features.c); + printf("d -> %d\n",info.features.d); + printf("e -> %d\n",info.features.e); + printf("f -> %d\n",info.features.f); + printf("i -> %d\n",info.features.i); + printf("m -> %d\n",info.features.m); + printf("v -> %d\n",info.features.v); + printf("q -> %d\n",info.features.q); + fflush(stdout); +} + +//#endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) +//#endif // CPU_FEATURES_ARCH_RISCV \ No newline at end of file From 930a761e26a4cf19e438112bccba05904d5306c2 Mon Sep 17 00:00:00 2001 From: DaniAffCH Date: Wed, 17 Aug 2022 22:59:10 +0200 Subject: [PATCH 7/8] Architecture detection, vendor detection and automated tests --- CMakeLists.txt | 5 + include/cpuinfo_riscv.h | 34 ++--- ..._linux_or_android.c => impl_riscv_linux.c} | 51 +++----- src/utils/list_cpu_features.c | 11 ++ test/CMakeLists.txt | 7 + test/cpuinfo_riscv_test.cc | 123 ++++++++++++++++++ 6 files changed, 175 insertions(+), 56 deletions(-) rename src/{impl_riscv_linux_or_android.c => impl_riscv_linux.c} (76%) create mode 100644 test/cpuinfo_riscv_test.cc diff --git a/CMakeLists.txt b/CMakeLists.txt index 15d7aad6..e4e68b7e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -49,6 +49,7 @@ set(PROCESSOR_IS_ARM FALSE) set(PROCESSOR_IS_AARCH64 FALSE) set(PROCESSOR_IS_X86 FALSE) set(PROCESSOR_IS_POWER FALSE) +set(PROCESSOR_IS_RISCV FALSE) if(CMAKE_SYSTEM_PROCESSOR MATCHES "^mips") set(PROCESSOR_IS_MIPS TRUE) @@ -60,6 +61,8 @@ elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "(x86_64)|(AMD64|amd64)|(^i.86$)") set(PROCESSOR_IS_X86 TRUE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(powerpc|ppc)") set(PROCESSOR_IS_POWER TRUE) +elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^riscv") + set(PROCESSOR_IS_RISCV TRUE) endif() macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME) @@ -79,6 +82,8 @@ macro(add_cpu_features_headers_and_sources HDRS_LIST_NAME SRCS_LIST_NAME) list(APPEND ${SRCS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/internal/windows_utils.h) elseif(PROCESSOR_IS_POWER) list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_ppc.h) + elseif(PROCESSOR_IS_RISCV) + list(APPEND ${HDRS_LIST_NAME} ${PROJECT_SOURCE_DIR}/include/cpuinfo_riscv.h) else() message(FATAL_ERROR "Unsupported architectures ${CMAKE_SYSTEM_PROCESSOR}") endif() diff --git a/include/cpuinfo_riscv.h b/include/cpuinfo_riscv.h index 942f021b..fba88048 100644 --- a/include/cpuinfo_riscv.h +++ b/include/cpuinfo_riscv.h @@ -18,9 +18,9 @@ #include "cpu_features_cache_info.h" #include "cpu_features_macros.h" -//#if !defined(CPU_FEATURES_ARCH_RISCV) -//#error "Including cpuinfo_riscv.h from a non-riscv target." -//#endif +#if !defined(CPU_FEATURES_ARCH_RISCV) +#error "Including cpuinfo_riscv.h from a non-riscv target." +#endif CPU_FEATURES_START_CPP_NAMESPACE @@ -39,31 +39,11 @@ typedef struct { int q : 1; // Quad Precision Floating Point } RiscvFeatures; -typedef enum -{ - RISCV_UNKNOWN, - N25, - CODIX_BK3, - CODIX_BK5, - CODIX_BK7, - ET_MINION, - ET_MAXION, - BOTTLEROCKET, - MI_V, - NV_RISCV, - E31, - E51, - E54_MC, - _7_SERIES, - VANILLA_5, - ROCKET, - RISCV_MICROARCHITECTURE_LAST_ -} RiscvMicroarchitecture; typedef struct { - RiscvFeatures features; - RiscvMicroarchitecture uarch; - //Address space size (32, 64, 128)? + RiscvFeatures features; + char uarch[64]; // 0 terminated string + char vendor[64]; // 0 terminated string } RiscvInfo; typedef enum { @@ -83,6 +63,8 @@ typedef enum { } RiscvFeaturesEnum; RiscvInfo GetRiscvInfo(void); +int GetRiscvFeaturesEnumValue(const RiscvFeatures* features, RiscvFeaturesEnum value); +const char* GetRiscvFeaturesEnumName(RiscvFeaturesEnum); CPU_FEATURES_END_CPP_NAMESPACE diff --git a/src/impl_riscv_linux_or_android.c b/src/impl_riscv_linux.c similarity index 76% rename from src/impl_riscv_linux_or_android.c rename to src/impl_riscv_linux.c index 54140d6d..0df4aa97 100644 --- a/src/impl_riscv_linux_or_android.c +++ b/src/impl_riscv_linux.c @@ -14,8 +14,8 @@ #include "cpu_features_macros.h" -//#ifndef CPU_FEATURES_ARCH_RISCV -//#if defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) +#ifdef CPU_FEATURES_ARCH_RISCV +#if defined(CPU_FEATURES_OS_LINUX) #include "cpuinfo_riscv.h" @@ -43,11 +43,6 @@ // Implementation. //////////////////////////////////////////////////////////////////////////////// -/* - UARCH FOUND: - sifive,bullet0 -> Series 7 -*/ - #include "internal/stack_line_reader.h" #include "internal/filesystem.h" @@ -62,26 +57,31 @@ static bool HandleRiscVLine(const LineResult result, StringView key, value; if (CpuFeatures_StringView_GetAttributeKeyValue(line, &key, &value)) { if (CpuFeatures_StringView_IsEquals(key, str("isa"))) { - //CpuFeatures_StringView_IndexOf StringView tmp_sv; + value.ptr+=2; // ignore 'rv' prefix at the beginning + value.size-=2; for (size_t i = 0; i < RISCV_LAST_; ++i){ tmp_sv.ptr = kCpuInfoFlags[i]; tmp_sv.size = strlen(kCpuInfoFlags[i]); - kSetters[i](&info->features, - CpuFeatures_StringView_IndexOf(value, tmp_sv) > 1); - + CpuFeatures_StringView_IndexOf(value, tmp_sv) != -1); + } } if (CpuFeatures_StringView_IsEquals(key, str("uarch"))){ - //TODO + int separatorIdx = CpuFeatures_StringView_IndexOfChar(value, ','); + StringView vendor = {.ptr = value.ptr, .size = separatorIdx}; + StringView uarch = {.ptr = value.ptr + separatorIdx + 1, .size = value.size - separatorIdx - 1}; + + CpuFeatures_StringView_CopyString(vendor,info->vendor,sizeof(info->vendor)); + CpuFeatures_StringView_CopyString(uarch,info->uarch,sizeof(info->uarch)); } } return !result.eof; } static void FillProcCpuInfoData(RiscvInfo* const info) { - const int fd = CpuFeatures_OpenFile("/Users/danieleaffinita/Desktop/cpu/infocpu"); + const int fd = CpuFeatures_OpenFile("/proc/cpuinfo"); if (fd >= 0) { StackLineReader reader; StackLineReader_Initialize(&reader, fd); @@ -99,22 +99,13 @@ RiscvInfo GetRiscvInfo(void){ RiscvInfo info = kEmptyRiscvInfo; FillProcCpuInfoData(&info); - //just testing - printf("PRETEST\n"); - printf("32 -> %d\n",info.features.riscv32); - printf("64 -> %d\n",info.features.riscv64); - printf("128 -> %d\n",info.features.riscv128); - printf("a -> %d\n",info.features.a); - printf("c -> %d\n",info.features.c); - printf("d -> %d\n",info.features.d); - printf("e -> %d\n",info.features.e); - printf("f -> %d\n",info.features.f); - printf("i -> %d\n",info.features.i); - printf("m -> %d\n",info.features.m); - printf("v -> %d\n",info.features.v); - printf("q -> %d\n",info.features.q); - fflush(stdout); + if(!*info.vendor) + strcpy(info.vendor, "unknown_vendor"); + if(!*info.uarch) + strcpy(info.uarch, "unknown_uarch"); + + return info; } -//#endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) -//#endif // CPU_FEATURES_ARCH_RISCV \ No newline at end of file +#endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID) +#endif // CPU_FEATURES_ARCH_RISCV \ No newline at end of file diff --git a/src/utils/list_cpu_features.c b/src/utils/list_cpu_features.c index 4d7fe147..e19decfd 100644 --- a/src/utils/list_cpu_features.c +++ b/src/utils/list_cpu_features.c @@ -35,6 +35,8 @@ #include "cpuinfo_mips.h" #elif defined(CPU_FEATURES_ARCH_PPC) #include "cpuinfo_ppc.h" +#elif defined(CPU_FEATURES_ARCH_RISCV) +#include "cpuinfo_riscv.h" #endif // Design principles @@ -205,6 +207,9 @@ DEFINE_ADD_FLAGS(GetMipsFeaturesEnumValue, GetMipsFeaturesEnumName, #elif defined(CPU_FEATURES_ARCH_PPC) DEFINE_ADD_FLAGS(GetPPCFeaturesEnumValue, GetPPCFeaturesEnumName, PPCFeatures, PPC_LAST_) +#elif defined(CPU_FEATURES_ARCH_RISCV) +DEFINE_ADD_FLAGS(GetRiscvFeaturesEnumValue, GetRiscvFeaturesEnumName, RiscvFeatures, + RISCV_LAST_) #endif // Prints a json string with characters escaping. @@ -408,6 +413,12 @@ static Node* CreateTree(void) { AddMapEntry(root, "microarchitecture", CreateString(strings.type.base_platform)); AddFlags(root, &info.features); +#elif defined(CPU_FEATURES_ARCH_RISCV) + const RiscvInfo info = GetRiscvInfo(); + AddMapEntry(root, "arch", CreateString("risc-v")); + AddMapEntry(root, "vendor", CreateString(info.vendor)); + AddMapEntry(root, "microarchitecture", CreateString(info.uarch)); + AddFlags(root, &info.features); #endif return root; } diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index 8e8f72af..5e203ce9 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -89,3 +89,10 @@ if(PROCESSOR_IS_POWER) target_link_libraries(cpuinfo_ppc_test all_libraries) add_test(NAME cpuinfo_ppc_test COMMAND cpuinfo_ppc_test) endif() +##------------------------------------------------------------------------------ +## cpuinfo_riscv_test +if(PROCESSOR_IS_RISCV) + add_executable(cpuinfo_riscv_test cpuinfo_riscv_test.cc ../src/impl_riscv_linux.c) + target_link_libraries(cpuinfo_riscv_test all_libraries) + add_test(NAME cpuinfo_riscv_test COMMAND cpuinfo_riscv_test) +endif() diff --git a/test/cpuinfo_riscv_test.cc b/test/cpuinfo_riscv_test.cc new file mode 100644 index 00000000..20b3f2fe --- /dev/null +++ b/test/cpuinfo_riscv_test.cc @@ -0,0 +1,123 @@ +// Copyright 2022 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "cpuinfo_riscv.h" + +#include "filesystem_for_testing.h" +#include "gtest/gtest.h" +#include "hwcaps_for_testing.h" + +namespace cpu_features { +namespace { + +TEST(CpuinfoRiscvTest, LicheeFromCpuInfo) { + ResetHwcaps(); + auto& fs = GetEmptyFilesystem(); + fs.CreateFile("/proc/cpuinfo", R"(processor : 0 +hart : 0 +isa : rv64imafdc +mmu : sv39 +uarch : thead,c906)"); + const auto info = GetRiscvInfo(); + EXPECT_STREQ(info.uarch, "c906"); + EXPECT_STREQ(info.vendor, "thead"); + + EXPECT_FALSE(info.features.riscv32); + EXPECT_TRUE(info.features.riscv64); + EXPECT_FALSE(info.features.riscv128); + EXPECT_TRUE(info.features.a); + EXPECT_TRUE(info.features.c); + EXPECT_TRUE(info.features.d); + EXPECT_FALSE(info.features.e); + EXPECT_TRUE(info.features.f); + EXPECT_TRUE(info.features.i); + EXPECT_TRUE(info.features.m); + EXPECT_FALSE(info.features.q); + EXPECT_FALSE(info.features.v); +} + +TEST(CpuinfoRiscvTest, KendryteFromCpuInfo) { + ResetHwcaps(); + auto& fs = GetEmptyFilesystem(); + fs.CreateFile("/proc/cpuinfo", R"(hart : 0 +isa : rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0 +mmu : sv39 + +hart : 1 +isa : rv64i2p0m2p0a2p0f2p0d2p0c2p0xv5-0p0 +mmu : sv39)"); + const auto info = GetRiscvInfo(); + EXPECT_STREQ(info.uarch, "unknown_uarch"); + EXPECT_STREQ(info.vendor, "unknown_vendor"); + + EXPECT_FALSE(info.features.riscv32); + EXPECT_TRUE(info.features.riscv64); + EXPECT_FALSE(info.features.riscv128); + EXPECT_TRUE(info.features.a); + EXPECT_TRUE(info.features.c); + EXPECT_TRUE(info.features.d); + EXPECT_FALSE(info.features.e); + EXPECT_TRUE(info.features.f); + EXPECT_TRUE(info.features.i); + EXPECT_TRUE(info.features.m); + EXPECT_FALSE(info.features.q); + EXPECT_TRUE(info.features.v); +} + +TEST(CpuinfoRiscvTest, UnknownFromCpuInfo) { + ResetHwcaps(); + auto& fs = GetEmptyFilesystem(); + fs.CreateFile("/proc/cpuinfo", R"(processor : 0 +hart : 2 +isa : rv64imafdc +mmu : sv39 +uarch : sifive,bullet0 + +processor : 1 +hart : 1 +isa : rv64imafdc +mmu : sv39 +uarch : sifive,bullet0 + +processor : 2 +hart : 3 +isa : rv64imafdc +mmu : sv39 +uarch : sifive,bullet0 + +processor : 3 +hart : 4 +isa : rv64imafdc +mmu : sv39 +uarch : sifive,bullet0)"); + const auto info = GetRiscvInfo(); + EXPECT_STREQ(info.uarch, "bullet0"); + EXPECT_STREQ(info.vendor, "sifive"); + + EXPECT_FALSE(info.features.riscv32); + EXPECT_TRUE(info.features.riscv64); + EXPECT_FALSE(info.features.riscv128); + EXPECT_TRUE(info.features.a); + EXPECT_TRUE(info.features.c); + EXPECT_TRUE(info.features.d); + EXPECT_FALSE(info.features.e); + EXPECT_TRUE(info.features.f); + EXPECT_TRUE(info.features.i); + EXPECT_TRUE(info.features.m); + EXPECT_FALSE(info.features.q); + EXPECT_FALSE(info.features.v); +} + +} // namespace +} // namespace cpu_features \ No newline at end of file From f3bc4d75af8a0cd69546923bd5666115d8305cf8 Mon Sep 17 00:00:00 2001 From: Daniele Affinita Date: Thu, 18 Aug 2022 12:16:46 +0200 Subject: [PATCH 8/8] Update README.md --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 3e6a16b4..644a0515 100644 --- a/README.md +++ b/README.md @@ -172,14 +172,14 @@ flags : aes,avx,cx16,smx,sse4_1,sse4_2,ssse3 ## What's supported -| | x86³ | ARM | AArch64 | MIPS⁴ | POWER | -|---------|:----:|:-------:|:-------:|:-------:|:-------:| -| Android | yes² | yes¹ | yes¹ | yes¹ | N/A | -| iOS | N/A | not yet | not yet | N/A | N/A | -| Linux | yes² | yes¹ | yes¹ | yes¹ | yes¹ | -| MacOs | yes² | N/A | not yet | N/A | no | -| Windows | yes² | not yet | not yet | N/A | N/A | -| FreeBSD | yes² | not yet | not yet | not yet | not yet | +| | x86³ | ARM | AArch64 | MIPS⁴ | POWER | RISC-V | +|---------|:----:|:-------:|:-------:|:-------:|:-------:|:-------:| +| Android | yes² | yes¹ | yes¹ | yes¹ | N/A | N/A | +| iOS | N/A | not yet | not yet | N/A | N/A | N/A | +| Linux | yes² | yes¹ | yes¹ | yes¹ | yes¹ | yes¹ | +| MacOs | yes² | N/A | not yet | N/A | no | N/A | +| Windows | yes² | not yet | not yet | N/A | N/A | N/A | +| FreeBSD | yes² | not yet | not yet | not yet | not yet | N/A | 1. **Features revealed from Linux.** We gather data from several sources depending on availability: