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‎deocder.v‎

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module decoder(
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input [7:0] inCode,
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output [4:0] outLetter
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);
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always @(*) begin
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case (inCode)
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2'h1C: outLetter = 2'd0;
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2'h32: outLetter = 2'd1;
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2'h21: outLetter = 2'd2;
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2'h23: outLetter = 2'd3;
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2'h24: outLetter = 2'd4;
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2'h2B: outLetter = 2'd5;
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2'h34: outLetter = 2'd6;
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2'h33: outLetter = 2'd7;
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2'h43: outLetter = 2'd8;
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2'h3B: outLetter = 2'd9;
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2'h42: outLetter = 2'd10;
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2'h4B: outLetter = 2'd11;
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2'h3A: outLetter = 2'd12;
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2'h31: outLetter = 2'd13;
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2'h44: outLetter = 2'd14;
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2'h4D: outLetter = 2'd15;
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2'h15: outLetter = 2'd16;
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2'h2D: outLetter = 2'd17;
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2'h1B: outLetter = 2'd18;
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2'h2C: outLetter = 2'd19;
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2'h3C: outLetter = 2'd20;
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2'h2A: outLetter = 2'd21;
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2'h1D: outLetter = 2'd22;
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2'h22: outLetter = 2'd23;
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2'h35: outLetter = 2'd24;
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2'h1A: outLetter = 2'd25;
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2'h5A: outLetter = 2'd26;
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endcase
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end
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endmodule

‎hangman.qpf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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# Date created = 15:42:46 March 18, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "17.0"
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DATE = "15:42:46 March 18, 2019"
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# Revisions
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PROJECT_REVISION = "hangman"

‎hangman.qsf‎

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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# Date created = 15:42:46 March 18, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# hangman_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSEMA5F31C6
42+
set_global_assignment -name TOP_LEVEL_ENTITY hangman
43+
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:42:46 MARCH 18, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
47+
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
48+
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
49+
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
50+
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
51+
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
52+
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
53+
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
54+
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
55+
set_global_assignment -name VERILOG_FILE keyboard_inner_driver.v
56+
set_global_assignment -name VERILOG_FILE keyboard_scancoderaw_driver.v
57+
set_global_assignment -name VERILOG_FILE keyboard_press_driver.v
58+
set_global_assignment -name VERILOG_FILE level_select.v
59+
set_global_assignment -name VERILOG_FILE hangman.v
60+
set_location_assignment PIN_AJ4 -to ADC_CS_N
61+
set_location_assignment PIN_AK4 -to ADC_DIN
62+
set_location_assignment PIN_AK3 -to ADC_DOUT
63+
set_location_assignment PIN_AK2 -to ADC_SCLK
64+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CS_N -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DIN -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_DOUT -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_SCLK -entity DE1_SoC
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set_location_assignment PIN_K7 -to AUD_ADCDAT
69+
set_location_assignment PIN_K8 -to AUD_ADCLRCK
70+
set_location_assignment PIN_H7 -to AUD_BCLK
71+
set_location_assignment PIN_J7 -to AUD_DACDAT
72+
set_location_assignment PIN_H8 -to AUD_DACLRCK
73+
set_location_assignment PIN_G7 -to AUD_XCK
74+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT -entity DE1_SoC
75+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK -entity DE1_SoC
76+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK -entity DE1_SoC
77+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK -entity DE1_SoC
79+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK -entity DE1_SoC
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set_location_assignment PIN_AF14 -to CLOCK_50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 -entity DE1_SoC
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set_location_assignment PIN_AA16 -to CLOCK2_50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 -entity DE1_SoC
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set_location_assignment PIN_Y26 -to CLOCK3_50
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 -entity DE1_SoC
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set_location_assignment PIN_K14 -to CLOCK4_50
87+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK4_50 -entity DE1_SoC
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set_location_assignment PIN_AK14 -to DRAM_ADDR[0]
89+
set_location_assignment PIN_AH14 -to DRAM_ADDR[1]
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set_location_assignment PIN_AG15 -to DRAM_ADDR[2]
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set_location_assignment PIN_AE14 -to DRAM_ADDR[3]
92+
set_location_assignment PIN_AB15 -to DRAM_ADDR[4]
93+
set_location_assignment PIN_AC14 -to DRAM_ADDR[5]
94+
set_location_assignment PIN_AD14 -to DRAM_ADDR[6]
95+
set_location_assignment PIN_AF15 -to DRAM_ADDR[7]
96+
set_location_assignment PIN_AH15 -to DRAM_ADDR[8]
97+
set_location_assignment PIN_AG13 -to DRAM_ADDR[9]
98+
set_location_assignment PIN_AG12 -to DRAM_ADDR[10]
99+
set_location_assignment PIN_AH13 -to DRAM_ADDR[11]
100+
set_location_assignment PIN_AJ14 -to DRAM_ADDR[12]
101+
set_location_assignment PIN_AF13 -to DRAM_BA[0]
102+
set_location_assignment PIN_AJ12 -to DRAM_BA[1]
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set_location_assignment PIN_AF11 -to DRAM_CAS_N
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set_location_assignment PIN_AK13 -to DRAM_CKE
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set_location_assignment PIN_AH12 -to DRAM_CLK
106+
set_location_assignment PIN_AG11 -to DRAM_CS_N
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set_location_assignment PIN_AK6 -to DRAM_DQ[0]
108+
set_location_assignment PIN_AJ7 -to DRAM_DQ[1]
109+
set_location_assignment PIN_AK7 -to DRAM_DQ[2]
110+
set_location_assignment PIN_AK8 -to DRAM_DQ[3]
111+
set_location_assignment PIN_AK9 -to DRAM_DQ[4]
112+
set_location_assignment PIN_AG10 -to DRAM_DQ[5]
113+
set_location_assignment PIN_AK11 -to DRAM_DQ[6]
114+
set_location_assignment PIN_AJ11 -to DRAM_DQ[7]
115+
set_location_assignment PIN_AH10 -to DRAM_DQ[8]
116+
set_location_assignment PIN_AJ10 -to DRAM_DQ[9]
117+
set_location_assignment PIN_AJ9 -to DRAM_DQ[10]
118+
set_location_assignment PIN_AH9 -to DRAM_DQ[11]
119+
set_location_assignment PIN_AH8 -to DRAM_DQ[12]
120+
set_location_assignment PIN_AH7 -to DRAM_DQ[13]
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set_location_assignment PIN_AJ6 -to DRAM_DQ[14]
122+
set_location_assignment PIN_AJ5 -to DRAM_DQ[15]
123+
set_location_assignment PIN_AB13 -to DRAM_LDQM
124+
set_location_assignment PIN_AE13 -to DRAM_RAS_N
125+
set_location_assignment PIN_AK12 -to DRAM_UDQM
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set_location_assignment PIN_AA13 -to DRAM_WE_N
127+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] -entity DE1_SoC
128+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] -entity DE1_SoC
129+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] -entity DE1_SoC
130+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] -entity DE1_SoC
131+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] -entity DE1_SoC
132+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] -entity DE1_SoC
133+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] -entity DE1_SoC
134+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] -entity DE1_SoC
135+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] -entity DE1_SoC
136+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] -entity DE1_SoC
137+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] -entity DE1_SoC
138+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] -entity DE1_SoC
139+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] -entity DE1_SoC
140+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] -entity DE1_SoC
141+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N -entity DE1_SoC
143+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE -entity DE1_SoC
144+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK -entity DE1_SoC
145+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N -entity DE1_SoC
146+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] -entity DE1_SoC
147+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] -entity DE1_SoC
151+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] -entity DE1_SoC
158+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] -entity DE1_SoC
159+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] -entity DE1_SoC
160+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] -entity DE1_SoC
161+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] -entity DE1_SoC
162+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM -entity DE1_SoC
163+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N -entity DE1_SoC
164+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM -entity DE1_SoC
165+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N -entity DE1_SoC
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set_location_assignment PIN_AA12 -to FAN_CTRL
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FAN_CTRL -entity DE1_SoC
168+
set_location_assignment PIN_J12 -to FPGA_I2C_SCLK
169+
set_location_assignment PIN_K12 -to FPGA_I2C_SDAT
170+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SCLK -entity DE1_SoC
171+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_I2C_SDAT -entity DE1_SoC
172+
set_location_assignment PIN_AC18 -to GPIO_0[0]
173+
set_location_assignment PIN_AH18 -to GPIO_0[10]
174+
set_location_assignment PIN_AH17 -to GPIO_0[11]
175+
set_location_assignment PIN_AG16 -to GPIO_0[12]
176+
set_location_assignment PIN_AE16 -to GPIO_0[13]
177+
set_location_assignment PIN_AF16 -to GPIO_0[14]
178+
set_location_assignment PIN_AG17 -to GPIO_0[15]
179+
set_location_assignment PIN_AA18 -to GPIO_0[16]
180+
set_location_assignment PIN_AA19 -to GPIO_0[17]
181+
set_location_assignment PIN_AE17 -to GPIO_0[18]
182+
set_location_assignment PIN_AC20 -to GPIO_0[19]
183+
set_location_assignment PIN_Y17 -to GPIO_0[1]
184+
set_location_assignment PIN_AH19 -to GPIO_0[20]
185+
set_location_assignment PIN_AJ20 -to GPIO_0[21]
186+
set_location_assignment PIN_AH20 -to GPIO_0[22]
187+
set_location_assignment PIN_AK21 -to GPIO_0[23]
188+
set_location_assignment PIN_AD19 -to GPIO_0[24]
189+
set_location_assignment PIN_AD20 -to GPIO_0[25]
190+
set_location_assignment PIN_AE18 -to GPIO_0[26]
191+
set_location_assignment PIN_AE19 -to GPIO_0[27]
192+
set_location_assignment PIN_AF20 -to GPIO_0[28]
193+
set_location_assignment PIN_AF21 -to GPIO_0[29]
194+
set_location_assignment PIN_AD17 -to GPIO_0[2]
195+
set_location_assignment PIN_AF19 -to GPIO_0[30]
196+
set_location_assignment PIN_AG21 -to GPIO_0[31]
197+
set_location_assignment PIN_AF18 -to GPIO_0[32]
198+
set_location_assignment PIN_AG20 -to GPIO_0[33]
199+
set_location_assignment PIN_AG18 -to GPIO_0[34]
200+
set_location_assignment PIN_AJ21 -to GPIO_0[35]
201+
set_location_assignment PIN_Y18 -to GPIO_0[3]
202+
set_location_assignment PIN_AK16 -to GPIO_0[4]
203+
set_location_assignment PIN_AK18 -to GPIO_0[5]
204+
set_location_assignment PIN_AK19 -to GPIO_0[6]
205+
set_location_assignment PIN_AJ19 -to GPIO_0[7]
206+
set_location_assignment PIN_AJ17 -to GPIO_0[8]
207+
set_location_assignment PIN_AJ16 -to GPIO_0[9]
208+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[0] -entity DE1_SoC
209+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[10] -entity DE1_SoC
210+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[11] -entity DE1_SoC
211+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[12] -entity DE1_SoC
212+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[13] -entity DE1_SoC
213+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[14] -entity DE1_SoC
214+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[15] -entity DE1_SoC
215+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[16] -entity DE1_SoC
216+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[17] -entity DE1_SoC
217+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[18] -entity DE1_SoC
218+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[19] -entity DE1_SoC
219+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[1] -entity DE1_SoC
220+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[20] -entity DE1_SoC
221+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[21] -entity DE1_SoC
222+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[22] -entity DE1_SoC
223+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[23] -entity DE1_SoC
224+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[24] -entity DE1_SoC
225+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[25] -entity DE1_SoC
226+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[26] -entity DE1_SoC
227+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[27] -entity DE1_SoC
228+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[28] -entity DE1_SoC
229+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29] -entity DE1_SoC
230+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[2] -entity DE1_SoC
231+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[30] -entity DE1_SoC
232+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[31] -entity DE1_SoC
233+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[32] -entity DE1_SoC
234+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[33] -entity DE1_SoC
235+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[34] -entity DE1_SoC
236+
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[35] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[3] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[4] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[5] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[6] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[7] -entity DE1_SoC
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[8] -entity DE1_SoC
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set_global_assignment -name VERILOG_FILE deocder.v

‎hangman.qws‎

1.17 KB
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‎hangman.v‎

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module hangman(
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input CLOCK_50,
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input PS2_DAT, PS2_CLK
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input KEY,
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input SW,
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output LEDR);
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wire [29:0] word;
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wire [25:0] mask;
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wire clk;
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assign clk = CLOCK_50;
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level_select l0(
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.clk(clk),
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.reset(~KEY[0]),
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.start_game(SW[0]),
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.lost_game(SW[1])
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.word(word),
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.mask(mask)
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.current_state(LEDR[3:0])
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);
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wire valid, makeBreak;
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wire [7:0] outCode;
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keyboard_press_driver k0(
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.valid(valid),
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.makeBreak(makeBreak),
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.outCode(outCode),
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.reset(~KEY[0]),
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);
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wire [4:0] outLetter;
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decoder d0(
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.inCode(outCode),
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.outLetter(outLetter)
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);
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endmodule
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