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zhouyiw2
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i don't know what these things are
1 parent cc2aa00 commit 3b2bdcb

16 files changed

+1778
-10
lines changed

DE1_SoC.qsf

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black.mif

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WIDTH=3;
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DEPTH=19200;
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ADDRESS_RADIX=UNS;
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DATA_RADIX=UNS;
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CONTENT BEGIN
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[0..19199] : 0;
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END;

greybox_tmp/cbx_args.txt

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CLOCK_ENABLE_INPUT_A=BYPASS
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CLOCK_ENABLE_OUTPUT_A=BYPASS
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INIT_FILE=./init_ram.mif
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INTENDED_DEVICE_FAMILY="Cyclone V"
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NUMWORDS_A=16
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OPERATION_MODE=SINGLE_PORT
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OUTDATA_ACLR_A=NONE
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OUTDATA_REG_A=UNREGISTERED
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POWER_UP_UNINITIALIZED=FALSE
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READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
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WIDTHAD_A=4
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WIDTH_A=56
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WIDTH_BYTEENA_A=1
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DEVICE_FAMILY="Cyclone V"
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address_a
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clock0
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q_a

hangman.qpf

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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# Date created = 15:13:25 March 25, 2019
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "17.0"
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DATE = "15:13:25 March 25, 2019"
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# Revisions
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PROJECT_REVISION = "hangman"

hangman.qsf

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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel MegaCore Function License Agreement, or other
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# applicable license agreement, including, without limitation,
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# that your use is for the sole purpose of programming logic
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# devices manufactured by Intel and sold by Intel or its
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# authorized distributors. Please refer to the applicable
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# agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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# Date created = 15:13:25 March 25, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# hangman_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone V"
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set_global_assignment -name DEVICE 5CSEMA5F31C6
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set_global_assignment -name TOP_LEVEL_ENTITY hangman
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:13:25 MARCH 25, 2019"
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set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
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set_global_assignment -name VERILOG_FILE keyboard_inner_driver.v
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set_global_assignment -name VERILOG_FILE keyboard_scancoderaw_driver.v
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set_global_assignment -name VERILOG_FILE hangman.v
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set_global_assignment -name VERILOG_FILE hex_decoder.v
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set_global_assignment -name VERILOG_FILE decoder.v
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set_global_assignment -name VERILOG_FILE game_state.v
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set_global_assignment -name VERILOG_FILE level_select.v
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set_global_assignment -name VERILOG_FILE keyboard_press_driver.v
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name QIP_FILE ram.qip

hangman.qws

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init_ram.mif

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CONTENT
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BEGIN
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0: 00101011100011100101011001001111111110111101011110101111;
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1: 00001100111001101001001110111011111110111101111010111110;
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2: 01101011110010010101011000010111111011111010011111100111;
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3: 01111101011010010000101011010011111001110011111111111111;
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4: 00001011001011100001110011001110101110111111011111111110;
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5: 00100100100100110110001011001011110111011111111011100111;
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6: 01101001010110101111100101100110111111011010111111101111;
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7: 00101011100001101111001000010111111111111001111111100011;
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8: 10011001010110000101000111010011111100111111011111101011;
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9: 10011010010011101110000010110011111110111101011010111110;
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0: 00101011100011100101011001001111111110111101011110101111;
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1: 00001100111001101001001110111011111110111101111010111110;
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2: 01101011110010010101011000010111111011111010011111100111;
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3: 01111101011010010000101011010011111001110011111111111111;
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4: 00001011001011100001110011001110101110111111011111111110;
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5: 00100100100100110110001011001011110111011111111011100111;
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6: 01101001010110101111100101100110111111011010111111101111;
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7: 00101011100001101111001000010111111111111001111111100011;
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8: 10011001010110000101000111010011111100111111011111101011;
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9: 10011010010011101110000010110011111110111101011010111110;
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END;
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