1+ # -------------------------------------------------------------------------- #
2+ #
3+ # Copyright (C) 2017 Intel Corporation. All rights reserved.
4+ # Your use of Intel Corporation's design tools, logic functions
5+ # and other software and tools, and its AMPP partner logic
6+ # functions, and any output files from any of the foregoing
7+ # (including device programming or simulation files), and any
8+ # associated documentation or information are expressly subject
9+ # to the terms and conditions of the Intel Program License
10+ # Subscription Agreement, the Intel Quartus Prime License Agreement,
11+ # the Intel MegaCore Function License Agreement, or other
12+ # applicable license agreement, including, without limitation,
13+ # that your use is for the sole purpose of programming logic
14+ # devices manufactured by Intel and sold by Intel or its
15+ # authorized distributors. Please refer to the applicable
16+ # agreement for further details.
17+ #
18+ # -------------------------------------------------------------------------- #
19+ #
20+ # Quartus Prime
21+ # Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition
22+ # Date created = 15:13:25 March 25, 2019
23+ #
24+ # -------------------------------------------------------------------------- #
25+ #
26+ # Notes:
27+ #
28+ # 1) The default values for assignments are stored in the file:
29+ # hangman_assignment_defaults.qdf
30+ # If this file doesn't exist, see file:
31+ # assignment_defaults.qdf
32+ #
33+ # 2) Altera recommends that you do not modify this file. This
34+ # file is updated automatically by the Quartus Prime software
35+ # and any changes you make may be lost or overwritten.
36+ #
37+ # -------------------------------------------------------------------------- #
38+
39+
40+ set_global_assignment -name FAMILY "Cyclone V"
41+ set_global_assignment -name DEVICE 5CSEMA5F31C6
42+ set_global_assignment -name TOP_LEVEL_ENTITY hangman
43+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
44+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:13:25 MARCH 25, 2019"
45+ set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition"
46+ set_global_assignment -name VERILOG_FILE keyboard_inner_driver.v
47+ set_global_assignment -name VERILOG_FILE keyboard_scancoderaw_driver.v
48+ set_global_assignment -name VERILOG_FILE hangman.v
49+ set_global_assignment -name VERILOG_FILE hex_decoder.v
50+ set_global_assignment -name VERILOG_FILE decoder.v
51+ set_global_assignment -name VERILOG_FILE game_state.v
52+ set_global_assignment -name VERILOG_FILE level_select.v
53+ set_global_assignment -name VERILOG_FILE keyboard_press_driver.v
54+ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
55+ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
56+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
57+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
58+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
59+ set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
60+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
61+ set_global_assignment -name QIP_FILE ram.qip
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