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zhouyiw2
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add ram files
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‎init_ram.mif‎

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WIDTH = 56;
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DEPTH = 16;
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ADDRESS_RADIX = HEX;
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DATA_RADIX = BIN;
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CONTENT
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BEGIN
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0: 00101011100011100101011001001111111110111101011110101111;
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1: 00001100111001101001001110111011111110111101111010111110;
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2: 01101011110010010101011000010111111011111010011111100111;
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3: 01111101011010010000101011010011111001110011111111111111;
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4: 00001011001011100001110011001110101110111111011111111110;
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5: 00100100100100110110001011001011110111011111111011100111;
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6: 01101001010110101111100101100110111111011010111111101111;
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7: 00101011100001101111001000010111111111111001111111100011;
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8: 10011001010110000101000111010011111100111111011111101011;
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9: 10011010010011101110000010110011111110111101011010111110;
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END;

‎ram.qip‎

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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "17.0"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram.v"]

‎ram.v‎

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// megafunction wizard: %RAM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: ram.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2017 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Intel and sold by Intel or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module ram (
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address,
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clock,
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data,
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wren,
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q);
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input [3:0] address;
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input clock;
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input [55:0] data;
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input wren;
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output [55:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [55:0] sub_wire0;
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wire [55:0] q = sub_wire0[55:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_output_a = "BYPASS",
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altsyncram_component.init_file = "init_ram.mif",
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altsyncram_component.intended_device_family = "Cyclone V",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 16,
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altsyncram_component.operation_mode = "SINGLE_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 4,
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altsyncram_component.width_a = 56,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrData NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: Clken NUMERIC "0"
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// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING "init_ram.mif"
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegData NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
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// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "4"
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// Retrieval info: PRIVATE: WidthData NUMERIC "56"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "init_ram.mif"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "56"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL "address[3..0]"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 56 0 INPUT NODEFVAL "data[55..0]"
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// Retrieval info: USED_PORT: q 0 0 56 0 OUTPUT NODEFVAL "q[55..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
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// Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 56 0 data 0 0 56 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 56 0 @q_a 0 0 56 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf

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