Skip to content

Commit 3c6059d

Browse files
scuciureandbogdan
scuciurean
authored and
dbogdan
committed
arch: arm: boot: Add Pulsar example dts
Add devicetrees for 4 different types of pulsar eval boards. Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
1 parent bf5c2a4 commit 3c6059d

File tree

4 files changed

+416
-0
lines changed

4 files changed

+416
-0
lines changed

‎arch/arm/boot/dts/zynq-coraz7s-ad7687-pmdz.dts‎

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Analog Devices AD7687
4+
* https://www.analog.com/en/products/ad7687.html
5+
*
6+
* hdl_project: <pulsar_adc_pmdz/coraz7s>
7+
* board_revision: <A>
8+
*
9+
* Copyright (C) 2022 Analog Devices Inc.
10+
*/
11+
/dts-v1/;
12+
#include "zynq-coraz7s.dtsi"
13+
#include <dt-bindings/interrupt-controller/irq.h>
14+
#include <dt-bindings/gpio/gpio.h>
15+
16+
/ {
17+
vref: regulator-vref {
18+
compatible = "regulator-fixed";
19+
regulator-name = "fixed-supply";
20+
regulator-min-microvolt = <5000000>;
21+
regulator-max-microvolt = <5000000>;
22+
regulator-always-on;
23+
};
24+
};
25+
26+
&fpga_axi {
27+
28+
adc_trigger: pwm@0x44b00000 {
29+
compatible = "adi,axi-pwmgen";
30+
reg = <0x44b00000 0x1000>;
31+
label = "adc_conversion_trigger";
32+
#pwm-cells = <2>;
33+
clocks = <&spi_clk>;
34+
};
35+
36+
spi_engine: spi@44a00000 {
37+
compatible = "adi,axi-spi-engine-1.00.a";
38+
reg = <0x44a00000 0x10000>;
39+
interrupt-parent = <&intc>;
40+
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
41+
clocks = <&clkc 15 &spi_clk>;
42+
clock-names = "s_axi_aclk", "spi_clk";
43+
num-cs = <1>;
44+
45+
#address-cells = <0x1>;
46+
#size-cells = <0x0>;
47+
48+
adc@0 {
49+
#address-cells = <1>;
50+
#size-cells = <0>;
51+
compatible = "adi,pulsar,ad7687";
52+
reg = <0>;
53+
spi-max-frequency = <80000000>;
54+
clocks = <&spi_clk>;
55+
clock-names = "ref_clk";
56+
dmas = <&rx_dma 0>;
57+
dma-names = "rx";
58+
pwms = <&adc_trigger 0 0>;
59+
pwm-names = "cnv";
60+
vref-supply = <&vref>;
61+
channel@0 {
62+
reg = <0>;
63+
diff-channels = <0 1>;
64+
};
65+
};
66+
};
67+
68+
rx_dma: rx-dmac@44a30000 {
69+
compatible = "adi,axi-dmac-1.00.a";
70+
reg = <0x44a30000 0x1000>;
71+
#dma-cells = <1>;
72+
interrupt-parent = <&intc>;
73+
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
74+
clocks = <&clkc 16>;
75+
76+
adi,channels {
77+
#size-cells = <0>;
78+
#address-cells = <1>;
79+
80+
dma-channel@0 {
81+
reg = <0>;
82+
adi,source-bus-width = <32>;
83+
adi,source-bus-type = <1>;
84+
adi,destination-bus-width = <64>;
85+
adi,destination-bus-type = <0>;
86+
};
87+
};
88+
};
89+
90+
spi_clk: axi-clkgen@0x44a70000 {
91+
compatible = "adi,axi-clkgen-2.00.a";
92+
reg = <0x44a70000 0x10000>;
93+
#clock-cells = <0>;
94+
clocks = <&clkc 15>, <&clkc 15>;
95+
clock-names = "s_axi_aclk", "clkin1";
96+
clock-output-names = "spi_clk";
97+
};
98+
};

‎arch/arm/boot/dts/zynq-coraz7s-ad7689-ardz.dts‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Analog Devices AD7689
4+
* https://www.analog.com/en/products/ad7689.html
5+
*
6+
* hdl_project: <pulsar_adc_pmdz/coraz7s>
7+
* board_revision: <A>
8+
*
9+
* Copyright (C) 2022 Analog Devices Inc.
10+
*/
11+
/dts-v1/;
12+
#include "zynq-coraz7s.dtsi"
13+
#include <dt-bindings/interrupt-controller/irq.h>
14+
#include <dt-bindings/gpio/gpio.h>
15+
16+
/ {
17+
vref: regulator-vref {
18+
compatible = "regulator-fixed";
19+
regulator-name = "fixed-supply";
20+
regulator-min-microvolt = <4096000>;
21+
regulator-max-microvolt = <4096000>;
22+
regulator-always-on;
23+
};
24+
};
25+
26+
&fpga_axi {
27+
28+
adc_trigger: pwm@0x44b00000 {
29+
compatible = "adi,axi-pwmgen";
30+
reg = <0x44b00000 0x1000>;
31+
label = "adc_conversion_trigger";
32+
#pwm-cells = <2>;
33+
clocks = <&spi_clk>;
34+
};
35+
36+
spi_engine: spi@44a00000 {
37+
compatible = "adi,axi-spi-engine-1.00.a";
38+
reg = <0x44a00000 0x10000>;
39+
interrupt-parent = <&intc>;
40+
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
41+
clocks = <&clkc 15 &spi_clk>;
42+
clock-names = "s_axi_aclk", "spi_clk";
43+
num-cs = <1>;
44+
45+
#address-cells = <0x1>;
46+
#size-cells = <0x0>;
47+
48+
adc@0 {
49+
#address-cells = <1>;
50+
#size-cells = <0>;
51+
compatible = "adi,pulsar,ad7689";
52+
reg = <0>;
53+
spi-max-frequency = <80000000>;
54+
clocks = <&spi_clk>;
55+
clock-names = "ref_clk";
56+
dmas = <&rx_dma 0>;
57+
dma-names = "rx";
58+
pwms = <&adc_trigger 0 0>;
59+
pwm-names = "cnv";
60+
vref-supply = <&vref>;
61+
channel@0 {
62+
reg = <0>;
63+
diff-channels = <0 1>;
64+
};
65+
channel@1 {
66+
reg = <1>;
67+
diff-channels = <2 3>;
68+
};
69+
channel@2 {
70+
reg = <2>;
71+
adi,single-channel = <4>;
72+
};
73+
channel@3 {
74+
reg = <3>;
75+
adi,single-channel = <5>;
76+
};
77+
channel@4 {
78+
reg = <4>;
79+
adi,single-channel = <6>;
80+
};
81+
channel@5 {
82+
reg = <5>;
83+
adi,single-channel = <7>;
84+
};
85+
channel@6 {
86+
reg = <6>;
87+
adi,temp-sensor;
88+
};
89+
};
90+
};
91+
92+
rx_dma: rx-dmac@44a30000 {
93+
compatible = "adi,axi-dmac-1.00.a";
94+
reg = <0x44a30000 0x1000>;
95+
#dma-cells = <1>;
96+
interrupt-parent = <&intc>;
97+
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
98+
clocks = <&clkc 16>;
99+
100+
adi,channels {
101+
#size-cells = <0>;
102+
#address-cells = <1>;
103+
104+
dma-channel@0 {
105+
reg = <0>;
106+
adi,source-bus-width = <32>;
107+
adi,source-bus-type = <1>;
108+
adi,destination-bus-width = <64>;
109+
adi,destination-bus-type = <0>;
110+
};
111+
};
112+
};
113+
114+
spi_clk: axi-clkgen@0x44a70000 {
115+
compatible = "adi,axi-clkgen-2.00.a";
116+
reg = <0x44a70000 0x10000>;
117+
#clock-cells = <0>;
118+
clocks = <&clkc 15>, <&clkc 15>;
119+
clock-names = "s_axi_aclk", "clkin1";
120+
clock-output-names = "spi_clk";
121+
};
122+
};

‎arch/arm/boot/dts/zynq-coraz7s-ad7946.dts‎

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,98 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* Analog Devices AD7946
4+
* https://www.analog.com/en/products/ad7946.html
5+
*
6+
* hdl_project: <pulsar_adc_pmdz/coraz7s>
7+
* board_revision: <A>
8+
*
9+
* Copyright (C) 2022 Analog Devices Inc.
10+
*/
11+
/dts-v1/;
12+
#include "zynq-coraz7s.dtsi"
13+
#include <dt-bindings/interrupt-controller/irq.h>
14+
#include <dt-bindings/gpio/gpio.h>
15+
16+
/ {
17+
vref: regulator-vref {
18+
compatible = "regulator-fixed";
19+
regulator-name = "fixed-supply";
20+
regulator-min-microvolt = <4096000>;
21+
regulator-max-microvolt = <4096000>;
22+
regulator-always-on;
23+
};
24+
};
25+
26+
&fpga_axi {
27+
28+
adc_trigger: pwm@0x44b00000 {
29+
compatible = "adi,axi-pwmgen";
30+
reg = <0x44b00000 0x1000>;
31+
label = "adc_conversion_trigger";
32+
#pwm-cells = <2>;
33+
clocks = <&spi_clk>;
34+
};
35+
36+
spi_engine: spi@44a00000 {
37+
compatible = "adi,axi-spi-engine-1.00.a";
38+
reg = <0x44a00000 0x10000>;
39+
interrupt-parent = <&intc>;
40+
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
41+
clocks = <&clkc 15 &spi_clk>;
42+
clock-names = "s_axi_aclk", "spi_clk";
43+
num-cs = <1>;
44+
45+
#address-cells = <0x1>;
46+
#size-cells = <0x0>;
47+
48+
adc@0 {
49+
#address-cells = <1>;
50+
#size-cells = <0>;
51+
compatible = "adi,pulsar,ad7946";
52+
reg = <0>;
53+
spi-max-frequency = <80000000>;
54+
clocks = <&spi_clk>;
55+
clock-names = "ref_clk";
56+
dmas = <&rx_dma 0>;
57+
dma-names = "rx";
58+
pwms = <&adc_trigger 0 0>;
59+
pwm-names = "cnv";
60+
vref-supply = <&vref>;
61+
channel@0 {
62+
reg = <0>;
63+
diff-channels = <0 1>;
64+
};
65+
};
66+
};
67+
68+
rx_dma: rx-dmac@44a30000 {
69+
compatible = "adi,axi-dmac-1.00.a";
70+
reg = <0x44a30000 0x1000>;
71+
#dma-cells = <1>;
72+
interrupt-parent = <&intc>;
73+
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
74+
clocks = <&clkc 16>;
75+
76+
adi,channels {
77+
#size-cells = <0>;
78+
#address-cells = <1>;
79+
80+
dma-channel@0 {
81+
reg = <0>;
82+
adi,source-bus-width = <32>;
83+
adi,source-bus-type = <1>;
84+
adi,destination-bus-width = <64>;
85+
adi,destination-bus-type = <0>;
86+
};
87+
};
88+
};
89+
90+
spi_clk: axi-clkgen@0x44a70000 {
91+
compatible = "adi,axi-clkgen-2.00.a";
92+
reg = <0x44a70000 0x10000>;
93+
#clock-cells = <0>;
94+
clocks = <&clkc 15>, <&clkc 15>;
95+
clock-names = "s_axi_aclk", "clkin1";
96+
clock-output-names = "spi_clk";
97+
};
98+
};

0 commit comments

Comments
 (0)