-
Notifications
You must be signed in to change notification settings - Fork 11
Expand file tree
/
Copy pathhalfword_transfer.asm
More file actions
229 lines (184 loc) · 4.19 KB
/
halfword_transfer.asm
File metadata and controls
229 lines (184 loc) · 4.19 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
halfword_transfer:
; Tests for the halfword data transfer instruction
mem equ r11
mov mem, MEM_IWRAM
add mem, 0x1500
t400:
; ARM 8: Store halfword
mvn r0, 0
strh r0, [mem]
lsr r0, 16
ldr r1, [mem]
cmp r1, r0
bne f400
add mem, 32
b t401
f400:
m_exit 400
t401:
; ARM 8: Load halfword
mvn r0, 0
str r0, [mem]
lsr r0, 16
ldrh r1, [mem]
cmp r1, r0
bne f401
add mem, 32
b t402
f401:
m_exit 401
t402:
; ARM 8: Load unsigned halfword
mov r0, 0x7F00
strh r0, [mem]
ldrsh r1, [mem]
cmp r1, r0
bne f402
add mem, 32
b t403
f402:
m_exit 402
t403:
; ARM 8: Load signed halfword
mov r0, 0xFF00
strh r0, [mem]
mvn r0, 0xFF
ldrsh r1, [mem]
cmp r1, r0
bne f403
add mem, 32
b t404
f403:
m_exit 403
t404:
; ARM 8: Load unsigned byte
mov r0, 0x7F
strb r0, [mem]
ldrsb r1, [mem]
cmp r1, r0
bne f404
add mem, 32
b t405
f404:
m_exit 404
t405:
; ARM 8: Load signed byte
mov r0, 0xFF
strb r0, [mem]
mvn r0, 0
ldrsb r1, [mem]
cmp r1, r0
bne f405
add mem, 32
b t406
f405:
m_exit 405
t406:
; ARM 8: Indexing, writeback and offset types
mov r0, 32
mov r1, 4
mov r2, mem
strh r0, [r2], 4
ldrh r3, [r2, -r1]!
cmp r3, r0
bne f406
cmp r2, mem
bne f406
add mem, 32
b t407
f406:
m_exit 406
t407:
; ARM 8: Aligned store halfword
mov r0, 32
strh r0, [mem, 1]
ldrh r1, [mem]
cmp r1, r0
bne f407
add mem, 32
b t408
f407:
m_exit 407
t408:
; ARM 8: Misaligned load halfword (rotated)
mov r0, 32
strh r0, [mem]
ldrh r1, [mem, 1]
cmp r1, r0, ror 8
bne f408
add mem, 32
b t409
f408:
m_exit 408
t409:
; ARM 8: Misaligned load signed halfword
mov r0, 0xFF00
strh r0, [mem]
mvn r0, 0
ldrsh r1, [mem, 1]
cmp r1, r0
bne f409
add mem, 32
b t410
f409:
m_exit 409
t410:
; ARM 8: Store writeback same register
mov r0, mem
dw 0xE1E000B4 ; strh r0, [r0, 4]!
add r1, mem, 4
cmp r1, r0
bne f410
ldr r1, [r0]
mov r2, mem
bic r2, 0xFF000000
bic r2, 0xFF0000
cmp r2, r1
bne f410
add mem, 32
b t411
f410:
m_exit 410
t411:
; ARM 8: Store writeback same register
mov r0, mem
dw 0xE0C000B4 ; strh r0, [r0], 4
sub r0, 4
cmp r0, mem
bne f411
ldr r1, [r0]
mov r2, mem
bic r2, 0xFF000000
bic r2, 0xFF0000
cmp r2, r1
bne f411
add mem, 32
b t412
f411:
m_exit 411
t412:
; ARM 8: Load writeback same register
mov r0, mem
mov r1, 32
str r1, [r0], -4
dw 0xE1F000B4 ; ldrh r0, [r0, 4]!
cmp r0, 32
bne f412
add mem, 32
b t413
f412:
m_exit 412
t413:
; ARM 8: Load writeback same register
mov r0, mem
mov r1, 32
strh r1, [r0]
dw 0xE0D000B4 ; ldrh r0, [r0], 4
cmp r0, 32
bne f413
add mem, 32
b halfword_transfer_passed
f413:
m_exit 413
halfword_transfer_passed:
restore mem