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base repository: qemu/qemu
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head repository: linumiz/qemu-tricore
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compare: release/ifx/tricore-1.0
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  • 9 commits
  • 48 files changed
  • 1 contributor

Commits on Apr 17, 2026

  1. hw/intc: add TriCore interrupt router 

    Add the TriCore interrupt router (tricore_ir) device model. This
implements the Service Request Node (SRN) based interrupt mechanism
used by both TC3x and TC4x SoC families.

Each SRN contains a Service Request Control Register (SRC) with
priority number (SRPN), service provider (TOS), enable (SRE),
request (SRR), and clear (CLRR) fields. The router evaluates all
enabled SRNs and drives the highest-priority pending interrupt to
the CPU via ICR.PIPN/CCPN comparison.

TC3x and TC4x use different SRC register bit layouts, handled via
feature-flag dispatch.

Originally-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
    @parthitce
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  2. hw/char: add ASCLIN UART controller for TriCore 

    Add the ASCLIN (Asynchronous/Synchronous Communication Line)
peripheral model for TriCore SoCs. Supports ASC (UART) mode with
TX/RX FIFO, interrupt-driven operation, and flag register handling.

TC3x and TC4x use different register offset maps and flag register
layouts, handled via SoC-type property dispatch.

Originally-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Bastian Koppelmann <bastian-qemu@tensor.gmbh>
Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
    @parthitce
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  3. hw/timer: add System Timer Module for TriCore 

    Add the STM (System Timer Module) peripheral model. Implements a
free-running 64-bit counter with compare match interrupt generation
via CMP0/CMP1 comparators and CMCON mask register.

Supports both TC3x and TC4x clock configurations with dynamic
frequency update from the SCU/clock subsystem.

Originally-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
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  4. hw/tricore: add SCU, virt device, and SFR helpers 

    Add three common TriCore peripheral support devices:

- System Control Unit (SCU): clock configuration registers (CCUCONx),
  reset control, watchdog, and PMCSR power management with CPU idle/
  halt support for TC3x.

- Paravirtualization device (tricore_virt): provides a simple exit
  mechanism for test and semihosting use.

- SFR helper (tricore_sfr): stub register region for CPU-level
  special function registers accessed via memory-mapped I/O.

Also adds tc_soc.h with common SoC memory layout constants shared
across TC27XD, TC39XB, and TC4DX SoC implementations.

Originally-by: David Brenken <david.brenken@efs-auto.de>
Originally-by: Georg Hofstetter <bastian-qemu@tensor.gmbh>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
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  5. target/tricore: extend CPU models and ISA for TC1.6.2/TC1.8 

    Extend the TriCore target to support ISA TC1.6.2P (TC3x family) and
TC1.8P (TC4x family) instruction sets and CPU models.

CPU models and initialization:
- Add tc37x, tc39x CPU types for TC3x (ISA 1.6.2)
- Add tc4x CPU type for TC4x (ISA 1.8)
- Each model sets appropriate feature flags and initial register
  values (BTV, BIV, ISP, PSW)
- Add TRICORE_FEATURE_14/161/162/18 feature flags

Instruction decode (translate.c):
- Add TC1.8 opcodes: CMPSWAP.W, SWAPMSK.W, CRC32B.W, CRC32L.W,
  POPCNT.W, SHUFFLE, CLO.B, CLO.H, CLS.B, CLS.H, WAIT, RFH
- Add 64-bit division (DIV64/DIV64U) distinguished via n-field
- Fix MFCR/MTCR to use TCG globals for ICR and PCXI
- Add PCON/DCON CSFR handling with auto-clear PCON1.PCINV
- Fix DISABLE instruction to emit tcg_gen_br after helper call

Interrupt and trap handling (cpu_helper.c, op_helper.c):
- New cpu_helper.c with tricore_cpu_do_interrupt implementing
  proper PIPN > CCPN priority check
- PCXI save uses bitwise OR for ul_mask field
- WAIT helper stores pc_succ_insn (not pc_next) and sets
  pmcsr_sleep_pending flag for deferred halt
- ISYNC helper checks pmcsr_sleep_pending for halt entry

FPU (fpu_helper.c):
- Add double-precision FPU helpers for TC1.8: ADD.D, SUB.D,
  MUL.D, DIV.D, CMP.D, FTOD, DTOF, DTOI, DTOU, ITOD, UTOD,
  FTOIZ, DTOLZ, and MADD/MSUB.D variants
- Implement packed arithmetic helpers

Debug and semihosting:
- Add debug-semihosting.c for TriCore semihosting support

Originally-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
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  6. hw/tricore: add TC4x clock device and CPU SFR wrapper 

    Add two TC4x-specific support devices:

- TC4x clock device (tc4x_clock): models the TC4x clock control
  unit with PLL0/PLL1/PLL2, CCUCONx divider registers, and clock
  tree propagation. Accepts an external oscillator (fosc) clock
  input and derives fSPB, fSTM, fBBB, fCPU frequencies.

- TC4x CPU wrapper (tc4x_cpu): encapsulates per-core resources
  for TC4x SoCs including CPU instance, per-core STM timer, local
  interrupt router (SRC nodes), and stub MMIO regions for SPROT
  and CPU SFR address ranges.

Originally-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
    @parthitce
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  7. hw/tricore: rename tc27x_soc to tc27xd_soc and add tc39xb SoC 

    Rename the existing tc27x SoC to tc27xd_soc to match the D-Step
silicon designation and rework its peripheral wiring to use the
new device models (ASCLIN, IR, SCU, STM, virt, SFR).

Add tc39xb_soc for the TC397B (B-Step) with 6 CPU cores (only
core 0 active in emulation), 3 STM instances, ASCLIN, IR, SCU,
and memory regions matching the TC39x memory map (PFLASH at
0x80000000, per-core DSPR/PSPR, LMU).

Update triboard.c machine definitions:
- KIT_AURIX_TC277_TRB: uses tc27xd_soc
- KIT_AURIX_TC397B_TRB: uses tc39xb_soc

Originally-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Originally-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
    @parthitce
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  8. hw/tricore: add tc4dx SoC and KIT_A3G_TC4D7_LITE machine 

    Add tc4dx_soc for the TC4D7 (TC4x family) with per-core CPU
wrappers (tc4x_cpu), TC4x clock subsystem, ASCLIN, IR, and
memory regions matching the TC4x address map.

Add KIT_A3G_TC4D7_LITE machine definition in triboard.c with
25 MHz external oscillator and ELF kernel loading support.

Originally-by: Christoph Seitz <christoph.seitz@infineon.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
    @parthitce
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  9. ci: add TriCore QEMU build and release workflow 

    Add GitHub Actions workflow for building TriCore-only QEMU
binary and publishing releases.

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
    @parthitce
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