ceng450_processor/motherboard.ucf at master · mtayler/ceng450_processor · GitHub

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NET "an[0]" LOC = F17;
NET "an[1]" LOC = H17;
NET "an[2]" LOC = C18;
NET "an[3]" LOC = F15;
NET "clk" LOC = U9;
NET "rst" LOC = B18;
NET "sseg[0]" LOC = L18;
NET "sseg[1]" LOC = F18;
NET "sseg[2]" LOC = D17;
NET "sseg[3]" LOC = D16;
NET "sseg[4]" LOC = G14;
NET "sseg[5]" LOC = J17;
NET "sseg[6]" LOC = H14;


NET "inport[0]" LOC = G18;
NET "inport[1]" LOC = H18;
NET "inport[2]" LOC = K18;
NET "inport[3]" LOC = K17;
NET "inport[4]" LOC = L14;
NET "inport[5]" LOC = L13;
NET "inport[6]" LOC = N17;
NET "inport[7]" LOC = R17;

TIMEGRP ROM=PADS("/proc/rom*");
TIMEGRP IF=PADS("/proc/reg_IF.*");
TIMEGRP ID=PADS("/proc/reg_ID.*");
TIMEGRP EX=PADS("/proc/reg_EX.*");

TIMESPEC TS_ROM_IF=FROM ROM TO IF 20;
TIMESPEC TS_IF_ID=FROM IF TO ID 20;
TIMESPEC TS_ID_EX=FROM ID TO EX 20;