diff --git a/.agents/NOW.md b/.agents/NOW.md index c054c3167..fbee0e881 100644 --- a/.agents/NOW.md +++ b/.agents/NOW.md @@ -18,7 +18,7 @@ checkpoint on `upstream/main` at `59674cf1d`. | DeepSeek-V4-Flash decode | **Closed: BEATS ds4 1.144x** (`VT_V4_RESIDENT_W`, byte-exact). Phase-2 routed-expert residency NEGATIVE (−3.4%), default-OFF | — | | f32-out GEMV audit | Only laguna + deepseek_v4 bf16 tower affected; gate/on-framework dense unaffected | Re-verify deepseek_v4 tower same-tool | | Invocation-parity prevention | CI guard (`check-gemv-invocation-consistency.py`) + AGENTS.md checklist landing | Review + merge; CUDA build-verify `kGemvHeuristicAlgos` on dgx | -| MiniMax-H3 lane | **LANDED on main (#26)**: portable path complete; e2e video on real weights (Thor); clean CPU build+ctest gated | FP4 speed path on GB10 (sm_121) | +| MiniMax-H3 lane | **W-FP4a fp4 routing CPU-landed** (`row/H3-FP4-SPEED`): NVFP4 kept packed -> Marlin W4A16, no new quant code; gate 62/62 | GB10 CUDA gate; real e2e disk-blocked | | Kimi-Linear-48B (KDA+NoPE-MLA+MoE) | **Full-model GB10 e2e RUNS** (bf16-resident §13): CPU+CUDA 13/13·656, no OOM. **Token gate NEAR-TIE 106/128** (6/8 token-exact) | device GDN/MLA islands + bf16 stream; 1.59 tok/s; default OFF | | 35B fresh grid | **BOUND** @`1ea26427`: tput 0.93-1.03x, c16 0.93x. INTAKE + Option A both **RESOLVED NEGATIVE** (H2D-out-of-capture tput WASH) | Real lever left: prefill glue (task #61) | | Qwen3.5-4B revalidation | 0.9971x @`59674cf1` (#35); TTFT/PSS pass, TPOT/ITL open | `docs/bench-evidence/` | diff --git a/.agents/benchmark-record.md b/.agents/benchmark-record.md index 60010b82a..1298a0bae 100644 --- a/.agents/benchmark-record.md +++ b/.agents/benchmark-record.md @@ -13093,6 +13093,54 @@ regenerate the GGUF manifest by range-fetching the first 4 MiB of the .gguf and **Next gate:** download a quantized checkpoint and close the e2e loop (encoder -> VAEs -> pipeline), then W2b/W10 for speed. See [.agents/specs/minimax-h3.md](../.agents/specs/minimax-h3.md). +## MiniMax-H3 W-FP4a — fp4-RESIDENT Marlin-W4A16 routing wired; CPU wiring-gate GREEN; GB10 fp4-vs-bf16 delta + s/step PENDING (2026-08-06, `row/H3-FP4-SPEED`, `ROAD-V1-H3`) + +**What changed.** The NVFP4 arm dequantized every packed FP4 projection to bf16 and +ran `vt::MatmulBT`, so the sm_121a FP4 tensor-core route had NEVER run for H3. This +keeps the FP4 packed and routes each quantized projection through +`dense_nvfp4::MatmulNvfp4W4A16D` (Marlin W4A16, forced by vLLM's own a16 selection — +the checkpoint is weight-only NVFP4, `IsTrueW4A4()==false`). No new quant code; it +reuses the same dispatcher as Laguna routed-experts + dense Qwen3-32B NVFP4. + +**Per-shape routing (real geometry, spec §8.1):** all quantized projections are +uniformly Marlin W4A16 — `qkv_proj [21504,5376]`, `out_proj [5376,7168]`, `fc1 +[28672,5376]`(+SiluAndMul, pre-merged so no fused-pair), `fc2 [5376,14336]`, block +`adaln [96768,2688]`, `condition_proj [5376,5120]`, `final_adaln [10752,2688]`, +refiner qkv/out/fc1/fc2. Islands + norms/biases stay bf16/f32. All N,K %16==0 and +%128==0 — no Marlin shape blocker. Peak device memory ~1/4 of bf16 (~16 GB packed +vs ~66 GB bf16). + +**CPU gate (verified, this box has no nvcc):** `test_minimax_h3` 62/62 cases / +30039 assertions, 0 failed (Release, gcc-13). The synthetic-NVFP4 case now streams +BOTH arms on the SAME file, asserts the fp4 loader kept projections PACKED (fp4 slot +set / bf16 slot Empty; inverse for the bf16 loader), and asserts the W4A16 +dispatcher executed all 11 quantized GEMMs (the `Nvfp4W4A16Stats` this-path-ran +counter == 11). fp4-vs-bf16 bounded <= 2e-3. On CPU the dispatcher has no Marlin op, +so it falls back to the bf16 arm's own dequant+matmul: this is a WIRING gate here, +proving the loader sets the fp4 slots and the forward routes them, NOT the kernel +numerics. The Marlin W4A16 kernel itself is CUDA-gated independently by +`test_ops_nvfp4_matmul` (odd shapes, 2e-3 f32-out / 4e-3 bf16-out vs bf16 ref) and +`test_linear_method`. + +**PENDING (GB10, handoff recipe):** git-archive the row to dgx.casa, configure with +`-DVLLM_CPP_CUDA=ON -DVLLM_CPP_CUTLASS_DIR=$HOME/cutlass-4.5.0`, build ONLY +`test_minimax_h3` (targeted — not a whole-archive), run +`test_minimax_h3 --test-case="*NVFP4 checkpoint loads*"` — on CUDA the same case +exercises Marlin (`stats.marlin_gemms==11`) and reports the real fp4-vs-bf16 delta; +add a steady per-step timer around `MiniMaxH3DitForwardDevice`. Blocked on a safe +disk/build window (dgx 33 G free vs 15 G floor; 570 G `.cache` is shared, not ours). +Real-checkpoint t2va e2e is DISK-BLOCKED (~41 GB NVFP4 working set to download vs +~18 GB usable, encoder required for a real render). `benchmark_binding=false`. + +**Comparability (mission #3):** vLLM-Omni CANNOT serve a quantized H3 on one GPU — +BF16-only in practice (source-audited at `a4ea67a2`/v0.26.0: no quantized H3 +checkpoint exists; the fp32-island guard `minimax_h3_transformer.py:898-904` aborts +a naive quant; text encoder hard-bf16 `encoder.py:930`; GGUF not wired into H3). +Single-GPU IS supported but as BF16 + `--enable-cpu-offload`. -> HW/loader-forced- +indirect (DeepSeek-GGUF precedent). The "DiT = 88% of latency" figure is NOT in the +vllm-omni source; the documented anchor is the recipe's 4×B300 BF16 evidence (FL2VA +209f 1248×768 = 86.964 s; two-video Ref2VA = 784.394 s, `recipe:298-311`). + ## Laguna-S-2.1-NVFP4 decode — router top-k KERNEL-EFFICIENCY (`VT_LAGUNA_TOPK_SHFL`), BYTE-EXACT, SigmoidTopK 1.67×, −0.57% decode-step GPU (2026-08-03, `CLAIM-LAGUNA-TOPK-SHFL`) Measured results for vllm.cpp, against the reference engine each workload diff --git a/.agents/model-matrix.md b/.agents/model-matrix.md index 201d3d625..83470a466 100644 --- a/.agents/model-matrix.md +++ b/.agents/model-matrix.md @@ -81,7 +81,7 @@ Engaged architectures (the 45 non-`INVENTORIED` rows): | ✅ | `Glm4MoeLiteForCausalLM` | GLM-4.7-Flash (31.2B MLA + GLM MoE) | SACRED gate 8/8 vs vLLM 0.25.0 (STRICT token-exact 1/8 + near-tie-band 7/8, 69/128 tokens strictly exact, max teacher-forced gap 0.0 nats, 0 forward-divergent; vLLM K=5 self-deterministic → STRICT bar); FIRST e2e coverage of the q_lora query branch AND the noaux_tc sigmoid router (closes the MLA campaign's two gaps, C2); speed pending | `MODEL-TEXT-glm4-moe-lite-glm4-moe-lite-for-causal-lm` | | 🚧 | `KimiLinearForCausalLM` | Kimi-Linear-48B-A3B | **FULL-MODEL GB10 e2e RUNS — NEAR-TIE 106/128 (2026-08-06, `row/MODEL-KIMI-LINEAR-BF16`):** the bf16-resident path CLEARS the f32-loader block — the full 48.9B model now runs e2e on one GB10. dgx CUDA build (`-Werror` clean, 14 GDN AOT symbols nm-linked, `test_kimi_linear_forward` 13/13·656 in the CUDA binary); `kimi-linear-gen --gpu` greedy-decodes the §12 8-prompt battery x16 vs `greedy_ids.npy`. MEMORY: load 117.6s, host RSS PEAK **1.7 GiB** (stage-then-ReleaseHost), device peak 98.5 GiB, min-avail **21.6 GiB** (above the 15 GiB floor, matches the ~25 GiB pool-math headroom), NO OOM/reboot. TOKEN gate **NEAR-TIE 106/128 (82.8%)** — prompts 0,1,3,4,5,6 are 16/16 token-exact, p2/p7 diverge at punctuation/word near-ties; 96 consecutive exact tokens across 6 prompts prove the WIRING (a wiring bug can't). Root cause (honest): the f32 residual stream + host-f64 islands are MORE precise than vLLM's bf16 device kernels, so they flip the argmax where vLLM's deterministic bf16 top-1 has a small margin. STRICT path = the named W7-speed residuals (device GDN/MLA islands -> bf16 stream matching vLLM's rounding). 1.59 tok/s (recompute+island rate). `VT_KIMI_DEVICE_COMPUTE` STAYS OFF (parity-enablers: near-tie != token-exact). Row STAYS 🚧. **bf16-RESIDENT loader/forward IMPLEMENTED + CPU-gated (2026-08-06, `row/MODEL-KIMI-LINEAR-BF16`):** the §13 design is coded — `LoadKimiLinearResidentBf16Weights`/`StageKimiResidentBf16`/`BuildKimiResidentFromHost` (`kimi_linear_weights.cpp`; `LoadBf16Direct` -> `OwnedTensor`, per-tensor stage-to-`d_dev` + `ReleaseHost`, tiny vectors host f32), `KimiLinearResidentWeights` (`kimi_linear.h`), bf16 device forward `DeviceForwardBodyBf16` + `Gemm Bf16` cast-act at ~20 GEMM sites with the two host-fallback islands EXTRACTED+shared (`kimi_linear_device.cpp`), `ForwardDevice` resident-path dispatch (`kimi_linear.cpp`), and the `kimi-linear-gen` e2e harness. CPU **13/13·656** (12/12·614 f32 path UNTOUCHED + NEW tiny-config bf16-vs-f32 gate). PENDING: dgx CUDA build + full-model GB10 e2e vs the STRICT golden. Row STAYS 🚧. **bf16-RESIDENT brick POOL-MATH+DESIGN (2026-08-06, `row/MODEL-KIMI-LINEAR-BF16`):** pool math CLOSES (91.5 GiB bf16 device-resident + ~2.4 GiB act/norms/ctx ≈ 94 GiB, ~25 GiB headroom); design grounded §13 (Laguna `GemmBf16` cast-act + `OwnedTensor::d_dev`, `LoadBf16Direct`, f32 `MaterializeHost` kept for the unit gate). Impl (loader/forward rewrite + gate + e2e) pending. Row STAYS 🚧. **§8 GOLDEN CAPTURED — STRICT (2026-08-06, `row/MODEL-KIMI-LINEAR-E2E`):** the §8 SACRED oracle golden is captured on GB10 (0.25.0-stage, util 0.82, moe=triton, min 15 GiB avail, NO reboot), **8/8 prompts DETERMINISTIC over K=3 → STRICT gate**, committed at `tests/parity/goldens/kimi_linear_greedy/`. Full our-engine e2e BLOCKED on OUR f32 loader (materializes ~183 GiB > 119 pool), the bf16-residency residual; row STAYS 🚧. **W7 GPU-VERIFY (2026-08-06, branch `row/MODEL-KIMI-LINEAR-GPU`):** the device compute runs **12/12·614 GREEN on GB10 sm_121a CUDA build**, BOTH arms (`VT_KIMI_DEVICE_COMPUTE=1` + host-ref); prod stack (CUTLASS-NVFP4 GEMM + FA2 ENABLED + Triton-AOT GDN, 14 cubins nm-verified); f32 device==W2 ref, no divergence, no DeepSeek-class trap. Oracle gateability re-confirmed (0.25.0-stage registers `KimiLinearForCausalLM`). e2e §8 SACRED golden STILL disk-blocked (91.5 GiB checkpoint absent, dgx root 100% full, 34G free). Row STAYS 🚧. **W7 DBuf-resident device COMPUTE landed, CPU-gated** (`CLAIM-KIMI-LINEAR-W7`): the real device compute (`ForwardDeviceCompute`, `kimi_linear_device.cpp`) composes the whole 27-layer KDA/NoPE-MLA + 256-expert-MoE hybrid over pooled f32 `DBuf`s through the SHARED `vt::` ops (embed/`FusedChain` add+RMSNorm/`MatmulBT` projections/`CausalConv1dFwd` convs/`L2Norm`/`RmsNormGated`/`MoeRouterTopK` sigmoid-`noaux_tc`/`MoeSiluMul`/`MoeCombine`/lm_head), returning DEVICE-RESIDENT logits; 2 documented HOST-FALLBACK islands (the KDA per-k-channel gated-delta recurrence + its exp/softplus decay gate — `vt::GdnDecode` carries only a per-HEAD scalar decay; the NoPE-MLA softmax core — the paged `mla::ForwardMlaAttentionBlock` device path is born-on-runner) are the W7-speed residuals. CPU-gated vs the W2 host reference (the CPU backend runs the SAME `vt::` dispatch): `test_kimi_linear_forward` **12/12·614** (per-op KDA/NoPE-MLA/MoE/dense device==ref within f32-accumulation tolerance; the whole `ForwardDeviceCompute` == ref logits + greedy-token-identical + device-resident). Runner opt-in via `VT_KIMI_DEVICE_COMPUTE=1` (default OFF keeps the CPU-verified W6 host-ref compose). GPU numerics (bf16 activations, GDN Triton-AOT cubins, paged het-KV, grouped-MoE slabs) + the e2e SACRED golden stay a NAMED pending (box down) — row STAYS 🚧. ON TOP OF **W6 DEVICE forward SEAM** (`CLAIM-KIMI-LINEAR-W6`): the born-on-the-runner `ForwardDevice` (the DEFAULT `gather_logits` runner path) no longer refuses — it composes the `[rows,vocab]` logits via the CPU reference and hands them back DEVICE-RESIDENT (a pooled `DBuf`, wrapped like deepseek_v2 `WrapDeviceLogits`; `on_device()==true` on CPU+CUDA) so the on-GPU sampler consumes them with NO host download. Kimi-Linear now ROUTES device-resident (`check-runner-routing-consistency` reclassifies it, refuse-skipped stubs 2→1, NO allowlist; `check-fusion-consistency` green); `test_kimi_linear_forward` **7/7·300** (adds the `ForwardDevice`==host-ref device-resident gate). The DBuf-resident device COMPUTE (KDA via the GDN family, NoPE-MLA via `mla::ForwardMlaAttentionBlock`, DeepSeek-V2 grouped-MoE over the paged het-KV; full plan in `kimi_linear.cpp`) is the GPU-verify-pending W7 residual. ON TOP OF **W2-W6 CPU REFERENCE forward** (`CLAIM-KIMI-LINEAR-W2`): the real host `KimiLinearModel::Forward` composes the whole 27-layer hybrid from the landed primitives (KDA layer via `vllm::kimi_kda` refs + the gated-delta recurrence; NoPE-MLA materialized-MHA ref; sigmoid `noaux_tc` MoE + shared expert; dense SwiGLU); loader now materializes host float weights; `test_kimi_linear_forward` 6/6·246 (per-op gates + finite whole forward + greedy decode). ON TOP OF **W1 scaffolding** (registry + `ParseKimiLinearParams` 20 KDA + 7 NoPE-MLA + index-verified name-map + het-KV spec). e2e-gateable (FITS one GB10, 0.77× pool). RESIDUAL = the DEVICE born-on-runner forward (KDA kernel/absorbed-MLA/grouped-MoE slabs) + the W0/W7 e2e SACRED golden. Row → `ACTIVE` (device SEAM wired; the DBuf device compute + e2e SACRED golden pending) | `MODEL-TEXT-kimi-linear-kimi-linear-for-causal-lm` | | 📋 | `KimiK3ForConditionalGeneration` | Kimi K3 (2.8T MoE + MoonViT-V2, DERIVE-AND-SHIP) | **W2/W5 CPU scaffolding landed** (registry stub + nested text/vision/quant config descent + text-backbone structural name-map + REFUSE-by-name forward + MXFP4-refuse loader; clean CPU build, scaffold gate 6/6). text backbone IS `KimiLinearForCausalLM` (KDA+MLA+MoE hybrid, HEAVY reuse); **does NOT fit GB10 (~1.56 TB MXFP4, ~12×)** and NOT in the pinned oracle ⇒ no on-box golden — DERIVED, proxy-gated on Kimi-Linear-48B; forward + MXFP4 + KDA delta + MoonViT-V2 not implemented (NOT-YET-BUILDABLE) | `MODEL-MM-kimi-k3-kimi-k3-for-conditional-generation` | -| 🚧 | `MiniMaxH3DiTModel` | MiniMax-H3 (33.1B omni-modal video+audio DiT, DERIVE-AND-SHIP) | **W1/W2 landed**: packed layout (fl2va + ref2va, fp64 position grid BIT-EXACT), latent packing, euler-ancestral eta0 scheduler, and the full DiT forward all parity-gated against the UPSTREAM vLLM-Omni modules executed at reduced dimensions (**max abs diff 1.6e-7**, 10/10 cases / 2539 assertions). NOT autoregressive (no KV cache, no sampler, no logits) and **e2e HW-BLOCKED** (~354 GB checkpoint, ~133 GB/rank on 4x B300 vs 119 GiB unified); bf16 production stream + request planning + the ComfyUI-GGUF arm also landed (535 REAL tensors resolve onto our contract, geometry from shapes alone). **HW verdict CORRECTED: quantized arms FIT (~41 GB in 119 GiB)**, so e2e + speed are reachable; encoder/VAEs/audio VAE DONE (4.2e-9 vs the checkpoint's remote code); NVFP4 layout GATED as identical to ours (speed path is loader wiring); BOTH VAE DECODERS done (audio 4.2e-9, video ViT3D 8.9e-8); video tiling + 3D-CNN encoder (conditioning only) pending; encoder TEXT tower done (1.2e-7); **serving `/v1/videos` DONE and the DEVICE-RESIDENT forward (W2b, f32) LANDED + GPU-VERIFIED on Thor sm_110 at video 1.49e-7 / audio 8.94e-8**; bf16 stream + fusion folds + the FP4 path (needs sm_121a) + a real-checkpoint run pending. **2026-08-05: the AUDIO-VAE ENCODER is ported** (DAC analysis stack + `pre_block` AttnProjection + `mean_proj`, gated stage by stage vs the checkpoint's own remote code at 2.98e-8 / 1.64e-7 / 1.86e-8) with its own checkpoint loader gated on the real 1087-tensor manifest — so **ref2va AUDIO and VIDEO+AUDIO references are now WIRED** (audio rows move by 0.51 / 0.71; a different waveform still moves them by 7.1e-4). Both VAEs are now complete in both directions | `MODEL-DIFFUSION-minimax-h3-mini-max-h3-dit` | +| 🚧 | `MiniMaxH3DiTModel` | MiniMax-H3 (33.1B omni-modal video+audio DiT, DERIVE-AND-SHIP) | **W1/W2 landed**: packed layout (fl2va + ref2va, fp64 position grid BIT-EXACT), latent packing, euler-ancestral eta0 scheduler, and the full DiT forward all parity-gated against the UPSTREAM vLLM-Omni modules executed at reduced dimensions (**max abs diff 1.6e-7**, 10/10 cases / 2539 assertions). NOT autoregressive (no KV cache, no sampler, no logits) and **e2e HW-BLOCKED** (~354 GB checkpoint, ~133 GB/rank on 4x B300 vs 119 GiB unified); bf16 production stream + request planning + the ComfyUI-GGUF arm also landed (535 REAL tensors resolve onto our contract, geometry from shapes alone). **HW verdict CORRECTED: quantized arms FIT (~41 GB in 119 GiB)**, so e2e + speed are reachable; encoder/VAEs/audio VAE DONE (4.2e-9 vs the checkpoint's remote code); NVFP4 layout GATED as identical to ours (speed path is loader wiring); BOTH VAE DECODERS done (audio 4.2e-9, video ViT3D 8.9e-8); video tiling + 3D-CNN encoder (conditioning only) pending; encoder TEXT tower done (1.2e-7); **serving `/v1/videos` DONE and the DEVICE-RESIDENT forward (W2b, f32) LANDED + GPU-VERIFIED on Thor sm_110 at video 1.49e-7 / audio 8.94e-8**; bf16 stream + fusion folds + the FP4 path (needs sm_121a) + a real-checkpoint run pending. **2026-08-05: the AUDIO-VAE ENCODER is ported** (DAC analysis stack + `pre_block` AttnProjection + `mean_proj`, gated stage by stage vs the checkpoint's own remote code at 2.98e-8 / 1.64e-7 / 1.86e-8) with its own checkpoint loader gated on the real 1087-tensor manifest — so **ref2va AUDIO and VIDEO+AUDIO references are now WIRED** (audio rows move by 0.51 / 0.71; a different waveform still moves them by 7.1e-4). Both VAEs are now complete in both directions. **W-FP4a LANDED (CPU) 2026-08-06 (`row/H3-FP4-SPEED`)**: the device DiT forward now routes the NVFP4 projections through the shared Marlin W4A16 dispatcher (fp4 kept packed; no new quant code), fp4-vs-bf16 wiring gate GREEN (62/62·30039); GB10 speed delta + real e2e pending (disk-blocked); vLLM-Omni has no quantized H3 arm (BF16-only) so any comparison is HW/loader-forced-indirect — spec §8 | `MODEL-DIFFUSION-minimax-h3-mini-max-h3-dit` | | ✅ | `LagunaForCausalLM` | Poolside Laguna-S-2.1 (118B/8B MoE) | **LONG-CTX DECODE LEVERS LANDED + MEASURED (2026-08-03, `CLAIM-LAGUNA-LONGCTX-LEVERS`): window-bounded SWA reads (`VT_LAGUNA_SWA_WINDOW`, default-ON, BYTE-EXACT) bound the four `DecodeAttnGqa*` kernels' read to the ~512 sliding window (vLLM `laguna.py:412`) — GB10 A/B token-IDENTICAL `=1` vs `=0` at 520-token context (truncation active), MEASURED −0.30 ms/step at ~2k (~0 at ≤512, grows linearly). bf16 paged KV (`VT_LAGUNA_KV_BF16`, default-OFF opt-in) a distributional near-tie left UNRATIFIED. See BENCHMARKS `CLAIM-LAGUNA-LONGCTX-LEVERS`.** — **NVFP4 W4A4 ARM RAN on GB10 (N4, 2026-08-01, `CLAIM-LAGUNA-NVFP4-N4`): the additive safetensors NVFP4 arm (N1a/N1b/N2/N3 — `Nvfp4Weight` expert fields + `LoadLagunaForCausalLMWeights` + `LqGemmNvfp4Fp4` per-expert TRUE-W4A4 + `LagunaFfnBlock` `fp4` branch + `laguna_gen` dir-autodetect; CPU-gated `test_laguna_nvfp4_loader` 3/3·61, GGUF path byte-identical) generates COHERENTLY on the real 67 GiB `poolside/Laguna-S-2.1-NVFP4`. vs the vLLM MARLIN golden (vLLM's exact prompt ids injected): FIRST 2 TOKENS MATCH exactly, then near-tie divergence (our TRUE-W4A4 fp4-activations vs the MARLIN golden's W4A16 bf16-activations — different precision, EXPECTED; shares golden vocab). SPEED (N5, trace-driven, 2026-08-01): 0.16 → ~4.5 tok/s (~28× THIS SESSION), now ~4× from vLLM 18.8. **Lever #2** (nsys found the bf16 tower running host `MatmulNK` on the CUDA queue): route it to the GPU (`LqGemm` bf16 → `CastBf16` + `MatmulBT`, weight stays bf16) → 6.34 → 0.39 s/tok (16×). **Lever #1** (nsys found the emulation expert GEMM at 92%, GPU 87% busy): the engine's native sm120a fp4 tensor-core MMA (`MatmulNvfp4Fp4Native`) reads the SAME linear scales — it was gated OFF behind `VT_NVFP4_FP4_NATIVE`; default it ON in the driver → 0.39 → ~0.20-0.24 s/tok (~2×). Both coherent + near-tie (byte-identical ids to emulation; first token matches golden). Two GB10 memory fixes landed to run (shard-release + context-before-load). OPEN #234 (remaining ~4×): grouped W4A4 MoE (top_k×3 launches → 3), `ResidentNvfp4`, decode CUDA-graph + on-GPU sampling (the host-orchestration tail). Spec `.agents/specs/laguna-nvfp4-arm-2026-07-31.md` §N4/§N5. The GGUF-Q4_K track (below) is the separate keep-quant vehicle.** Prior **FASTER DECODE (W9, 2026-07-31, `CLAIM-LAGUNA-W9-GROUPED`): the 30 un-grouped per-expert keep-quant GEMV launches/step (top_k × {gate,up,down} `LqGemmRowSlice`) fold onto the SHARED `vt::MatmulBTQuantGrouped` op — per token, Pk experts' gate/up/down each collapse to ONE grouped launch over the already-stacked `[E*N,H]` tower (no loader change). Same-binary A/B on real UD-Q4_K_XL (GB10, `--gpu`, drop_caches cold, 24 tok): grouped (`VT_LAGUNA_GROUPED_MOE=1`, default) == per-expert (`=0`) BYTE-IDENTICAL (md5 `754728c6`, both == W6 golden) + decode 0.18 → 0.13 s/tok (1.38×). Routes through the shared vt op (fold policy). Cumulative with W8: decode 0.66 → 0.13 s/tok (5.1×; 1.5 → 7.7 tok/s; 18× → 3.6× vs llama.cpp 27.8). Next lever: device-resident decode (#1). See spec §W9.** Prior **FASTER DECODE (W8, 2026-07-31, `CLAIM-LAGUNA-W8-EMBED`): `LagunaEmbed` no longer converts the whole 1.23 GB embed table to f32 every token (it gathered T rows out of the whole [Vsz,H] table via `ReadF32` — ~311M host element-converts/token, the DOMINANT decode cost the W7 profile under-filed as "#5"); now gathers only the T needed rows directly (BIT-IDENTICAL — same per-element conversion, same rows). GATED on the real 3-shard UD-Q4_K_XL GGUF (GB10, `--gpu`, W6 cached, drop_caches cold, 24 tok): TOKEN-IDENTICAL to the W5/W6 golden (`22345 83 350 785 …`, coherent " Paris.") + decode 0.66 → 0.17 s/tok = 3.9× (1.5 → 5.9 tok/s; 18× → 4.7× vs llama.cpp 27.8). See `.agents/specs/laguna-s21-w7-speed-2026-07-31.md` §W8. Next: grouped-expert GEMM (=A3) then device-resident decode.** Prior **DECODE-SPEED ATTRIBUTED (W7 profile-only, 2026-07-31, `CLAIM-LAGUNA-W7-SPEED`): `nsys` of the W6 decode (real UD-Q4_K_XL GGUF, GB10) attributes the 0.66 s/tok (~1.5 tok/s vs llama.cpp 27.8 on identical bytes, ~15-18x) to HOST-ORCHESTRATION, not kernel compute — GPU active only 32.7% of the step, 67.3% host/idle; 22,115 `cudaStreamSynchronize` (~2,764/step, zero GPU overlap) from the ~1,795 per-GEMM `DrainQueue` in `LagunaForwardGgufCached` + scalar host glue; 39.4% of GPU time is `QuantizeQ8K` activation-quant (per-GEMM), weight GEMVs un-grouped at ~22% of the 240 GB/s peak (llama.cpp ~76%); no H2D/D2H (unified memory). Ranked levers (all in-tree from ds4): device-resident decode 1.5->~5-7 tok/s, grouped-expert GEMM (`MatmulBTQuantGrouped`) +1.5-2x + dedupes the activation-quant, decode CUDA-graph, tuned MMVQ; + free host cleanups (`LagunaEmbed` copies the whole 1.23 GB embed table/token, per-token RoPE-cache rebuild). Honest reachable ~13-20 tok/s, 27.8 a stretch. NO code changed. See `.agents/specs/laguna-s21-w7-speed-2026-07-31.md`. Prior RUNNABLE + FAST DECODE (W6, 2026-07-31): a per-layer K/V cache + single-token incremental decode replaces W5's O(n²) STATELESS recompute — TOKEN-IDENTICAL (byte-equal ids, md5 `754728c6…` match, == the W5 golden) and 5.05× faster per token: decode 3.33 → 0.66 s/tok on the real UD-Q4_K_XL GGUF (GB10, `--gpu`, keep-quant), same " Paris.…" text. `LagunaKvCache` (mirrors `DeepseekV4KvCache`, MLA-latent → GQA multi-head K/V; caches post-QK-RMSNorm/post-RoPE K + raw V at f32 — bit-exact since RoPE/QK-norm are position-only and attention is causal), MIXED attention per-layer: 12 GLOBAL layers grow unbounded + 36 SLIDING-WINDOW-512 layers EVICT rows beyond the 512 window (gemma2/3 `is_sliding`); `LagunaForwardGgufCached` + shared `LagunaAttention`/`LagunaFfnBlock` helpers used by BOTH forwards (identical float ops; recompute ids unchanged after refactor), `examples/laguna_gen --stateless` A/B flag. No cache bug (bit-exact first run). Next speed = grouped-expert GEMM + device-resident decode (both in-tree from ds4). See `.agents/specs/laguna-s21-w6-2026-07-31.md`. Prior RUNNABLE (W5, 2026-07-31): our engine greedy-generates COHERENT text on the REAL 3-shard UD-Q4_K_XL GGUF (GB10 keep-quant) — "The capital of France is" → " Paris. …", first token "Paris." matches the llama.cpp-Poolside reference. Multi-shard GGUF reader + keep-quant tower (`LoadLagunaFromGgufShards`) + `LagunaForwardGguf` (ds4 keep-quant Gemm/GemmRowSlice) + `examples/laguna_gen`; load 20.6s, peak 71 GiB, 3.27 s/tok stateless recompute (speed=W6).** Prior W3: **W3 REAL forward + 3 new ops landed** (`laguna_ops.cpp`: per-head softplus attn out-gate + ungrouped sigmoid-noaux router + dual per-layer RoPE cos/sin builders; `LagunaModel::Forward` now a REAL runnable host-reference composition — variable-Q-head GQA + dual RoPE + sliding-window mask + softplus gate + dense L0 / ungrouped-MoE L1..47 + untied lm_head — replacing the W1/W2 `VT_CHECK(false)` stub; CPU `-Werror` full-library build clean; `test_laguna_scaffold` **8/8·166** incl. softplus math, router selection+tie-break RED-first, dual-RoPE cos/sin bit-match, variable-Q-head shapes, forward composition on synthetic weights; `test_model_registry` 24/24). W1 oracle DECISION: vLLM native `laguna.py` in pin ⇒ config constructs; dual-oracle = vLLM-NVFP4/-FP8 (fits GB10, BF16 235 GiB does NOT) + llama.cpp-Q4_K token-exact. DEFERRED to W4 (needs 73 GB checkpoint): GGUF keep-quant tower materialization + device/paged production forward + strict dual-oracle greedy gate. ~85-90% reuse (ds4-MoE + gemma-sliding + olmo3-dual-rope + landed Q4_K keep-quant); NEW = the 3 landed host ops + name-map + variable-Q-head device runner. **W4 (2026-07-31, `CLAIM-LAGUNA-W4`, in progress):** the UD-Q4_K_XL GGUF (73.4 GiB, 3 shards) FETCHED to dgx + its metadata/tensor-map READ AUTHORITATIVELY (814 tensors, arch `laguna`, `expert_gating_func=2` sigmoid, `leading_dense_block_count=1`, `expert_weights_scale=2.5`). Three CPU-verified FIDELITY corrections the W1-W3 scaffold got wrong, each grounded in the real GGUF + llama.cpp: (1) **per-head QK-RMSNorm** (`attn_q_norm`/`attn_k_norm` F32[128]) added to params+forward — the scope MISSED it (surfaces only in the tensor map); (2) **dual-RoPE mscale** now uses llama.cpp's `yarn_attn_factor·(1+0.1·ln(factor))` off the GGUF-authoritative `factor=32`/`yarn_attn_factor=1.0` (256K-ctx build, NOT HF's factor-128/1.4852 1M-ctx scalar) — resolves the numerics-delicate residual; (3) **separate** `ffn_gate_exps`/`ffn_up_exps` (Q4_K) + `ffn_down_exps` (Q5_K) + Q8_0 shared/attn (the scaffold assumed merged gate_up). GGUF keep-quant tower materialization (`Mw`/`Sew` mirror of ds4) + keep-quant `ForwardGguf` (vt::MatmulBT/GemmRowSlice) + the real-model greedy run vs the llama.cpp-laguna same-quant oracle remain the W5 close (73 GB single-GB10, host-orchestrated) | `MODEL-TEXT-laguna-laguna-for-causal-lm` | | 🚫 | `DeepseekV3ForCausalLM` / `DeepseekV32ForCausalLM` | DeepSeek-V3 / V3.2 | HW-blocked (671B, ~642 GiB fp8 vs 119 GiB unified memory); V3.2 additionally DEP-blocked (DSA indexer) | `MODEL-TEXT-deepseek-v2-deepseek-v3-for-causal-lm` | | 🚫 | `GlmMoeDsaForCausalLM` | GLM-5 (DSA) | HW-blocked (1404 GiB bf16) and DEP-blocked (GLM-5.x is DeepSeek-V3.2 verbatim) | `MODEL-TEXT-deepseek-v2-glm-moe-dsa-for-causal-lm` | diff --git a/.agents/parity-ledger.md b/.agents/parity-ledger.md index 176778328..49de1eb98 100644 --- a/.agents/parity-ledger.md +++ b/.agents/parity-ledger.md @@ -913,3 +913,4 @@ Columns: | 2026-08-04 (`HARDEN-DETECTOR-LANES` PR #28 CI repair; `CLAIM-HARDEN-SANITIZER-DISK`; Ordino task `t-e19dc73f`; CPU-only, lifecycle unchanged; closing commit: this checkpoint) | Repairs the hosted ASan+UBSan build's filesystem exhaustion without weakening detector coverage. Sanitizer tests share one internal fully instrumented engine image instead of force-linking another static copy into every executable, and `-g1` retains file/line traces without full type/local-variable DWARF. CI enables the existing `VT_POOL_BYPASS=1` exact-allocation/real-free detector mode. The newly reachable leak survey removes a real minja `MacroNode` ownership cycle by weakly capturing the context that owns the callable. It also closes the two Nix-only suite portability gaps: resolve `true` and the active Python executable instead of assuming `/usr/bin`, and remove inherited `PYTHONHASHSEED` only from the unconfigured control suite. Default build linkage and packaged C ABI exports remain unchanged. | No vLLM behavioral counterpart: this is local build/test infrastructure plus a vendored minja lifetime repair. Anchors: `CMakeLists.txt`, `tests/CMakeLists.txt`, `.github/workflows/ci.yml`, `third_party/minja/minja.hpp`, `tests/tools/test_gdn_packed_component.py`, and `tests/tools/test_online_gate_client.py`. Remote root-cause evidence: GitHub run `30819266647`, job `91704728276`, 99 MiB free then `ld: No space left on device`. | **PASS.** GCC 15.2.0 ASan+UBSan full suite **331/331** under leak detection and pool bypass; TSan full suite **331/331** under pool bypass; affected plain GCC 15 `-Werror` suites **3/3**. ASan+UBSan tree **93 GiB -> 5.6 GiB** (about 94% smaller); TSan tree **1.9 GiB**. `benchmark_binding=false`, performance **NOT APPLICABLE**. Hosted PR confirmation is the next external gate; `continue-on-error` stays until that confirmation. | | 2026-08-06 (`row/KERNEL-FA2-GQA-SWAP`; `CLAIM-KERNEL-FA2-GQA-SWAP`; kernel `KERNEL-ATTN-FA2`; gated default-OFF, lifecycle unchanged) | Ports vLLM's FA2 `seqlenq_ngroups_swapped` decode optimization into the d128 varlen decode launcher (`LaunchDecodeVarlenFA2Bf16`, gate `VT_FA2_DECODE_GQA_SWAP`): the Qwen3-dense decode grid becomes `(batch, kv_heads)` not `(batch, hq)` — the ngroups query heads pack into seqlen_q, KV read once/group, presented WITHOUT a materialized transpose via kv-major-group-minor strides (a 1:1 mirror of the already-shipped d256 `LaunchDecodeFA2Bf16` swap). OFF path byte-identical to the prior plain-varlen reduction; ON is non-byte-exact only when num_splits>1 (split reduction order → near-tie, toward vLLM's own numerics). | Mirrors `flash-attention @ 2c839c33` `mha_fwd_kvcache` seqlenq_ngroups_swapped + `set_params_splitkv` and vLLM v0.25.0 `flash_attn.py flash_attn_varlen_func` decode (#47 measured vLLM's swapped grid `(1,6,16)` = batch×kv_heads vs ours `(1,3,64)` = batch×query_heads). The vendored `flash_fwd_kernel.h` `get_lse_tile`/combine already honor the flag in both the num_splits==1 direct-write and >1 combine paths (the d256 arm is the proof). | GB10 sm_121a CUDA 13.0: op RED-first test 280/280 (both GQA ratios × batch{1,2,4,8} × short+long ctx; `swap_launches==1` proves the grid engaged; swap-vs-plain near-tie; MHA-inert) — RED proven (wrong swapped stride → 26,528 violations); full binary 28/28·454,679 no regression; compute-sanitizer 0-err/0-leak; #44 MXFP4 e2e smoke swap-ON 3/3 deterministic TOKEN-EXACT + coherent, byte-identical to swap-OFF. `benchmark_binding=false` (c1-c8 x3 re-bench + default flip = recorded next step; #47 projects flash ~28%@c2 / ~55%@c8 of the gap). | | 2026-08-06 (`row/KERNEL-MARLIN-DENSE-PORT`; `CLAIM-KERNEL-MARLIN-DENSE-PORT`; kernel `KERNEL-GEMM-MARLIN-W4A16`; gated default-OFF, lifecycle unchanged) | Vendors vLLM's OWN dense marlin W4A16 GEMM as a new `vt::MarlinDenseGemm` op (`VT_MARLIN_DENSE`, default OFF) and routes the E=1 dense NVFP4/MXFP4 projections (`dense_nvfp4_gemm.h` `MatmulNvfp4MarlinD`/`MatmulMxfp4W4A16D`/`GateUpFusedMarlinD`) through it. The dense kernel is direct-A + tile-per-CTA with vLLM's OWN dense fp32-C_tmp reduce, so at M<=8 it runs the sms-wide (48-CTA) grid WITHOUT the one-bf16-ULP shift the `VT_MARLIN_E1_PAR1` MoE-route par-regroup costs (#54: that ULP flips a strict 32B-NVFP4A16 token). Reuses the EXISTING marlin resident + workspace (same `marlin_permute` repack for dense and MoE — confirmed, no shim); rank-2 operand views, no moe_align gather. | 1:1 lift of vLLM @ `555967922` `csrc/libtorch_stable/quantization/marlin/`: `marlin.cu:326-541` (`marlin::marlin_mm` + config helpers) → `marlin_mm_dense.cu`; the torch::stable `marlin_gemm` wrapper (`:545-894`) → torch-free `cuda_marlin_dense.cu` launcher (mirrors `cuda_moe_marlin.cu`, dense c_tmp sizing `:713-716`); `kernel.h`/`marlin_template.h:1-2081` verbatim (the DENSE kernel — DISTINCT from the moe one, but SAME 12-param `Marlin<>` template so the generated `kernel_selector.h`+`sm80_*.cu` instantiation set is shared, namespace `marlin` from the local kernel.h). Shared `marlin.cuh`/`marlin_dtypes.cuh`/`dequant.h`/`marlin_mma.h` diff-verified byte-identical. Forced-Marlin a16 selection `kernels/linear/__init__.py:879-881`. | CPU `-fsyntax-only` CLEAN (`ops.cpp` + the `VT_MARLIN_NVFP4` routing header). GPU compile: all 3 new dense `.cu` compile CLEAN on dgx GB10 sm_121a under exact production flags (`-Werror=all-warnings`, `-static-global-template-stub=false`, `--generate-code=…sm_121a`). RED-first unit battery WRITTEN (`test_ops_moe_grouped.cpp`: NVFP4+MXFP4, M=1..8 × 3 shapes, dense-vs-CPU-ref AND dense-vs-grouped-route, row-shifted stride RED-injection). `benchmark_binding=false`; GPU EXEC gates (unit run + strict token battery dense-ON vs oracle incl. 32B-NVFP4A16:344 + launch-counter + nsys 48-CTA + binding c1..c8 x3) are the scoped dgx follow-up; default stays OFF until the strict battery proves oracle byte-match and the binding beats the MoE route (state `KERNEL-MARLIN-DENSE-PORT`). | +| 2026-08-06 (`row/H3-FP4-SPEED`; `ROAD-V1-H3`; model `MODEL-DIFFUSION-minimax-h3-mini-max-h3-dit`; lifecycle unchanged) | **MiniMax-H3 W-FP4a — fp4-RESIDENT NVFP4 routing for the device DiT forward (NO new quant code).** Until now both NVFP4 loaders dequantized the packed FP4 projections to bf16 and the device forward ran `vt::MatmulBT`, so the sm_121a FP4 tensor-core route never ran for H3. Adds `Nvfp4Weight` carriers to `MiniMaxH3DitBlockWeights`/`MiniMaxH3DitWeights`, a fp4-resident streamer `StreamMiniMaxH3Nvfp4ToDeviceFp4` (keeps the compressed-tensors triple host-resident; the shared dispatcher uploads+repacks lazily then frees the fp4 originals, so peak device memory is ~1/4 of the bf16 arm), and a `LinearDev` dispatch that routes a non-Empty fp4 projection through `dense_nvfp4::MatmulNvfp4W4A16D`. | The routing is vLLM's OWN forced-Marlin-for-a16 selection: the checkpoint is weight-only NVFP4 (no `input_activations`, `IsTrueW4A4()==false`), so `kernels/linear/__init__.py:879-881` forces the Marlin W4A16 kernel, mirrored by `include/vllm/model_executor/models/dense_nvfp4_gemm.h:12-22,505-549` (`MatmulNvfp4W4A16D` -> single-expert `vt::MoeGroupedGemmNvfp4Marlin`, the SAME kernel Laguna routed-experts + dense Qwen3-32B NVFP4 use). Not cutlass-fp4/W4A4 (needs fp4 activations, private to `qwen3_5.cpp`). fc1 is already merged `[gate;up]` -> one W4A16 GEMM + `vt::SiluAndMul`. | **CPU-GATED (wiring), verified**: `test_minimax_h3` 62/62 cases / 30039 assertions, 0 failed. The synthetic-NVFP4 case streams the fp4 twin, asserts the loader kept the projections PACKED (fp4 slot set / bf16 slot Empty, and the inverse for the bf16 loader), runs fp4 + bf16 device forwards on the SAME file, asserts the W4A16 dispatcher executed ALL 11 quantized GEMMs (the `Nvfp4W4A16Stats` this-path-ran counter), and bounds fp4-vs-bf16 <= 2e-3. On CPU the dispatcher has no Marlin op so it falls to the bf16 arm's own dequant+matmul (hence a WIRING gate here); the Marlin kernel numerics are CUDA-gated independently by `test_ops_nvfp4_matmul` / `test_linear_method` (2e-3 f32-out / 8e-3 bf16-out vs a bf16 reference). `benchmark_binding=false`. PENDING: GB10 CUDA build + the fp4-vs-bf16 numeric delta and steady per-step timing (disk/build window); real-checkpoint t2va e2e DISK-BLOCKED (~41 GB working set). Comparability: vLLM-Omni serves NO quantized H3 (BF16-only in practice; source-audited `a4ea67a2`, spec §8.3) -> HW/loader-forced-indirect. | diff --git a/.agents/roadmap_v1.md b/.agents/roadmap_v1.md index 3fb8c19cb..64ed24d45 100644 --- a/.agents/roadmap_v1.md +++ b/.agents/roadmap_v1.md @@ -76,7 +76,7 @@ models we already ship + benchmark. Full seam map + M0–M5 W-plan: | 13 | `ROAD-V1-D4` | **KV persistent state to disk, and external KV-cache provider interoperability with LMCache** (user-directed 2026-07-22: "let's do the KV persistent state to disk support, and LMCache support too", under the standing same-featureset-as-vLLM-and-better bar) | [`KV-OFFLOAD`](engine-matrix.md), [`KV-EXTERNAL-CACHE`](engine-matrix.md), [`KV-CONNECTORS`](engine-matrix.md), [coverage view §2](feature-matrix.md#2-kv-cache--memory), [LMCache quickstart](https://docs.lmcache.ai/getting_started/quickstart.html) | spike ACCEPTED [kv-persistence-lmcache.md](specs/kv-persistence-lmcache.md) — 60 enumerated features across `vllm/v1/kv_offload/`, the `KVConnectorBase_V1` ABI and the LMCache integration, each with a DONE/PARTIAL/MISSING verdict read out of our source. **The two halves of the user's ask are NOT the same kind of work.** Disk persistence is a faithful MIRROR job and is tractable: vLLM's `fs` tier is ~101 lines of `open`/`write`/`readv` with nothing Python-specific in the byte path, one raw file per block, temp-file + atomic rename under `O_DIRECT`. LMCache is NOT: the vLLM-facing glue is vendored in-tree (~2396 lines) but every file of it imports the EXTERNAL PyPI package at module scope, and the storage engine, wire protocol, config schema and CUDA-IPC handoff all live outside the tree with no upstream test that runs without it — so it is scoped as an interop STUDY with a go/no-go, never a from-scratch client. **REOPENED 2026-07-23 ([LMCache client wire analysis](specs/lmcache-cpp-client-connector.md)), and the "no specified wire protocol" half of that verdict is REFUTED by reading the LMCache package: vLLM connects to a RUNNING LMCache over TWO fully-specified portable wires — the `lm://` remote-store (plain TCP + fixed `struct` header + raw KV bytes, no ZMQ/msgpack/pickle/CUDA-IPC) and the MP server (ZMQ + `msgspec.msgpack` + CUDA-IPC, the user's "zmq" recollection). A from-scratch C++ client is FEASIBLE with ZERO `lmcache` in-process; both wires sidestep the hash blocker because LMCache keys on its own blake3 token hash. Recommend the `lm://` mode first. Residual risk is that LMCache is an unpinned moving target — an interop feature with a version-sync cost, not a mechanical core port. LMCACHE-CLIENT W1 LANDED 2026-07-23 (`CLAIM-LMCACHE-CPP-CLIENT`, `KV-EXTERNAL-CACHE` `SPIKE`→`ACTIVE`): the pure-CPU `lm://` wire codec — fixed-`struct` `ClientMetaMessage`/`ServerMetaMessage` framing, the `CacheEngineKey` string, the blake3 rolling token hash (vendored BLAKE3 1.5.5), and the `KV_2LTD` `[2,L,T,D]` repack — is BYTE/BIT-EXACT vs fixtures from the real Python codec (`test_lmcache_codec` 6/6, 2074 assertions), blake3 verified byte-identical on x86-64 + aarch64, and INERT (no call site; the connector is client-W3). LMCACHE-CLIENT W2 LANDED 2026-07-23 — the go/no-go PASSED: a blocking POSIX-socket `LMCacheRemoteClient` (PUT/GET/EXIST/HEALTH/LIST + `KV_2LTD` repack + `VT_LMCACHE_*` config) round-trips a REAL `lmcache.v1.server` (`8570aad`, run headless from source in a throwaway venv — torch imported before lmcache to dodge a torch circular import, the compiled `c_ops` ext stubbed as unused by the lm:// CPU store) byte-identical (`test_lmcache_client` 36/36), with BIDIRECTIONAL interop proven against LMCache's OWN Python protocol codec; the always-on CI gate is a same-binary C++ mock-server round-trip (45/45, no Python). STILL `ACTIVE`, not DONE. Resume at client-W3 (wire as a `KVConnector` over the parent W5 seam, then key-agreement + DGX every-axis gates).** **Blocking correction found in OUR source:** `NONE_HASH` is seeded from `std::random_device` with no escape hatch, so every block hash differs across processes and a content-addressed disk tier would score 0% hits on restart — we are WORSE than vLLM here, which at least exposes `PYTHONHASHSEED`. This also FALSIFIES the caching spike's §B2 claim that we are deterministic by construction. **Two upstream weaknesses recorded as beyond-parity targets:** the `fs` tier's `config.json` is written and never read (its only identity check is a path digest that omits checkpoint content, weight quantization, rope config and `sliding_window` — a silent-wrong-output hazard we will not copy), and the disk tier has no capacity accounting and no eviction. Three matrix rows `INVENTORIED` -> `SPIKE`; `SharedStorageConnector` found RENAMED to `ExampleConnector` and `P2pNcclConnector` found DELETED at the pin, both stale in the prior record **W1-W3 IMPLEMENTED 2026-07-22, CPU-only.** W1 deterministic block hashes: `init_none_hash` now resolves explicit arg > `$VLLM_PREFIX_CACHING_HASH_SEED` > `$PYTHONHASHSEED` > a fixed built-in default, so hashes are identical across processes with ZERO configuration — the blocking correction is CLOSED, and we now BEAT upstream on this axis rather than trailing it (upstream is random-by-default and documents `PYTHONHASHSEED` as the operator's problem). Proven by comparing hash chains emitted by SEPARATELY LAUNCHED processes, with a negative control confirming the opt-in `=random` mode genuinely disagrees. W2 CPU primary tier: `CachePolicy` (LRU + ARC) with the `ref_cnt == -1` tri-state and the ATOMIC evict, `CPUOffloadingManager` incl. the `prepare_store -> nullopt` skip control path, pinned backing store, and a side-queue event-polled device/host transfer worker. W3 disk `fs` tier: one raw file per block, temp-file + atomic rename publish, self-healing unlink, dual-queue read/write pool. **BOTH recorded upstream weaknesses are now EXCEEDED rather than merely noted** — the identity block is a VERIFIED header read on EVERY open that REFUSES on mismatch across 27 fields (tested per field, with a positive control), and the tier carries a byte budget with policy eviction honoured across restarts. `O_DIRECT` deliberately NOT ported (a header+payload file breaks its alignment requirement); the GIL-releasing batch-lookup C extension is unconditionally unnecessary without a GIL. `KV-OFFLOAD` `SPIKE` -> `PARTIAL`. **W4 IMPLEMENTED 2026-07-23:** the TIERING MANAGER (ONE manager over CPU primary + disk secondary — disk→CPU promotion RETRY→flush→HIT, cascade demotion, reset drains the secondary first and never resets it so a persisted cache survives) and the CONNECTOR/SCHEDULER HALF (`OffloadingConnector`, the semantics of `KVConnectorBase_V1`'s scheduler hooks — nullopt third state, `block_hashes` striding, load-before-compute — wired OPT-IN + DEFAULT-OFF into the scheduler). First measured offload speedup: a restarted-prefix workload through the REAL scheduler saved 32/48 prefill tokens (2/3 blocks HIT from disk), promoted bytes byte-identical to the cold store; identity refusal holds through a promotion. Ported the SEMANTICS not the Python plugin ABI (compile-time wiring); the full abstract ABI is W5. **W5 IMPLEMENTED 2026-07-23, CPU-only:** the connector seam is now a first-class C++ ABI — the abstract `KVConnector` base carrying the full scheduler + worker method set of `KVConnectorBase_V1` (the scheduler methods load-bearing, the worker hooks defaulted no-ops for our synchronous runner, documented), a compile-time `KVConnectorFactory` + `REGISTER_KV_CONNECTOR` (the C++ analogue of vLLM's `importlib` module path), and a `KVTransferConfig` selection surface (default `kv_connector` empty == no connector == zero behaviour change, `kv_role` validation, `fail`-default load policy). The W4 disk connector was refactored ONTO this base behaviour-identically — the restart-hit e2e reproduces byte-for-byte and a config-selected owning connector shortcuts prefill by the identical 32/48. `KV-CONNECTORS` `SPIKE`→`ACTIVE`. This closes the seam so LMCache client-W3 is 'implement the abstract `KVConnector` with the landed W2 `lm://` client'. **LMCACHE-CLIENT W3 LANDED 2026-07-23 — the `lm://` client wired as a `KVConnector` over the W5 seam (`LMCacheConnector`, `REGISTER_KV_CONNECTOR("LMCacheConnector", …)`, default OFF), the FIRST time the whole chain engine -> connector -> W2 client -> a running lm:// server -> back runs.** Scheduler side computes rolling-blake3 chunk hashes and `Exist`-probes the remote store for the longest cached prefix (synchronous `(n, false)`, mirroring `lmcache_connector.py:230-259`); worker `StoreChunk`/`LoadChunk` drive the W2 client with foreign-block REFUSAL. **Gate ACHIEVED = the connector-level round-trip: STORE a prefix -> a fresh "restarted" connector LOOKS UP + shortcuts prefill through the REAL scheduler (32/48 tokens saved) -> LOAD byte-identical; foreign-key REFUSAL; default-off INERT** (`test_lmcache_connector` 5 cases / 50 assertions vs an in-process mock; store->load ALSO GREEN vs a REAL `lmcache.v1.server` 8570aad, 16 assertions, `VT_LMCACHE_LIVE_*`). **LMCACHE-CLIENT W4 LANDED 2026-07-23 — REAL peer KEY-AGREEMENT + a peer->us interop LOAD, both PROVEN — the interop-correctness milestone is COMPLETE; `KV-EXTERNAL-CACHE` stays `ACTIVE` for the DGX full-model output-invariance + throughput arm.** The actual `lm://` key derivation is `ChunkedTokenDatabase` (NOT the blake3 MP hasher): chunk_size 256, a rolling prefix-hash over `(prefix_int, tuple(tokens), extra=())` keyed by vLLM's OWN hash (portable `sha256_cbor`), folded to uint64 each step, `NONE_HASH=fold8(sha256_cbor(str(PYTHONHASHSEED)))`. Mirrored byte-exact (`chunked_token_database.{h,cpp}`, reusing `CborValue`+`sha256_cbor`) and wired as connector `key_mode=kVllmSha256Cbor` (chunk 256) alongside W3's kept-green blake3 path. Key-agreement GREEN: `test_lmcache_key_agreement` 4/85 == the REAL lmcache `ChunkedTokenDatabase.process_tokens()` BYTE-FOR-BYTE (fixtures dumped from the unmodified real driver + vLLM's pinned `sha256_cbor`/`init_none_hash`), sample `meta-llama/Llama-3.1-8B@1@0@33d6862800fff40c@bfloat16`. Peer->us LOAD GREEN over the wire: a REAL lmcache `ChunkedTokenDatabase` derives a key + PUTs KV to a REAL `lmcache.v1.server`, our C++ re-derives the SAME key and GETs the 512 B byte-identical (`run_key_interop.sh`). ASan+UBSan clean. Text-only (mm-hash extra_keys deferred). **LMCACHE-CLIENT W5 LANDED 2026-07-24 — the LAST open arm, connector-ON full-model OUTPUT-INVARIANCE + throughput in a REAL generation loop, is CLOSED (spec gates 4/6 met).** The worker side is now wired into the engine: `GPUModelRunner::execute_model` calls `ConnectorLoadExternalKv` before the forward (writes the external-prefix KV into the allocated GPU blocks, load-before-compute) and `ConnectorStorePromptKv` after (stores each newly-complete prompt block), and `LoadedEngine` builds the connector from an `EngineParams` `KVTransferConfig` and wires it to BOTH the scheduler and the runner. **OUTPUT-INVARIANCE PROVEN on a real OPT-125m loop vs a live `lmcache.v1.server`: connector-ON generated tokens are BIT-IDENTICAL to connector-OFF (cold full prefill) — first-divergence index -1 — on BOTH (a) a store->restart->load cycle in one process AND (b) a genuinely cold second process that only hits the server; prefill saved on the hit = 48 tokens (3×16-token blocks).** `tests/vllm/models/test_lmcache_output_invariance.cpp` PASSES both modes via `scripts/lmcache/run_output_invariance.sh`. THROUGHPUT reported HONESTLY: on a 125M model the wall-clock delta is noise-dominated (fixed TCP/copy overhead ~ tiny compute saved), so NO binding speedup is claimed — a real speed number is owed by an every-axis grid on a larger model + long shared-prefix corpus (docs/BENCHMARKS.md). No-regression: OPT SACRED UNCHANGED default-off (6/6, 96/96, 63/63); connector unit tests green (codec 6/6, client 3/3, connector 5/5, key-agreement 4/4, kv_offload_connector 11/11); ASan+UBSan clean on the connector path; CUDA `-Werror` 0 warnings. Additive + default-off inert (all worker/loader changes are behind a null-connector guard)| `PARTIAL` | **W7 the one genuine beyond-parity item (imperative named per-sequence save/restore), which now has the verified header it depends on; and a binding every-axis LMCache throughput grid on a larger model vs vLLM's `--kv-transfer-config`.** W5 (the abstract ABI) is DONE; LMCache client W1 (codec) + W2 (client) + W3 (connector round-trip) + W4 (peer key-agreement + interop load) + W5 (full-model output-invariance) are DONE. **The benchmark blocker is CLEARED:** the caching spike's W1 prefix-cache counters landed earlier, so the W4 offload arm proved its hits | | 13a | `ROAD-V1-D4-APC` | **Prompt / prefix caching to full vLLM parity, then beyond (user-directed 2026-07-22: "same featureset of vLLM and better")** — the headline user-facing caching feature, previously mentioned only once in this roadmap despite being a shipped, default-ON behaviour for dense models | [`KV-PREFIX-CACHE`](engine-matrix.md), [`KV-BLOCK-POOL`](engine-matrix.md), [`KV-HYBRID-COORD`](engine-matrix.md), [`KV-MAMBA-ALIGN`](engine-matrix.md), [`KV-EVENTS`](engine-matrix.md), [`KV-PREFIX-MATCH-UNIT`](engine-matrix.md), [`ENG-CASCADE-ATTN`](engine-matrix.md), [coverage view §2](feature-matrix.md#2-kv-cache--memory) | umbrella spike ACCEPTED [prefix-prompt-caching-parity.md](specs/prefix-prompt-caching-parity.md) — enumerates the complete pinned-vLLM caching surface (38 features) with a per-feature DONE/PARTIAL/MISSING verdict grounded in our source. **The ported core is deeper than the record claimed** (chain hashing, block pool, all three coordinators, the full hybrid fixed-point intersection, four single-type managers); the real gaps are narrower and different: block-hash extra keys are a no-op stub, there are NO prefix-cache statistics at any level, KV events are inert, `cache_salt` and 3 of 4 hash algos are absent, and `reset_prefix_cache` is implemented but unreachable. Three matrix rows corrected, two of them in our favour. `ENG-CASCADE-ATTN` DISPOSITIONED as not owed (default-off, absent from the MRV2 runner we port, unreachable on Blackwell). llama.cpp comparison completed: its "prompt cache" is session/slot state serialization, strictly weaker than APC on every reuse axis, and vLLM already covers disk persistence via the `kv_offload` fs tier — the ONE genuine capability neither vLLM nor we have is an imperative named per-sequence save/restore **W1 IMPLEMENTED 2026-07-22: prefix-cache statistics exist for the first time.** `BaseCacheStats`/`PrefixCacheStats`/`CachingMetrics` ported 1:1 from `vllm/v1/metrics/stats.py:35-142`, recorded in `get_computed_blocks`, flagged by `reset_prefix_cache`, taken-and-swapped per step and folded into a 1000-request sliding window exposed on `Scheduler`/`EngineCore`/`LLMEngine`. Per the standing parity-enabler rule `log_stats` is DEFAULTED ON (mirroring upstream's `disable_log_stats=False`), so no benchmark arm is void for want of a counter. `Request::num_preemptions` un-deferred to feed the mutually-exclusive `preempted_*` triple. **FIRST MEASURED HIT RATE: 0.75** (1920 of 2560 queried tokens over 16 requests sharing a 128-token prefix), with a caching-OFF 0.0 negative control — the first demonstration in this project that APC actually serves cached tokens. The hard blocker on [`BACKEND-GATE-CUDA-SGLANG-PREFIX`](backend-matrix.md) is CLOSED **W2 DONE 2026-07-27 (`CLAIM-ROADMAP-D4APC`, CPU-gated on dgx GB10, NOT pushed):** `generate_block_hash_extra_keys` ported 1:1 (`kv_cache_utils.py:451-591`) — mm hash + LoRA name + `cache_salt`, fixed order lora->mm->salt (prompt_embeds deferred: no prompt-embeds path); `cache_salt`/`lora_name` carried on `Request`/`EngineCoreRequest`, set before the first hash in `FromEngineCoreRequest` (fixes a latent ordering bug). RED-first no-false-share PROVEN: with the stub a differently-salted request false-hits the prior tenant's 48 cached tokens (`n1==48`), with extra keys `n1==0`. Ported extra-key/ordering cases + hash- and manager-level no-false-share (`test_kv_cache_utils.cpp` 29/29, `test_kv_cache_manager.cpp` 10/10). **This unblocks the MM + LoRA cache consumers.** **W3 DONE 2026-07-27 (`CLAIM-ROADMAP-D4APC-W3`, dgx GB10, NOT pushed) — the FIRST-EVER cache-ON model gate:** on `Qwen/Qwen3-4B` (dense, full-attention, APC-default-ON — the vehicle the prior "vehicle-blocked" note missed) a shared-prefix workload runs APC-ON and APC-OFF through the full paged engine, gating token-identity + hits + prefill drop. **NO engine code changed** (`git diff --stat` = tests+scripts+goldens) ⇒ pure GATE over the already-shipped default-ON path; binary byte-identical ⇒ SACRED unaffected. RESULT (`test_qwen3_apc_e2e` 2/2, 84/84 asserts): APC-ON hits **2240/2777 (rate 0.807)**, APC-OFF 0; APC-ON == APC-OFF EXACT on 5/6 (the 1 diff a vLLM-confirmed 0.125-nat near-tie, RCA'd = attention-kernel-path near-tie flip, not a cache bug); **== vLLM-APC-ON** teacher-forced (APC-OFF 6/6 max gap 0.0 nats = exact argmax, APC-ON 6/6 max gap 0.125 nats, 0 outside top-20); **TTFT drop 70.1→39.9 ms = 1.76×** on a cache hit. Existing 4B SACRED gate 16/16 GREEN (no regression). Oracle vLLM 0.25.0 (0.26 venv broken — editable source disk-reclaimed; 4B byte-stable across the pin). | `DONE` (headline) | **Row DONE for the default dense APC path (block hashing incl. extra_keys, pool, coordinators, stats, scheduling, cache-ON e2e all gated).** Named NON-BLOCKING tails tracked in their own rows / future items: W4 KV events (`KV-EVENTS` — event GENERATION + `msgpack` PAYLOAD DONE 2026-07-27 `CLAIM-ROADMAP-D4-KV-EVENTS`, `SPIKE`→`ACTIVE`, byte-exact vs `msgspec`; live ZMQ transport + engine batch wiring DEFERRED), W5 partial-block primitive (upstream dead-code), W6 Mamba-`align` hybrid cache-on (`KV-MAMBA-ALIGN`, SPIKE — feeds `BACKEND-GATE-CUDA-SGLANG-PREFIX`), W7 `reset_prefix_cache` dev-endpoint + `--prefix-caching-hash-algo` + `skip_reading_prefix_cache`, W8/W9 the beyond-vLLM named session save/restore. The every-axis cache-on grid vs vLLM/SGLang is a separate perf follow-on under `ROAD-V1-A`. No `/metrics` route yet (`SERVE-METRICS`), so the hit rate is read from the engine API. **`--prefix-match-unit` (0.26-new fine-grained matching unit) W0 spike + W1 resolver LANDED 2026-07-28 (`CLAIM-PREFIX-MATCH-UNIT`, `KV-PREFIX-MATCH-UNIT` PARTIAL): `resolve_kv_cache_block_sizes` computes `hash_block_size = prefix_match_unit if set else gcd(group_block_sizes)`, RED-first unit-gated; config/CLI/ABI field (W2) + scheduler threading of `hash_block_size != block_size` (W3, needs the `KV-BLOCK-POOL` align path) + benchmark (W4) deferred.** | | 14 | `ROAD-V1-D5` | LoRA, local KV/weight offload, expert streaming, wider model zoo | [engine matrix](engine-matrix.md), [model matrix](model-matrix.md) | corrected expert-streaming spike accepted (`ENG-EXPERT-STREAM` READY): bank-only safetensors→Marlin bank, fixed contiguous cache slots matching Marlin dense strides, logical→slot remap after explicit router D2H, chunked C HW/loader-forced-indirect. | | 15 | `ROAD-V1-D6` | **llama.cpp device breadth folded into scope (user-directed 2026-08-05):** the 11 ggml backends vLLM has no platform for — cann, musa, opencl, openvino, rpc, webgpu, zdnn, zendnn, hexagon, blas, virtgpu — inventoried as `BACKEND-GGML-*`. **SPIKES FIRST:** no implementation before each row's `.agents/specs/.md` clears the spike contract, per the standing directive. vLLM stays the mirror source; llama.cpp is the breadth reference. | [backend matrix](backend-matrix.md) | ☐ per-row spike required | `INVENTORIED` | first spike accepted | An area row cannot enter `READY` without a real spike under `specs/`, and cannot diff --git a/.agents/specs/minimax-h3.md b/.agents/specs/minimax-h3.md index bce2d0e19..0c578861a 100644 --- a/.agents/specs/minimax-h3.md +++ b/.agents/specs/minimax-h3.md @@ -313,3 +313,137 @@ covers only the vLLM repo; H3 lives outside it. (b) The MP4 dependency decision. (c) Hardware: nothing past W2b/W3 can be END-TO-END gated on this project's boxes, so W4-W8 should be reviewed as structural ports with unit gates, and the honest lifecycle cap for this row is "correctness-complete, hardware-blocked". + +## 8. W-FP4 — the fp4 SPEED path (row `row/H3-FP4-SPEED`, 2026-08-06) + +Until this change the NVFP4 arm ran the DiT projections in **bf16**: both the +reference loader (`LoadMiniMaxH3DitFromNvfp4`) and the streaming stager +(`StreamMiniMaxH3Nvfp4ToDeviceBf16`) DEQUANTIZE every packed FP4 weight to bf16 and +the device forward calls `vt::MatmulBT`. The sm_121a FP4 tensor-core route had +never actually run for H3. W-FP4a wires it. + +### 8.1 W-FP4a — per-shape routing table (grounded in `dense_nvfp4_gemm.h`) + +The `lilcheaty/MiniMax-H3-NVFP4` checkpoint is **weight-only NVFP4 (W4A16)**: every +quantized projection carries only `weight` (U8 E2M1) + `weight_scale` (E4M3, group +16) + `weight_scale_2` (F32) and **no `input_activations`** (confirmed +`minimax_h3_nvfp4.cpp:63-76` and the real manifest, spec §4). Per the dispatcher's +own contract (`dense_nvfp4_gemm.h:12-22`, mirroring vLLM +`kernels/linear/__init__.py:879-881` — *"Force a16 (Marlin) when running +weight-only quantization"*), a W4A16 weight (`Nvfp4Weight::IsTrueW4A4()==false`, +alpha==0) is **forced to the Marlin W4A16 grouped GEMM**, bypassing the +capability-based kernel registry. So on sm_121a **every quantized H3 projection +takes the SAME kernel** — `dense_nvfp4::MatmulNvfp4MarlinD` (single-expert +`vt::MoeGroupedGemmNvfp4Marlin`), the exact path the Laguna routed-experts +(`laguna.cpp`) and the dense Qwen3-32B NVFP4 arm (`qwen3_5.cpp`) use. The +cutlass-FP4 / true-W4A4 route (`MatmulNvfp4Fp4D`) is NOT taken here: it needs fp4 +ACTIVATIONS this checkpoint does not carry, and is deliberately private to +`qwen3_5.cpp` (`dense_nvfp4_gemm.h:12-18`). + +Real geometry: H=5376, ffn=14336, heads=56×128 (inner=7168), time_embed_dim=2688, +text_dim=5120, adaln_out=18·H=96768, final_adaln=2·H=10752. + +| Projection (per layer unless noted) | `[N, K]` | Route | Why (file:line) | +|---|---|---|---| +| `attn.qkv_proj` | `[21504, 5376]` | **Marlin W4A16** | W4A16 forced-Marlin `dense_nvfp4_gemm.h:512-525` | +| `attn.out_proj` | `[5376, 7168]` | **Marlin W4A16** | same | +| `mlp.fc1` (merged `[gate;up]`) | `[28672, 5376]` | **Marlin W4A16** → `SiluAndMul` | fc1 is ALREADY merged, so ONE GEMM to `[M,2·ffn]` then `vt::SiluAndMul`; the fused-pair `GateUpFusedMarlinD` does NOT apply (no separate gate/up shards) — `minimax_h3_device.cpp` `MlpDev` | +| `mlp.fc2` | `[5376, 14336]` | **Marlin W4A16** | same | +| `adaln_proj.linear` (block) | `[96768, 2688]` | **Marlin W4A16** (+ bias `vt::Add`) | skinny-M (M=num_unique_timesteps): Marlin `block=8` dense tile at M≤8, `dense_nvfp4_gemm.h:273-286` | +| `condition_proj` | `[5376, 5120]` | **Marlin W4A16** (+ bias) | embed, once | +| `final_layer.adaln_proj.linear` | `[10752, 2688]` | **Marlin W4A16** (+ bias) | final, once | +| refiner `qkv/out/fc1/fc2` (×2) | same as block | **Marlin W4A16** | refiner has no adaln | +| **islands** (`video/audio_patch_proj`, `time_embedder.*`, `final_layer.{video,audio}_out`) + all norms/biases | — | **`vt::MatmulBT` bf16 / f32 (unchanged)** | fp32 island policy (`minimax_h3_transformer.py:85-101`); never quantized in the checkpoint | + +All N and K are multiples of 16 (group) and of 128 (Marlin tile) — no shape blocker. +The activation MUST be bf16 for the Marlin path; in the bf16 production stream it is, +so the fp4 arm pairs with the bf16 stream. In the f32 parity stream (or any backend +without the Marlin op — e.g. CPU) the SAME dispatcher falls back to a +redundant-dequant GEMM, so the arm is correct either way, fast only where Marlin is +realized (kCUDA sm_121a). + +**Implementation (this change, NO new quant code):** `Nvfp4Weight` fp4 carriers on +`MiniMaxH3DitBlockWeights`/`MiniMaxH3DitWeights`; a new fp4-resident streamer +`StreamMiniMaxH3Nvfp4ToDeviceFp4` (keeps packed FP4 host-resident, dispatcher +uploads + repacks lazily on first forward, then frees the fp4 originals — peak +device memory ~1/4 of the bf16 arm: ~16 GB packed vs ~66 GB bf16); `LinearDev` +routes a non-Empty fp4 weight through `dense_nvfp4::MatmulNvfp4W4A16D`. + +**Gate.** CPU: `test_minimax_h3` "an NVFP4 checkpoint loads into a runnable DiT" now +also streams the fp4 twin, asserts the loader kept the projections PACKED (fp4 slot +set, bf16 slot Empty), runs the fp4 and bf16 device forwards on the SAME synthetic +NVFP4 file, asserts the W4A16 dispatcher executed all 11 quantized GEMMs (the +"this-path-ran" counter), and bounds the fp4-vs-bf16 delta. On CPU the dispatcher +has no Marlin op so it falls to the bf16 arm's own dequant+matmul — this is a +**wiring** gate here. The Marlin kernel's real numeric behaviour is CUDA-gated +independently by `test_ops_nvfp4_matmul` / `test_linear_method` (2e-3/8e-3 vs a +bf16 reference). **GB10 leg (fp4-vs-bf16 numeric delta + per-step timing at real +geometry): PENDING** — see §8.3. + +### 8.2 Supports-audit vs vLLM-Omni (source-pinned to `a4ea67a2`, v0.26.0) + +vLLM-Omni H3 modules at `vllm_omni/diffusion/models/minimax_h3/`; serving in +`vllm_omni/entrypoints/openai/`. + +| Capability | vLLM-Omni (file:line) | Ours (file:line) | Verdict | +|---|---|---|---| +| Async video route `POST /v1/videos` | `api_server.py:3146` | `ApiServer` `/v1/videos` (W7, `minimax_h3` serving) | **DONE** | +| Sync route `POST /v1/videos/sync` | `api_server.py:3189` | `/v1/videos/sync` | **DONE** | +| Status `GET /v1/videos/{id}` | `api_server.py:3305` | registered | **DONE** | +| List / DELETE / `/content` download | `api_server.py:3268,3333,3385` | — | **MISSING** (list/delete/content-GET) | +| WebSocket `/v1/video/chat/stream`, `/v1/realtime/video` | `api_server.py:1593,1610` | — | **MISSING** (streaming/realtime) | +| Request schema (prompt, size/w/h, num_frames, fps, seed, steps, refs) | `protocol/videos.py:97-249` | request contract (W7) | **PARTIAL** (core fields; frame-interp/lora/generate_sound absent) | +| H3 knobs via `extra_params.{task,duration,flow_shift,audio_flow_shift}` | `pipeline:1034,403,1157-1158` | planner reads task/duration/shift | **DONE** | +| Modalities in: text/image/video/audio | `pipeline:1036-1104` | t2va (text) done; fl2va/ref2va image/video/audio WIRED (W6/ref2va) | **PARTIAL** (encoder vision tower still open) | +| Output: joint video+audio, 24 fps, 32 kHz stereo | `pipeline:106-111,1187` | frames + WAV + MP4 mux (W7) | **DONE** | +| Scheduler: euler-ancestral rectified flow (single) | `scheduling_...euler_ancestral.py`; `time_request.py:34-61` | `MiniMaxH3EulerEta0Step` / `MiniMaxH3TimeShiftSigmas` | **DONE** | +| CFG: distilled, no CFG (guidance params accepted+ignored; `cfg_parallel_size==1`) | `pipeline:250,275-276` | no CFG branch | **DONE** (matches) | +| Res/frame bounds: mult-32, aspect 1:4–4:1, 17n+5 frames, 24 fps, canvas 768×1344 | `pipeline:399-430`, `time_request.py:5-31` | request planner (17n+5, canvas, sigma) EXACT | **DONE** | +| Task dispatch t2va/fl2va/ref2va | `pipeline:374-391` | planner dispatch (W6a) | **DONE** | +| Single-GPU serving | `--num-gpus 1 --enable-cpu-offload` (`recipe:53-74`) | single GB10, quantized-resident | **DONE (ours needs no offload — quantized fits)** | +| USP / DiT-TP / VAE patch-parallel | `pipeline` collectives (throughput) | `vt::communicator`/NCCL present, USP not ported (W8) | **MISSING** (multi-GPU only) | + +### 8.3 Speed statement + comparability verdict (mission #3) + +**vLLM-Omni CANNOT serve a quantized H3 on one GPU** (source-pinned, spec-audited): +it is **BF16-only in practice**. The generic diffusion framework has ModelOpt +FP8/NVFP4 plumbing and the H3 DiT forwards a `quant_config` to vLLM quant-capable +linears, but (i) **no quantized H3 checkpoint exists or is referenced** anywhere in +the repo; (ii) the fp32-island guard `post_load_weights()` (`minimax_h3_transformer.py:898-904`) +**raises** if the patch/time/output layers are not fp32, so a naive blanket quant +aborts; (iii) the **text encoder is hard-coded bf16** (`encoder.py:930`, no +quant_config) and the **VAEs load unquantized**; (iv) GGUF is **not wired into H3's +bespoke `load_weights`** at all. Single-GPU IS supported — but as **BF16 + +`--enable-cpu-offload`** (`recipe:53-74`). + +**Therefore the comparison is HW/loader-FORCED-INDIRECT** (the DeepSeek-GGUF +precedent): a like-for-like quant-matched vllm-omni run on one GB10 is impossible +because vllm-omni has no quantized H3 arm. The honest baselines are our own bf16 +arm (`StreamMiniMaxH3Nvfp4ToDeviceBf16`) and the portable path; vLLM-Omni's own best +published numbers are **4× B300 BF16**. + +**Honesty correction on the "88%":** the *"DiT ≈ 88% of request latency on 4× B300"* +figure is **NOT documented anywhere in the vllm-omni checkout** (exhaustive grep). +The real documented anchor is the recipe's *"Validated four-GPU evidence"* +(`recipes/MiniMaxAI/MiniMax-H3.md:298-311`): FL2VA 209-frame 1248×768 = **86.964 s** +mean client latency on 4× B300; two-video Ref2VA 362-frame = **784.394 s**. The DiT +`diffuse` stage share is measurable per-request (`pipeline:255-262`) but no fixed +percentage is written down. The upstream **reference config** is 50 steps, 24 fps, +video flow_shift 12 / audio 3, no CFG; default canvas **768×1344**, default frames +**209** (t2va/fl2va) / **124** (ref2va) — NOT the "864×480 / 124" in the task brief. + +### 8.4 Status (this row) + +- **W-FP4a: CPU-LANDED + gated** — fp4-resident loader + Marlin-W4A16 routing + the + fp4-vs-bf16 wiring gate. No new quant code. +- **W-FP4a GB10 leg: PENDING** — build the CUDA `test_minimax_h3` on dgx.casa, + run the CUDA `an NVFP4 checkpoint loads into a runnable DiT` case (the same gate + exercises the Marlin path via `marlin_gemms`), and capture the fp4-vs-bf16 delta + + steady per-step time. Gated on a safe disk/build window (dgx: 33 G free vs 15 G + floor; the 570 G shared `.cache` is not ours to prune). +- **W-FP4b real-checkpoint t2va e2e: DISK-BLOCKED.** The NVFP4 arm working set is + DiT + Qwen3-VL-32B NVFP4 encoder + both VAEs (~41 GB+ on disk to download); with + ~18 GB usable above the disk floor it does not fit, and the encoder is required + for a real conditioned render. Recorded HW/disk-forced-indirect. A DiT-only + steady-per-step at real geometry (fp4 vs bf16) is the reachable speed number once + a single NVFP4 DiT variant download fits. diff --git a/.agents/state.md b/.agents/state.md index 34c57224f..7eb2ebf2b 100644 --- a/.agents/state.md +++ b/.agents/state.md @@ -39232,3 +39232,46 @@ were mapped the same way (body cross-references of duplicated stamps map to the first occurrence). The DATES are now evidence-true; the intra-day minutes on corrected entries are synthetic ordering values, not measured times. No cited SHA changed. + + +## 2026-08-06T14:19 - MiniMax-H3 W-FP4a: fp4-resident Marlin-W4A16 routing (CPU-landed) + + +Row `row/H3-FP4-SPEED` (helper, `ROAD-V1-H3`). The H3 NVFP4 arm ran the DiT +projections in BF16 (both loaders dequantized packed FP4 -> bf16, forward called +`vt::MatmulBT`), so the sm_121a FP4 tensor-core route had never run for H3. + +W-FP4a wires it, adding NO quant code. The `lilcheaty/MiniMax-H3-NVFP4` checkpoint +is weight-only W4A16 (no `input_activations`), so per the landed dispatcher +`dense_nvfp4_gemm.h:12-22,512-525` (mirroring vLLM `__init__.py:879-881` +forced-Marlin for a16) EVERY quantized projection routes UNIFORMLY through +`dense_nvfp4::MatmulNvfp4W4A16D` = Marlin W4A16 single-expert — the SAME kernel +the Laguna routed-expert + dense-Qwen3-32B NVFP4 arms use. NOT cutlass-fp4/W4A4 +(that needs fp4 activations this checkpoint lacks). fc1 is pre-merged `[gate;up]`, +so it is ONE W4A16 GEMM + SiluAndMul (the fused-pair path does not apply). Islands +(patch/time/output heads) + norms/biases stay bf16/f32 unchanged. + +Change: `Nvfp4Weight` carriers on the block/DiT weight structs; new fp4-resident +streamer `StreamMiniMaxH3Nvfp4ToDeviceFp4` (keeps packed FP4 host-resident, +dispatcher uploads+repacks lazily, peak device mem ~1/4 of bf16: ~16 GB vs ~66 GB); +`LinearDev` dispatch. Files: `include/.../minimax_h3.h`, +`src/.../minimax_h3_device.cpp`, `tests/.../test_minimax_h3.cpp`, spec §8. + +Gate (CPU, verified): `test_minimax_h3` 62/62 cases, 30039 assertions, 0 failed. +The NVFP4 case streams the fp4 twin, asserts the loader kept projections PACKED +(fp4 slot set / bf16 slot Empty), runs fp4 + bf16 device forwards on the SAME +synthetic file, asserts the W4A16 dispatcher executed all 11 quantized GEMMs +(the this-path-ran counter), and bounds fp4-vs-bf16 <= 2e-3. On CPU the dispatcher +has no Marlin op -> falls to the bf16 arm's own dequant+matmul, so this is a WIRING +gate; the Marlin kernel numerics are CUDA-gated independently by +`test_ops_nvfp4_matmul`/`test_linear_method` (2e-3/8e-3). + +PENDING (handoff): (1) GB10 build of CUDA `test_minimax_h3` on dgx.casa + run the +NVFP4 case (exercises Marlin via `marlin_gemms`), capturing the real fp4-vs-bf16 +delta + steady per-step time. Blocked on a safe disk/build window (dgx 33 G free +vs 15 G floor; 570 G `.cache` is shared, not ours). (2) Real-checkpoint t2va e2e is +DISK-BLOCKED: NVFP4 working set (DiT + Qwen3-VL-32B NVFP4 encoder + 2 VAEs) is +~41 GB+ to download vs ~18 GB usable, and the encoder is required for a real +render. Comparability: vLLM-Omni CANNOT serve a quantized H3 on one GPU +(BF16-only in practice; source-audited `a4ea67a2`) -> HW/loader-forced-indirect, +DeepSeek-GGUF precedent. Draft PR is the claim. diff --git a/docs/BENCHMARKS.md b/docs/BENCHMARKS.md index 5178544aa..5a7e8121e 100644 --- a/docs/BENCHMARKS.md +++ b/docs/BENCHMARKS.md @@ -296,6 +296,7 @@ built on it rather than keeping the flattering one. | Qwen3-dense decode CUDA-graph | Token-exact pass, ~4.3% e2e directional | Steady-state per-step tok/s | | Kimi-Linear-48B-A3B (KDA+MLA+MoE) | Full-model GB10 e2e RUNS (bf16-resident §13), NEAR-TIE 106/128, pool math CLOSES; default OFF | Full model RUNS on GB10 (bf16-resident, RSS peak 1.7 GiB, min-avail 21 GiB, no OOM). Token NEAR-TIE 106/128 (6/8 prompts exact, numerics vs deterministic oracle). 1.59 tok/s. Detail: spec §13 | | vLLM 0.26 re-benchmark | Pending | Re-run the binding grids on the advanced pin | +| MiniMax-H3 FP4 speed (W-FP4a) | Pending. fp4-resident Marlin-W4A16 routing CPU-landed (62/62); GB10 delta + per-step unmeasured (disk window); real e2e disk-blocked; vLLM-Omni has no quantized H3 (BF16-only) | Build CUDA `test_minimax_h3` on dgx, run the NVFP4 case (Marlin via `marlin_gemms`), capture delta + s/step. Detail: benchmark-record + spec §8 | | MXFP4 Qwen3-8B (W4A16 Marlin) | **`KERNEL-MARLIN-DENSE-EXEC` x3 (dense-ON default): c1 1.020, c2/c4/c8 0.962/0.966/0.969, GPU mem 2.63x less** (beats #51 1.005/0.925/0.939/0.953 EVERY axis); #44 3/3, 32B-NVFP4A16 6/6; -Werror test-guard fixes x2 | **VT_MARLIN_DENSE default-ON**. `QUANT-CT-MXFP4-FINAL-STACK` TERMINAL: 2 last levers exhausted (num_splits cap gated-OFF c1-only; glue folds via FusedChain, residual out-of-catalog). c2-c8 GPU-intrinsic; see record | | SGLang floor arms | Never ran | Both arms of the SGLang comparison | | cuBLAS invocation-parity guard | CI guard landed (CPU); `kGemvHeuristicAlgos` refactor build-verify owed | `nvcc` rebuild + SACRED gate on dgx | diff --git a/docs/FEATURES.md b/docs/FEATURES.md index 7914dda84..b1a30412d 100644 --- a/docs/FEATURES.md +++ b/docs/FEATURES.md @@ -115,7 +115,7 @@ oversight. | Image | ✅ correctness-gated | ✅ | ✅ | ◐ | | Video | ✅ correctness-gated | ✅ | ✅ | ☐ | | Audio | ✅ correctness-gated | ✅ | ◐ | ◐ | -| Video+audio GENERATION (MiniMax-H3 DiT, vLLM-Omni lane) | ◐ portable path complete; e2e on real weights (Thor); FP4 speed sm_121-pending | ✅ (vllm-omni) | ☐ | ☐ | +| Video+audio GENERATION (MiniMax-H3 DiT, vLLM-Omni lane) | ◐ portable path complete; e2e on real weights (Thor); FP4-resident Marlin-W4A16 routing CPU-landed, GB10 speed pending | ✅ (vllm-omni, BF16-only, no quantized H3 arm) | ☐ | ☐ | | Multimodal over the OpenAI server | ☐ | ✅ | ✅ | ◐ | Image, video and audio are correct through the CLI and library. Serving them diff --git a/docs/STATUS.md b/docs/STATUS.md index 728152704..1daac77a0 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -73,7 +73,7 @@ token-for-token correctness against the pinned oracle. | OLMo-3 dense (dual rope, interleaved sliding window) | Implemented, oracle-blocked | Loads + runs in our engine (dual rope: plain sliding + YaRN full-attn, per-layer sliding window); no SACRED gate: vLLM 0.25.0 oracle cannot run OLMo-3-1025-7B (`KeyError: 'rope_theta'`; transformers 5.13.1 nests `rope_parameters` per layer-type, no flat `rope_theta`; run-verified W0 2026-07-26) | | Laguna-S-2.1 MoE (`LagunaForCausalLM`, 118B/8B) | **BINDING 2026-08-04: 87% of vLLM (37.55 vs 43.10, SAME-TOOL nsys both engines); the whole +3.1 ms/step is the bf16 M=1 GEMV bucket (2/3 o_proj, ~196-204 vs 139 us/call, identical `gemvx` kernel); attention/MoE/glue tied or ours-ahead. Invocation match (bf16-out `cublasGemmEx`) A/B'd = WASH, ruled out; ROOT CAUSE FOUND 2026-08-04 (`VT_LAGUNA_RESIDENT_BF16W`): the bf16 projections read UNIFIED/ATS host memory, not `cudaMalloc`'d device memory — staging them device-resident (byte-exact ids) gives 38.8→44.6 tok/s (o_proj 194→131, lm_head 2410→1620 us/call), parity+ vs vLLM 43.1; **default-ON** (flip smoke-verified: canonical byte-exact ids, 44.6 clean-median). Earlier ceiling/diffuse verdicts below were cross-tool artifacts.** **REAL vLLM BAR ESTABLISHED (2026-07-31, `CLAIM-LAGUNA-VLLM-NVFP4`): FIRST-EVER vLLM Laguna run** — prior numbers (incl. the correctness oracle) were all llama.cpp, never vLLM. vLLM on official `poolside/Laguna-S-2.1-NVFP4` (single GB10, greedy, eager, MARLIN backend forced via `VLLM_TEST_FORCE_FP8_MARLIN=1` because the auto-default `FLASHINFER_CUTLASS` needs an absent `nvcc`): **~18.8 tok/s** (64-tok steady) — a LOWER bound. Our GGUF-Q4_K engine = 7.7 tok/s (vLLM ~2.4×); llama.cpp GGUF = 27.8 (still fastest at batch-1). llama.cpp is now a labeled SECONDARY "beat best-in-class GGUF" note; vLLM-NVFP4 is the headline bar. TRUE apples-to-apple still owes OUR NVFP4 Laguna forward arm (same tensor-core path as 27B/35B) — bring-up W-plan SPEC'D in `.agents/specs/laguna-nvfp4-arm-2026-07-31.md` (~85% reuse of the 35B NVFP4 W4A4 MoE infra + a name-map; bf16 attn/dense + fp4 experts; N1-N5 bricks, DGX-gated). **N1-scaffold LANDED (2026-07-31):** additive `LagunaMoeWeights.experts_{gate,up,down}_fp4` + `shared_{gate,up,down}_fp4` (`Nvfp4Weight`, mirror qwen3_5), dead until the N1 loader; CPU build clean + `test_laguna_scaffold` 8/8·167 unchanged. **N1b loader IMPLEMENTED (2026-07-31, build-verified):** `LoadLagunaForCausalLMWeights` (`laguna_weights.cpp`) replaces the `VT_CHECK(false)` stub — resolver + per-layer `LoadBf16Direct` (attn/dense/norms/embed/lm_head/router/shared-expert) + F32 `e_score_correction_bias` + `LnLoadCtNvfp4Raw` W4A4 experts. Name-map + dtypes VERIFIED against the real `poolside/Laguna-S-2.1-NVFP4` index (router `mlp.gate` BF16, bias F32, experts W4A4, shared-expert BF16). **N1b RUN-VERIFIED (2026-07-31):** loader round-trips a synthetic NVFP4 checkpoint byte-identically (`test_laguna_nvfp4_loader` 2/2·29; full detail in the benchmark record). **N2 FORWARD-BRANCH LANDED + CPU-GATED (2026-07-31):** `LqGemmNvfp4Fp4` (per-expert TRUE-W4A4: `ScaledFp4Quant(input_global_scale_inv)`→`MatmulNvfp4Fp4(alpha)`, unified-memory pattern like `LqGemm`) + `LagunaFfnBlock` branches on `fp4=!experts_gate_fp4.empty()` (routed experts fp4; keep-quant grouped fast-path gated off `!fp4`; bf16 attn/dense/router/shared-expert/lm_head unchanged) + both `LagunaForwardGguf{,Cached}` guards relaxed to `has_gguf_weights||has_nvfp4_weights`. **CORRECTION:** routed experts are W4A4 ⇒ per-expert `MatmulNvfp4Fp4`, NOT the grouped W4A16 `MoeGroupedGemmNvfp4` (grouped W4A4 deferred to N5 speed). `test_laguna_nvfp4_loader` 3/3·61 (added a forward run-gate: fp4 MoE branch runs through the real `LagunaForwardGguf` → finite+deterministic logits + routed-experts-consumed); `test_laguna_scaffold` 8/8 unchanged (GGUF byte-identical). **N3 DRIVER LANDED + CPU-SMOKE-VERIFIED (2026-07-31):** `examples/laguna_gen` auto-detects a safetensors DIRECTORY (→ NVFP4: `LoadHfConfig(config.json)` + `LoadLagunaForCausalLMWeights` + `LagunaForwardGguf{,Cached}`) vs a `.gguf` FILE (→ keep-quant), sharing the greedy loop; `--token-ids` bypass the tokenizer for the id-vs-golden gate. Verified on a synthetic NVFP4 dir with a REAL config.json (exercises the `LoadHfConfig`→`ParseLagunaParams` seam the loader test bypassed) → `has_nvfp4=1`, KV-cache decode runs finite. **N4 RAN on GB10 (2026-08-01) — the arm works end-to-end; correctness coherent+near-tie, speed 120× off.** git-archived `84fab587` → clean CUDA build (`121a`) → `laguna-gen --gpu` on the real 67 GiB `ckpt` with vLLM's exact prompt ids injected (`2,785,9626,377,15360,395`, captured via the HF tokenizer). Two GB10 memory fixes landed to run: release the mmap'd shards after the loader's memcpy-copy (114→67 GiB RSS), and create the CUDA context BEFORE the load (the 67 GiB reclaimable page cache otherwise starves `cudaStreamCreate`). **Correctness:** ours `22345 83 350 71070 395 340 9626 372 1703 …` vs golden `22345 83 290 350 674 330 5541 966 340 9626 377 15360 …` — **first 2 tokens match vLLM exactly**, then near-tie divergence; coherent ("France is" = 9626/377/15360; shares golden vocab). EXPECTED: our TRUE-W4A4 (fp4 activations) vs the MARLIN golden's W4A16 (bf16 activations) — different precision, not a bug. **Speed: 6.34 s/tok (0.16 tok/s), prefill 17.3s — ~120× slower than vLLM 18.8.** ROOT CAUSE (source-confirmed): `LqGemmNvfp4Fp4` uses the generic `vt::MatmulNvfp4Fp4` = the hand-written EMULATION CUDA kernel, NOT the cutlass sm120a fp4 tensor-core path the 27B/35B W4A4 use (`MatmulNvfp4Fp4DirectD`); + per-expert loop + per-GEMM host sync + no device residency. **nsys (2026-08-01) trace-confirmed + refined:** only 2 GPU kernels — `MatmulNvfp4Fp4Naive` = 99.3% of GPU time + fp4-quant 0.7%; GPU busy only ~18% of wall. NO bf16 GEMM on the GPU ⇒ `LqGemm`'s bf16 branch runs the host `MatmulNK` reference on the CUDA queue (attention/dense/router/shared/lm_head are CPU-bound, ~4.8 s/tok) — a second lever the source scan missed. **N5 LEVER #2 LANDED (2026-08-01) — 16× decode.** Routed the bf16 tower (attention/dense/router/shared/lm_head) off the host `MatmulNK` onto the GPU (`LqGemm` bf16 branch: `vt::CastBf16` the small activation + `vt::MatmulBT` bf16×bf16→f32, weight stays bf16 — no per-token `ReadF32` of `lm_head [100352,H]`): **decode 6.34 → 0.39 s/tok (16.3×; 0.16 → 2.56 tok/s), prefill 17.3 → 2.24s**; coherence preserved (near-tie). CPU path unchanged (run-gate byte-identical). **N5 LEVER #1 LANDED (2026-08-01) — native fp4 tensor-core, another ~2×.** The engine's native sm120a fp4 tensor-core MMA (`MatmulNvfp4Fp4Native`, `mma.sync kind::mxf4nvf4`) reads the same linear scale layout `LqGemmNvfp4Fp4` produces — it was gated OFF behind `VT_NVFP4_FP4_NATIVE`; the Laguna driver now defaults it ON (scoped; 27B/35B untouched). **decode 0.39 → ~0.20-0.24 s/tok (~2×; ~4.2-5.0 tok/s)**; coherent (byte-identical ids to the emulation path — numerically equivalent), first token matches the golden. **Cumulative N5: 0.16 → ~4.5 tok/s (~28×), now ~4× from vLLM 18.8.** **Device-resident MoE block LANDED + MEASURED (2026-08-01, `LagunaMoeResidentFp4`, `VT_LAGUNA_RESIDENT_MOE` default-ON):** the whole token's routed experts as ONE async device chain (fp4-quant→GEMM gate/up, `MoeSiluMul`, →down stacked, ONE `MoeCombine`), draining once vs ~Pk×3 syncs. **Speed EAGER-NEUTRAL (0.20 s/tok)** — empirically confirms the ds4 precedent (per-op syncs overlap GPU compute; wall is GPU-serial-bound; the graph is the payoff). **CORRECTNESS WIN: golden-token match 2 → 13** (the device `MoeSiluMul`/`MoeCombine` mirror vLLM's fused MoE faithfully). Lands default-ON (better correctness, no speed cost, graph prerequisite). **CORRECTED CEILING (from the measured state): a perfect decode graph caps at ~5.9 tok/s** (GPU already ~87% busy at 0.20 s/tok), still 3.3× short of vLLM 18.8 — the graph is necessary but NOT sufficient; the remaining 3.3× is KERNEL EFFICIENCY (native fp4 MMA ~302µs/M=1 expert GEMM vs vLLM's tuned cutlass sm120a fp4 + fused norm/quant/silu). Parity = TWO campaigns: (A) device-resident+graph → ~5.9; (B) cutlass DirectD experts + fused ops + M=1-tuned GEMV → the rest. **CAMPAIGN-B FIRST BRICK LANDED (2026-08-01): coalesced M=1 fp4 GEMV** (`MatmulNvfp4Fp4Gemv`, one warp/column, coalesced weight-row reads, `VT_NVFP4_FP4_GEMV` default-ON) — same-binary A/B: **decode 0.20 → 0.15 s/tok (1.33×; → ~6.7 tok/s), prefill 1.14 → 0.86s**, coherent+near-tie. **Cumulative this session: 0.16 → ~6.7 tok/s (~42×), now ~2.8× from vLLM 18.8.** (ILP variant `kCpw=4` measured SLOWER — 0.21 s/tok, occupancy loss > activation-reuse gain — reverted to `kCpw=1`; kernel kept templated as a re-measurable knob.) **ncu of the GEMV (sudo): sm__throughput 35-71%, DRAM n/a — COMPUTE/LATENCY-bound, not BW-bound.** Corrects the earlier "~6× BW → ~16-17 tok/s" estimate: the next GEMV lever is HARDWARE fp4 dequant (`cvt.e2m1x2`), not more bandwidth. Parity (18.8) is a multi-brick campaign (decode graph + fused norm/quant + hardware-dequant GEMV), not one more kernel. **B0 hw-fp8 SCALE-decode: MEASURED NEGATIVE, reverted (2026-08-01, `ab7a1c1e`).** Replacing the GEMV's per-byte software fp8-e4m3 group-scale decode (`F8E4M3ToF32Dev`/`ldexpf`) with hardware `cvt.rn.f16.e4m3` (`__nv_fp8_e4m3`→float) is bit-exact (ids byte-identical on the real ckpt) but paging-immune ncu shows it NEUTRAL-to-slightly-WORSE (grid768 41.2 vs 41.9µs tie; mean 53.6 vs 49.4µs) — GPU `ldexpf` is a cheap exponent-bit add, not a libcall. NOTE this is the fp8 SCALE decode, NOT the fp4-e2m1 WEIGHT dequant (the `kE2M1` `__constant__` LUT); the LUT→arithmetic/`cvt.e2m1x2` weight-dequant is a SEPARATE still-open lever (spec brick B1). Also: end-to-end wall-clock is unusable for kernel A/B here (67 GiB unified reload swings TPOT 0.16↔1.08 s/tok run-to-run) — kernel-duration ncu is the only honest anchor. **★ B2 SCOPED + DE-RISKED (2026-08-01, zero-DGX) — the real 18.8 lever:** vLLM's 18.8 bar is MARLIN W4A16 (`VLLM_TEST_FORCE_FP8_MARLIN=1`), which is LOW-M-optimized (decode-correct, unlike a tensor-core W4A4 GEMM that wastes M=1 tile rows). The engine already ships the EXACT kernel `vt::MoeGroupedGemmNvfp4Marlin` (1:1 lift of vLLM `moe_wna16_marlin_gemm`) + shared `MarlinRepackExpertWeight`, and qwen3_5 (27B/35B) already routes its NVFP4 experts through it (default-ON `VT_NVFP4_MARLIN`, 16/16-vs-oracle, +22% gate/+80% decode) via `BuildMoeMarlinResident`. So B2 = mirror that for `LagunaMoeWeights.experts_*_fp4` (a `BuildLagunaMoeMarlinResident` reusing the shared repack + route `LagunaFfnBlock`'s fp4 branch to the Marlin grouped GEMM, GEMV kept as the `=0` escape hatch) — pure reuse, no new kernel, matches vLLM's exact W4A16 numerics. **B2 IMPLEMENTED (2026-08-01, `3c49ef37`) — COMPILES CLEAN on GB10 sm_121a, runtime bug pending.** `LagunaMoeResidentMarlin` + `BuildLagunaMoeMarlinResident` (laguna.cpp, `#ifdef VT_MARLIN_NVFP4`) reconstruct the MoE Marlin path over the SHARED `dense_nvfp4::Dev`/`DBuf`/`ResidentNvfp4` + shared `vt::cuda` Marlin repack/align ops + `vt::MoeGroupedGemmNvfp4Marlin`; SACRED 27B/35B path BYTE-UNTOUCHED; gated `VT_LAGUNA_MARLIN_MOE=1` **default-OFF** (zero regression to the default GEMV path). Compiles clean on the full CUDA build. RUN: loads OK (48 layers, 256 experts) but the FIRST FORWARD device-faults silently on the Marlin path — a layout/param bug (suspects: `MoeCombine` bf16-in/f32-out dtype, the down-GEMM reusing the gate/up align, or the fp4-original free omitted → mem ~doubles). NEXT: `compute-sanitizer` localize → fix → near-tie vs the vLLM-Marlin golden + kernel-duration ncu → flip default-ON. Default path unaffected. **UPDATE (`22d6e146`): added the qwen3_5-style fp4-original free after repack** (device transients + host bytes; peak was ~3× the expert tower → past the 119 GiB pool → null-alloc → silent fault the likely cause); compiles clean. The runtime gate stayed INCONCLUSIVE this session (contended/orphaned processes on the shared box, no captured ids) — rerun on a clean uncontended session, compute-sanitizer if it still faults. **★★ B2 VALIDATED on GB10 (2026-08-01, with the mem-free fix): RUN_EXIT=0, coherent, first 13 generated tokens MATCH the vLLM-Marlin golden EXACTLY** (`22345 83 290 350 674 330 5541 966 340 9626 377 15360 81` — the best Laguna-NVFP4 correctness yet, W4A16 matching vLLM's config). **Steady-state decode 0.10 s/tok = ~10 tok/s** (steps 10-17 all 0.10; the TPOT-0.56 average is warmup-polluted — the DevicePool warms over ~9 decode steps then reuses). vs the GEMV path's 6.7 tok/s = **~1.5× faster; the gap to vLLM 18.8 closes from ~3× to ~1.9×.** Memory flat (7.9 GiB host RSS — the fp4-original free worked; it also fixed the first-forward fault). Still `VT_LAGUNA_MARLIN_MOE=1` default-OFF. TO DONE: move the lazy Marlin-resident build (216s first-forward, 48L×256E repack) to model-LOAD time → clean warm A/B + ncu → flip default-ON → matrix/roadmap. Remaining ~1.9×: vLLM graphs its decode (ours still eager) — decode CUDA-graph is the next lever. **REPRODUCED 3× (reproduction gate MET): GB10 runs deterministic — first 18-20 tokens byte-identical, steady-state 0.10 s/tok confirmed each — so the ~10 tok/s + golden-match is gated, not a single sample.** **#234 item (1) — load-time resident-build LANDED (`LagunaBuildMarlinResidents`, called from the example after load; mirrors vLLM process_weights_after_loading): builds all 48L×256E Marlin residents at LOAD so the repack is not a first-token TTFT spike. Fixed an anon-namespace linkage bug (public fn was defined with internal linkage → moved outside the anon namespace); BUILD CLEAN + links on GB10 sm_121a, default-OFF. Runtime prewarm-fires-at-load timing UNVERIFIED this session (repeated ssh-drops ate the run capture); the forward's lazy build is the validated fallback so it cannot regress. Owed: one clean run to confirm the build moved to load + then flip default-ON.** **★★ DONE (2026-08-01): Marlin is now the UNCONDITIONAL DEFAULT (`LagunaMarlinMoeEnabled` default-ON; `=0` is a code-level A/B opt-out no user needs) — "it just works" with NO env. Confirmed in a no-env GB10 run captured via tmux: `MARLIN residents built at load in 238.4s`, prefill 14.78s (build moved OUT of first-forward), golden-matching ids, steady-state 0.10 s/tok = ~10 tok/s (4th reproduction), RSS ~5-8 GiB. So a default Laguna-NVFP4 load on GB10 gets vLLM's own W4A16 Marlin decode (~10 tok/s, ~1.9× from vLLM 18.8) with zero flags. The 238s load-time repack is a one-time cost (mirrors vLLM process_weights_after_loading); optimizing its 48×256 per-expert sync count is a follow-up. Residual to 18.8 = decode CUDA-graph (deferred; user refocusing on DeepSeek next).** Post-lever-1 nsys: the remaining ~4× is HOST-SYNC-bound — 22,115 `cudaStreamSynchronize` (78.6% of API time, ~2,760/token, the per-GEMM `DrainQueue`), GPU kernels fast. Remaining levers: grouped W4A4 MoE (design input: `vt::MoeGroupedGemmNvfp4` is W4A16, so true-W4A4 grouped needs a new fp4×fp4 op or the `use_a16` mode + expert-stacking — needs a spike), device-resident decode (RECOMMENDED — the current forward is host-style so every GEMM drains; keep activations on-device, drain once/step; reuse qwen3_5's `Dev`/`Nvfp4Dev`/`ResidentNvfp4`/device-SwiGLU machinery; kills the 22k syncs; converges with the pending GGUF #228 and lifts both quant paths), decode CUDA-graph. Binding number needs a clean 2-3× re-run. See `docs/BENCHMARKS.md` + the spec N5 plan. See `docs/BENCHMARKS.md` `CLAIM-LAGUNA-VLLM-NVFP4`. Prior W7 nsys attribution: host-orchestration-bound, levers ranked (spec `laguna-s21-w7-speed-2026-07-31.md`, ledger `CLAIM-LAGUNA-W7-SPEED`). Prior RUNNABLE + FAST DECODE (W6, 2026-07-31): a per-layer K/V cache + single-token incremental decode replaces W5's O(n²) STATELESS full-recompute — TOKEN-IDENTICAL (byte-equal ids, md5 match, == the W5 golden) and 5.05× faster per token: decode 3.33 → 0.66 s/tok on the real 3-shard UD-Q4_K_XL GGUF (GB10, `--gpu`, keep-quant), same "The capital of France is" → " Paris.\n\nThe user is seeking a detailed explanation of the concept of \"cultural capital\"…". `LagunaKvCache` (mirrors `DeepseekV4KvCache`, MLA-latent → GQA multi-head K/V) caches post-QK-RMSNorm/post-RoPE K + raw V at f32 (bit-exact by construction: RoPE/QK-norm are position-only and attention is causal). MIXED attention handled per-layer: 12 GLOBAL layers grow the cache unbounded (full causal); 36 SLIDING-WINDOW-512 layers EVICT the oldest rows beyond the 512 window (gemma2/3 `is_sliding`), capping their K/V. `LagunaForwardGgufCached` + shared `LagunaAttention`/`LagunaFfnBlock` helpers used by BOTH forwards (identical float ops — the recompute path's ids are unchanged after the refactor); `examples/laguna_gen --stateless` forces the W5 recompute for the A/B gate. No cache bug: bit-exact on the first run. Next speed: grouped-expert GEMM + device-resident decode (both in-tree from ds4). See `.agents/specs/laguna-s21-w6-2026-07-31.md`. Prior RUNNABLE (W5, 2026-07-31): our engine greedy-generates COHERENT text on the REAL 3-shard UD-Q4_K_XL GGUF (GB10, keep-quant). `laguna-gen` "The capital of France is" → " Paris.\n\nThe user is seeking a detailed explanation of the concept of \"cultural capital\" as developed by French soci…" — the FIRST token is "Paris.", matching the llama.cpp-Poolside reference on the identical bytes. Multi-shard GGUF reader (LagunaGgufCtx routes each of 814 tensors to its shard; shard-1 = header only) + keep-quant tower (attn/dense/shared/experts/lm_head stay Q8_0/Q4_K/Q5_K COMPRESSED, consumed via `vt::MatmulBT`; norms/router/bias/embed → f32) + `LagunaForwardGguf` (the f32 composition with the ~9 GEMM sites swapped to keep-quant Gemm/GemmRowSlice, ds4 precedent) + `examples/laguna_gen`. Real GGUF metadata verified: dual-RoPE freq_base 500000/10000, dims 64/128, YaRN factor 32, sigmoid ungrouped-noaux router (scale 2.5), per-layer Q-head [48 global/72 sliding], per-head softplus out-gate, QK-RMSNorm. Load 20.6s, peak 71 GiB (fits 119 pool). Prior W4 IN PROGRESS (2026-07-31): 73.4 GiB UD-Q4_K_XL GGUF FETCHED + read authoritatively (814 tensors); 3 CPU-verified fidelity corrections grounded in the real GGUF + llama.cpp — per-head QK-RMSNorm (`attn_q/k_norm`, the scope MISSED it), GGUF-authoritative dual-RoPE mscale (llama.cpp `yarn_attn_factor·(1+0.1·ln(factor))`, factor 32 not HF 128), separate `ffn_gate/up_exps`. Keep-quant tower materialization + `ForwardGguf` + the real-model greedy run vs llama.cpp-laguna same-quant oracle = W5 close. Prior: W3 REAL host-reference forward + 3 new ops (`laguna_ops.cpp`, CPU `-Werror` clean, `test_laguna_scaffold` unit-gated)** | Poolside Laguna: 48 layers (12 global + 36 sliding-window-512), 256 routed top-10 + 1 shared expert, per-head **softplus attention output gate**, sigmoid `noaux_tc` router, dual per-layer RoPE (YaRN full-attn / plain sliding), GQA 8 KV / 128 head-dim, 1M ctx. **W3 (2026-07-31):** the 3 genuinely-NEW small host ops landed in `laguna_ops.cpp` — per-head softplus attn out-gate (`LagunaSoftplusHeadGate`), ungrouped sigmoid-noaux router (`LagunaUngroupedRouterTopK`, ds3 noaux_tc MINUS the group step + tie-break razor), dual per-layer RoPE cos/sin builders (`BuildLaguna{FullYarn,Sliding}CosSin`, reusing the pinned YaRN inv_freq over the partial-64 dims); `LagunaModel::Forward` is now a REAL runnable host-reference composition (variable-Q-head GQA + dual RoPE + sliding-window mask + softplus gate + dense L0 / ungrouped-MoE L1..47 + untied lm_head) replacing the `VT_CHECK(false)` stub; `test_laguna_scaffold` **8/8·166** (softplus math, router selection+tie-break RED-first, dual-RoPE bit-match, variable-Q-head shapes, forward composition on synthetic weights), `test_model_registry` 24/24. **W2 (2026-07-30):** registered, `ParseLagunaParams`, GGUF `blk.N.*` name-map + UD-Q4_K_XL quant-mix (Q4_K/Q5_K/Q6_K/Q8_0 ALL already decoded → ZERO new kernel). **W1 oracle DECISION:** vLLM NATIVE `laguna.py` (in pin → config constructs); dual-oracle = vLLM-NVFP4/-FP8 (fits GB10 119 GiB; BF16 235 GiB does NOT) + llama.cpp-Q4_K token-exact. ~85–90% reuse (ds4-MoE + Gemma-sliding + OLMo-3-dual-rope + Q4_K keep-quant, ALREADY landed). DEFERRED (W4): GGUF keep-quant tower materialization + device/paged production forward (loaders still LOUDLY throw) + strict dual-oracle greedy gate on a fetched checkpoint + `poolside_v1` parser. See `.agents/specs/laguna-s21-w3-2026-07-31.md` (+ W1/W2 `laguna-s21-w1w2-2026-07-30.md`, W0 `laguna-s21-scope-2026-07-30.md`). **Decode attention-glue fusion LANDED (2026-08-02, `CLAIM-LAGUNA-GLUE-FUSED`, default-ON `VT_LAGUNA_GLUE_FUSED`, `=0` A/B):** BYTE-EXACT L1 (softplus out-gate → `DecodeAttnCombineKernel` store) + L4 (residual-Add+RMSNorm pairs → the shared `vt::FusedChain(kFusedAddRmsNormStd)` seam) on the resident decode-graph — same-binary A/B ids byte-identical (159/159 @160), paging-immune nsys steady decode **−4.2% GPU-busy (28.90→27.69 ms/step), −120 graph nodes/step (−10%)**, wall drop_caches-tied (no regression). C shared-into-MoeCombine SKIPPED (Laguna's bf16 `MoeCombine` → not byte-exact); L2 qk-norm+RoPE preamble DEFERRED (needs a device-position kernel variant). See BENCHMARKS.md `CLAIM-LAGUNA-GLUE-FUSED`. **On-device greedy sample LANDED (2026-08-02, `CLAIM-LAGUNA-ONDEV-SAMPLE`, default-ON `VT_LAGUNA_ONDEV_SAMPLE`, `=0` A/B):** the resident decode graph used to Synchronize, return the whole `[100352]` logits, and argmax on the HOST between replays (+ host embed-gather of the next token) — the off-framework "born-on-host" seam the decode-framework-routing audit flagged. Now BOTH run ON-DEVICE inside the captured graph: `vt::GreedyArgmax` (lowest-index tie = the exact host winner) → 1-elem device token buffer, + a new capture-safe `embed_gather` kernel gathers the next input embedding from it (the stock `vt::Embedding` is NOT capture-safe: per-call event-sync + D2H ring). BYTE-EXACT (160-id stream identical `=0`/`=1` on `~/laguna-xs-nvfp4`) + faster: paired drop_caches decode wall **+0.28% median** (8/8 reps ≥0; removes ~150 us/step host argmax) at GPU-busy parity (nsys 2-length 27.44→27.42 ms/step). Aligns Laguna decode with vLLM on-device sampling. **Lever 2 (lm_head GEMV DRAM eff) MEASURED, NOT landed:** `[M=1,100352,2048]` bf16 = **170 GB/s (2.41 ms)** = ~91% of the cuBLAS M=1×large-N reference (~187 GB/s / 2.2 ms) — at the M=1 practical floor (the 273 GB/s ceiling is streaming-only, unreachable for a once-read GEMV); ≤0.7%-of-step headroom needs a reduction reorder (near-tie re-gate) ⇒ not chased, per prior "lm_head optimal". See BENCHMARKS.md `CLAIM-LAGUNA-ONDEV-SAMPLE`. **MoE add_rms_norm fold LANDED (2026-08-02, `CLAIM-LAGUNA-MOE-ADDNORM`, default-ON `VT_LAGUNA_MOE_ADDNORM_FUSED`, `=0` A/B):** the glue-fused MoE tail ran its residual update as TWO graph nodes — `vt::Add(hidden,routed)` [`AddKernel`] + `FusedChain(kFusedAddRmsNormStd)` [shared-add+RMSNorm, `RmsNormRowKernel`] — now ONE `fused_add2_rmsnorm` device node/MoE-layer (`hidden=(hidden+routed)+shared; hn=rms_norm(hidden)*w`). BYTE-EXACT (IEEE add commutes + the identical 256-thread shared-tree norm reduction; 160-id stream byte-identical `=0`/`=1` on `~/laguna-xs-nvfp4`) + faster: **−39 `AddKernel` graph nodes/step** (2.63ms→0 over 69 steps), paging-immune nsys 2-length **~−46 us/tok GPU (27339→27293)**, nsys wall **+0.4% (34.00→34.14 tok/s @70-tok)**. Small (byte-exact node-count trim on the graph-captured, GPU-bound decode; the dominant ~72% cost is the bf16 projection GEMVs — see the Lever-B negative in BENCHMARKS.md). See BENCHMARKS.md `CLAIM-LAGUNA-MOE-ADDNORM`. **Shared expert kept fp4 LANDED (2026-08-03, `CLAIM-LAGUNA-SHARED-FP4`, default-ON `VT_LAGUNA_SHARED_FP4`, `=0` A/B):** the XS-NVFP4 shared expert was DEQUANTIZED to bf16 at load (`LnLoadSharedExpertBf16`) → the M=1 decode GEMV read 4× the DRAM bytes of vLLM (which keeps it fp4). Now kept fp4-resident and routed through the SAME Marlin W4A16 single-expert (num_experts=1) grouped GEMM the routed experts win on (`dense_nvfp4::GateUpFusedMarlinD`+`MatmulNvfp4MarlinD`); the decode GEMV drops to router-ONLY (`moe.router`), shared gate/up/down go fp4. ADDITIVE new `laguna_shared_fp4.cpp` re-reads the on-disk fp4 from the gen driver before shard release (does NOT touch SACRED `laguna_weights.cpp`); bf16 shared KEPT for the T>1 prefill. NEAR-TIE (fp4≠bf16): coherent, first-20 ids == documented golden, byte-identical to bf16 for ~85 tokens then diverges; **DISTRIBUTIONAL GATE PASS 40/40** (ours' first-40 ids ∈ vLLM's 8-run greedy candidate set; vLLM XS-greedy is bf16-non-det, 8 unique of 8). FASTER: paging-immune nsys 2-length **GPU 27.24→26.53 ms/step (−2.6%)**, wall drop_caches **35.8→36.3 tok/s (+1.4%, fp4 wins all 3 reps)**; shared-expert kernel bucket ~1.68→~0.90 ms/step (halved); vs vLLM ~43 tok/s 83.3%→84.4%; RSS 22.2→22.1 GiB (freed the decode-only fused router-shared projection). Modest by design — XS's shared expert is small (`shared_expert_intermediate_size==moe_intermediate_size==512`). Default-ON per parity (matches vLLM's fp4 shared). See BENCHMARKS.md `CLAIM-LAGUNA-SHARED-FP4`. **qk-norm+RoPE preamble fusion LANDED (2026-08-03, `CLAIM-LAGUNA-PREAMBLE-FUSED`, default-ON `VT_LAGUNA_PREAMBLE_FUSED`, `=0` A/B):** closes the `CLAIM-LAGUNA-GLUE-FUSED` L2 deferral — the decode graph ran the per-layer attention preamble as FOUR under-occupied M=1 nodes (`rms_norm_seq(q)`+`rms_norm_seq(k)`+`rope_from_cache_g(q)`+`rope_from_cache_g(k)`); now ONE capture-safe `fused_qk_norm_rope_g` node/layer (`FusedQkNormRopeGKernel`, one block/head, reads the decode position from DEVICE `*pos_buf`, handles the per-layer dual-RoPE 64/128 + `Hq` 48/64). BYTE-EXACT BY CONSTRUCTION: it replicates the composed path's f32 MEMORY round-trip (Phase A 256-thread Σx² == `RmsNormSeqKernel`; Phase B the same `(x*inv)*w` store; `__syncthreads`; Phase C the `RopeFromCacheGKernel` rope read back) — an earlier register-only recompute was numerically-equivalent but diverged at a token-110 near-tie via compiler fma-contraction; the memory boundary forces bit-identity. 160-id stream byte-identical `=0`/`=1` on `~/laguna-xs-nvfp4` (determinism verified `=0`×3/`=1`×3 each run-to-run identical). FASTER: preamble norm+rope kernels **160→40 launches/tok, 326→154 us/tok (−0.17 ms/step)**; all decode-scaling kernels 26.53→26.37 ms/step; wall drop_caches **36.42→36.64 tok/s (+0.6%, fused wins all 3 paired reps)**; vs vLLM ~43 84.7%→85.2%. Modest (preamble ~1.2% of the 26.5 ms/step decode; the dominant cost stays the bf16 projection GEMVs at cuBLAS parity) — a byte-exact graph-node/launch trim (the glue-fusion residual mechanism). Default-ON per parity. See BENCHMARKS.md `CLAIM-LAGUNA-PREAMBLE-FUSED`. **W7 two-front pass LANDED (2026-08-03, `CLAIM-LAGUNA-W7-DECODE`):** FRONT 1 — the example driver logged `[gen] step N …(RSS)` EVERY decode step, and the RSS arg calls `CurResidentGiB()` (a `/proc/self/status` read) + an unbuffered stderr write in the GPU-idle gap between replays; guarded behind `VT_LAGUNA_STEP_LOG` (default OFF) + added a `decode_wall` line (TRUE end-to-end throughput incl. per-step gaps) next to the gap-free `decode_hp`. Since the fprintf sat OUTSIDE the `s0→s1` timer, `decode_hp` was ALREADY honest; with the log off `decode_wall == decode_hp` (within 0.001 tok/s, every LOG_OFF rep) and the recovered host tax is only ~0.1% (drop_caches noise floor). CONCLUSION: the ~86% gap to vLLM 43 is genuine device compute, NOT a harness artifact. FRONT 2 — `VT_LAGUNA_MOE_ONECAST` (default ON): a MoE layer cast the same `hn[1,H]` f32→bf16 THREE times (router GEMV + routed Marlin + shared Marlin); now cast ONCE into a persistent buffer and reuse (`CastHnBf16`/`GemmBf16Pre` + optional pre-cast param on both `…Into` helpers). BYTE-EXACT (deterministic truncation; `=1` vs `=0` byte-identical 300-tok ids); `CastBf16` **200→122 nodes/step (−78 = 2×39 MoE layers)**, GPU-busy parity within nsys noise, decode_hp +0.29%. Combined (onecast on + log off) **36.97 tok/s = 86.0% of vLLM-NVFP4 43** (from 36.64/85.2%). See BENCHMARKS.md `CLAIM-LAGUNA-W7-DECODE`. **Tail-fold follow-up LANDED (2026-08-03, `CLAIM-LAGUNA-TAIL-FUSED`, default-ON `VT_LAGUNA_TAIL_FUSED`, `=0` A/B):** a fresh node-ranking of the baseline decode graph found the routed-MoE `CastF32` as the one clean byte-exact fold left; it folds into the trailing `fused_add2_rmsnorm` via a new bf16-x1 sibling kernel (`AddAdd2RmsNormStdBf16Kernel` — `MoeCombine` writes bf16 straight to a persistent buffer, widened in-kernel by `__bfloat162float`). BYTE-EXACT (`=1` vs `=0` byte-identical 160-tok ids), `CastF32` **78→39 nodes/step**, total graph nodes **919→880**, GPU-busy parity; decode_hp a WASH (median +0.14% / mean −0.04%, at the drop_caches noise floor). Lands on the deterministic node-count basis (like onecast/preamble/addnorm), NOT a wall win; combined headline UNCHANGED **36.97 tok/s = 86.0%**. The ranking confirms the byte-exact decode-tail fold tier is now essentially EXHAUSTED (residual tail = already-folded norms + attention compute + cuBLAS-adjacent router/topk + ported-Marlin `MoeAlign`/`SiluAndMul`/`MoeCombine`); the gap to vLLM 43 is genuine device compute at the practical ceiling. See BENCHMARKS.md `CLAIM-LAGUNA-TAIL-FUSED`. **KERNEL-EFFICIENCY tier (2026-08-03, `VT_LAGUNA_FAST_NORM` default ON + f32 ext of `VT_RMSNORM_DECODE_FAST`):** the fold tier was exhausted but the residual-stream norm KERNELS were still under-occupied — `ncu` on the shipped `<<<1,256>>>` `AddAdd2RmsNormStdBf16`/`RmsNormRow` decode norms: `launch__waves_per_multiprocessor≈0.00`, `sm__throughput≈0.06%` (one 256-thread block on 1 SM of ~100+, latency-bound). Porting the PROVEN bit-identical `RmsNormRowFastKernel` structure (1024-thread float4 memory passes; 256-strided-partial + tree reduction reproduced byte-for-byte) to the f32 kernels cut each **286→~155 µs/tok (1.85×)**, **byte-exact** (160-tok ids identical `=1`vs`=0`; the f32 fix vs the bf16 sibling: store `v` not `v²` and square in the reduction so nvcc emits shipped's `acc += v*v` **fma** — a pre-squared f32 `v²` is not exact and flipped an XS near-tie at tok 108). **−0.81% decode-step GPU time** (paging-immune 70-vs-20 2-length diff, 26192→25980 µs/step); wall-clock ON/OFF overlap (noise floor). Residual: the byte-exact 256-strided reduction can't reach vLLM's per-kernel norm floor (~2.4× vLLM) without breaking byte-exactness → that remainder is byte-exactness-BLOCKED. See BENCHMARKS.md `CLAIM-LAGUNA-FAST-NORM`. **Router top-k warp-shuffle LANDED (2026-08-03, `CLAIM-LAGUNA-TOPK-SHFL`, default-ON `VT_LAGUNA_TOPK_SHFL`, `=0` A/B): BYTE-EXACT** — an nsys 2-length rank of the remaining small kernels (past the at-parity `gemvx` projection GEMVs ~69% of step + Marlin MoE) put the router `SigmoidTopKKernel` top (415 µs/step); `ncu` showed it `<<<1,256>>>` at `waves≈0.000`/`sm≈0.2%` — pure latency (8 serially-dependent rounds × a ~10-sync `sh[256]` argmax tree). New `SigmoidTopKShflKernel` reduces each round by warp-shuffle argmax (2 syncs/round; argmax over the total order is associative ⇒ SAME winner) → **`SigmoidTopK` 414.6→248.8 µs/step (1.67×)**, decode-step GPU **−0.57%** (26.018→25.869 ms/step), 37.39→37.49 tok/s decode_hp (**87.2% of vLLM-NVFP4 43**); 160-id stream byte-identical `=1`vs`=0`. **NOT landed — norm warp-shuffle (`VT_LAGUNA_NORM_SHFL`):** a near-tie register-accumulate+shuffle reduce for the Laguna `AddAdd2RmsNormStd{,Bf16}Fast` norms PASSED the distributional gate (coherent, in-set 38/40 = baseline, one near-tie fork at pos 37) and was −19.3% per-kernel (`AddAdd2RmsNormStdBf16` 150.3→121.3 µs/step) BUT washed at whole-step (0.6% of step; +0.02% within noise) — a near-tie fork isn't justified by a below-noise gain, so it was dropped. The small-kernel norm tail is at its occupancy floor; the decode step is dominated by the at-parity projection GEMVs. See BENCHMARKS.md `CLAIM-LAGUNA-TOPK-SHFL`. **Shared-expert 2-stream overlap LANDED (2026-08-03, `CLAIM-LAGUNA-SHARED-AUX`, default-ON `VT_LAGUNA_SHARED_AUX`, `=0` A/B):** mirror of vLLM's `MULTI_STREAM_OVERLAPPED` — in `LagunaGraph::RunChain` the fp4-shared arm's shared expert is EARLY-forked onto a second CUDA stream from the post-attn hidden `hn` BEFORE the router GEMV (aux reads `hn` f32 + does its own byte-identical cast; scratch from `AuxPool`), overlapping router+`sigmoid_topk`+routed grouped GEMM, joined before the combine — the SAME machinery the 35B ships default-ON (ENG-MOE-SHARED-AUX, runs inside the captured graph). This is the EARLY fork the prior fused-`router_shared_gu` attempt (`89e0d074`, −0.35% wash) could not reach. Capture-safe (aux stream+2 events in the ctor; gstate-0 warm-run builds residents + warms `AuxPool`). **BYTE-EXACT** (`=1`vs`=0` byte-identical 63-tok ids). REAL concurrency: nsys `--cuda-graph-trace=node` 20↔70 sum-vs-union → OVERLAP **2.34 ms/step** (SUM/UNION 1.092) vs `=0`'s 0.0004 ms; net GPU-busy wall **26.213→25.467 ms/step (−2.9%, 38.15→39.27 tok/s)**, wall @200 37.08→37.93 (+2.3%). Net +#include "vllm/model_executor/models/qwen3_5_weights.h" // Nvfp4Weight (fp4 arm) #include "vt/device.h" #include "vt/tensor.h" @@ -1100,6 +1101,16 @@ struct MiniMaxH3DitBlockWeights { vt::Tensor fc2; // [H, ffn] vt::Tensor adaln_w; // [expand*modality*H, time_embed_dim] (blocks only) vt::Tensor adaln_b; // [expand*modality*H] + + // W-FP4a: the fp4 SPEED arm. When the DiT is loaded fp4-RESIDENT (the NVFP4 + // checkpoint kept packed instead of dequantized), these carry the U8-packed + // E2M1 weight + its E4M3 group-16 scale + f32 global for each quantized + // projection, and the matching bf16 `vt::Tensor` above is left Empty(). The + // device forward routes a non-Empty() fp4 weight through + // dense_nvfp4::MatmulNvfp4W4A16D (Marlin W4A16 on sm_121, the SAME kernel the + // Laguna routed-expert + dense-Qwen3 NVFP4 arms use) instead of vt::MatmulBT; + // adaln_b keeps its bias `vt::Tensor` because the fp4 GEMM carries no bias. + Nvfp4Weight qkv_fp4, out_fp4, fc1_fp4, fc2_fp4, adaln_fp4; }; struct MiniMaxH3DitWeights { @@ -1116,6 +1127,11 @@ struct MiniMaxH3DitWeights { vt::Tensor final_adaln_w, final_adaln_b; vt::Tensor video_out_w, video_out_b; vt::Tensor audio_out_w, audio_out_b; + + // W-FP4a fp4 SPEED arm (see MiniMaxH3DitBlockWeights): the two quantized + // projections outside the block loop. condition_proj carries a bias + // (condition_proj_b, kept above); final_adaln carries final_adaln_b. + Nvfp4Weight condition_fp4, final_adaln_fp4; }; // A GGUF-loaded DiT: owned dequantized buffers plus the views the forward takes. @@ -1264,6 +1280,23 @@ MiniMaxH3DitDeviceWeights StreamMiniMaxH3Nvfp4ToDeviceBf16(vt::Queue& queue, const SafetensorsFile& file, MiniMaxH3DitParams* out_params = nullptr); +// W-FP4a — the fp4 SPEED twin of the streamer above. Instead of dequantizing each +// U8 projection to bf16 and running vt::MatmulBT, this keeps the compressed-tensors +// FP4 triple RESIDENT (an Nvfp4Weight per quantized projection) so the device +// forward routes those GEMMs through dense_nvfp4::MatmulNvfp4W4A16D — the Marlin +// W4A16 grouped GEMM (sm_121a native FP4 tensor cores) that the Laguna routed-expert +// and dense-Qwen3 NVFP4 arms already use. The fp32 ISLANDS (both patch projections, +// the time embedder, both output heads, rope.inv_freq) and the norms/biases stay +// exactly as the bf16 streamer stages them. The packed weight bytes are held host- +// resident on each Nvfp4Weight and uploaded (once, lazily) by the dispatcher's +// resident-repack on first forward, then freed — so peak device memory is ~1/4 of +// the bf16-dequant arm (the DiT is ~16 GB packed vs ~66 GB bf16). Correctness of +// the Marlin kernel itself is gated on CUDA by test_ops_nvfp4_matmul / +// test_linear_method; this arm is a loader+dispatch wiring, adding NO quant code. +MiniMaxH3DitDeviceWeights StreamMiniMaxH3Nvfp4ToDeviceFp4(vt::Queue& queue, + const SafetensorsFile& file, + MiniMaxH3DitParams* out_params = nullptr); + MiniMaxH3DitDeviceWeights StageMiniMaxH3DitWeights(vt::Queue& queue, const MiniMaxH3DitParams& params, const MiniMaxH3DitWeights& host, diff --git a/src/vllm/model_executor/models/minimax_h3_device.cpp b/src/vllm/model_executor/models/minimax_h3_device.cpp index 9cc70c4fd..a01d011a1 100644 --- a/src/vllm/model_executor/models/minimax_h3_device.cpp +++ b/src/vllm/model_executor/models/minimax_h3_device.cpp @@ -40,6 +40,7 @@ #include #include "vllm/model_executor/models/dense_device_glue.h" +#include "vllm/model_executor/models/dense_nvfp4_gemm.h" // W-FP4a: MatmulNvfp4W4A16D #include "vllm/model_executor/model_loader/gguf_dequant.h" #include "vllm/model_executor/model_loader/gguf_reader.h" #include "vllm/model_executor/model_loader/nvfp4_dequant.h" @@ -95,11 +96,31 @@ const minimax_h3::MiniMaxH3DeviceKernels* Glue(const Dev& d) { // vt::MatmulBT + optional rank-1 bias, the device twin of the reference `Linear`. // Weight is [out_features, in_features] — every {Column,Row,QKV,MergedColumn} // ParallelLinear at TP=1. +// +// W-FP4a: when `fp4` is non-null and non-Empty(), the projection is fp4-RESIDENT. +// The GEMM routes through dense_nvfp4::MatmulNvfp4W4A16D instead of vt::MatmulBT — +// the SAME forced-Marlin W4A16 dispatch the Laguna/dense-Qwen3 NVFP4 arms use +// (vLLM __init__.py:879-881: a weight-only NVFP4 scheme forces the Marlin kernel). +// On sm_121a with a bf16 activation that is the native FP4-tensor-core path; in the +// f32 parity stream (or on a backend without the Marlin op) the SAME dispatcher +// falls back to a redundant-dequant GEMM, so the arm is correct either way. The +// dequant lives entirely inside the shared dispatcher — this adds NO quant code. void LinearDev(Dev d, const Tensor& in, int64_t rows, int64_t in_features, const Tensor& weight, - const Tensor* bias, Tensor& out) { + const Tensor* bias, Tensor& out, const Nvfp4Weight* fp4 = nullptr) { + Tensor a = dense_attn::Reshape(in, {rows, in_features}); + if (fp4 != nullptr && !fp4->Empty()) { + VT_CHECK(fp4->k == in_features, + "minimax_h3 fp4 linear: packed weight K does not match input width"); + Tensor o = dense_attn::Reshape(out, {rows, fp4->n}); + DBuf r = dense_nvfp4::MatmulNvfp4W4A16D(d, a, *fp4, o.dtype); + d.b.Copy(d.q, o.data, r.t().data, r.bytes()); + if (bias != nullptr && bias->data != nullptr) { + vt::Add(d.q, o, o, *bias); // rank-1 row-broadcast == a nn.Linear bias term + } + return; + } VT_CHECK(weight.rank == 2 && weight.shape[1] == in_features, "minimax_h3 device linear: weight shape does not match input width"); - Tensor a = dense_attn::Reshape(in, {rows, in_features}); Tensor o = dense_attn::Reshape(out, {rows, weight.shape[0]}); vt::MatmulBT(d.q, o, a, weight); if (bias != nullptr && bias->data != nullptr) { @@ -143,6 +164,9 @@ struct AttnWeightsDev { const Tensor* q_norm; const Tensor* k_norm; const Tensor* out_proj; + // W-FP4a: fp4-resident twins of qkv/out_proj (null on the bf16/f32 arms). + const Nvfp4Weight* qkv_fp4 = nullptr; + const Nvfp4Weight* out_fp4 = nullptr; }; // MiniMaxH3Attention.forward (minimax_h3_transformer.py:421-467). @@ -155,7 +179,7 @@ void AttentionDev(Dev d, const MiniMaxH3DitParams& params, const AttnWeightsDev& const int64_t inner = heads * head_dim; DBuf qkv(d, dt.S(), {rows, 3 * inner}); - LinearDev(d, in, rows, params.hidden_size, *w.qkv, nullptr, qkv.t()); + LinearDev(d, in, rows, params.hidden_size, *w.qkv, nullptr, qkv.t(), w.qkv_fp4); DBuf qb(d, dt.S(), {rows, inner}); DBuf kb(d, dt.S(), {rows, inner}); @@ -192,19 +216,22 @@ void AttentionDev(Dev d, const MiniMaxH3DitParams& params, const AttnWeightsDev& vt::DFlashBlockAttention(d.q, attn.t(), tq, tk, tv, args); Tensor flat = dense_attn::Reshape(attn.t(), {rows, inner}); - LinearDev(d, flat, rows, inner, *w.out_proj, nullptr, out); + LinearDev(d, flat, rows, inner, *w.out_proj, nullptr, out, w.out_fp4); } // MiniMaxH3MLP.forward (minimax_h3_transformer.py:512-517): silu(gate) * up. // fc1 emits [gate; up] per row, which is exactly vt::SiluAndMul's input layout. void MlpDev(Dev d, const MiniMaxH3DitParams& params, const Tensor& fc1, const Tensor& fc2, - const Tensor& in, int64_t rows, const DeviceStreamDtype& dt, Tensor& out) { + const Tensor& in, int64_t rows, const DeviceStreamDtype& dt, Tensor& out, + const Nvfp4Weight* fc1_fp4 = nullptr, const Nvfp4Weight* fc2_fp4 = nullptr) { const int64_t ffn = params.ffn_hidden_size; DBuf hidden(d, dt.S(), {rows, 2 * ffn}); - LinearDev(d, in, rows, params.hidden_size, fc1, nullptr, hidden.t()); + // fc1 is already the merged [gate; up] (SwiGLU) — one W4A16 GEMM to [rows, 2*ffn] + // then SiluAndMul, so the fused gate_up pair (GateUpFusedMarlinD) does not apply. + LinearDev(d, in, rows, params.hidden_size, fc1, nullptr, hidden.t(), fc1_fp4); DBuf act(d, dt.S(), {rows, ffn}); vt::SiluAndMul(d.q, act.t(), hidden.t()); - LinearDev(d, act.t(), rows, ffn, fc2, nullptr, out); + LinearDev(d, act.t(), rows, ffn, fc2, nullptr, out, fc2_fp4); } // MiniMaxH3AdalnProj.forward (minimax_h3_transformer.py:555-561): @@ -212,8 +239,9 @@ void MlpDev(Dev d, const MiniMaxH3DitParams& params, const Tensor& fc1, const Te // the block loop by the caller: t_emb does not change across blocks, so the // reference's per-block silu is redundant work the device path simply does once. void AdalnProjectDev(Dev d, const Tensor& activated, int64_t m, int64_t time_embed_dim, - const Tensor& weight, const Tensor& bias, Tensor& out) { - LinearDev(d, activated, m, time_embed_dim, weight, &bias, out); + const Tensor& weight, const Tensor& bias, Tensor& out, + const Nvfp4Weight* fp4 = nullptr) { + LinearDev(d, activated, m, time_embed_dim, weight, &bias, out, fp4); } } // namespace @@ -548,7 +576,7 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, CastTo(d, text_rows.t(), text_rows_f32.t()); DBuf text_embed(d, dt.S(), {inputs.num_text_pos, hidden}); LinearDev(d, text_rows.t(), inputs.num_text_pos, params.text_dim, weights.condition_proj_w, - &weights.condition_proj_b, text_embed.t()); + &weights.condition_proj_b, text_embed.t(), &weights.condition_fp4); // Token refiner: a plain pre-norm stack, no AdaLN and no RoPE (:564-623), on the // REPLICATED text rows, so it uses the refiner's own cu_seqlens. @@ -560,8 +588,9 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, args.eps = static_cast(params.norm_eps); for (const MiniMaxH3DitBlockWeights& block : weights.refiner) { vt::RmsNorm(d.q, normed.t(), text_embed.t(), block.norm1, args); - AttentionDev(d, params, AttnWeightsDev{&block.qkv_proj, &block.q_norm, &block.k_norm, - &block.out_proj}, + AttentionDev(d, params, + AttnWeightsDev{&block.qkv_proj, &block.q_norm, &block.k_norm, &block.out_proj, + &block.qkv_fp4, &block.out_fp4}, normed.t(), rows, nullptr, nullptr, inputs.refiner_cu_seqlens, static_cast(inputs.num_refiner_cu_seqlens - 1), dt, tmp.t()); // FOLD onto the catalog recipe. This was DECLINED one milestone ago because @@ -573,7 +602,8 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, // one launch instead of two. vt::FusedChain(d.q, normed.t(), tmp.t(), block.norm2, &text_embed.t(), vt::kFusedAddRmsNormStd, args.eps); - MlpDev(d, params, block.fc1, block.fc2, normed.t(), rows, dt, tmp.t()); + MlpDev(d, params, block.fc1, block.fc2, normed.t(), rows, dt, tmp.t(), &block.fc1_fp4, + &block.fc2_fp4); vt::Add(d.q, text_embed.t(), text_embed.t(), tmp.t()); } vt::RmsNormArgs final_args; @@ -671,7 +701,7 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, for (const MiniMaxH3DitBlockWeights& block : weights.blocks) { AdalnProjectDev(d, t_emb_s.t(), m, params.time_embed_dim, block.adaln_w, block.adaln_b, - projected.t()); + projected.t(), &block.adaln_fp4); const Tensor shift_msa = chunk_view(projected, adaln_rows, 6, 0); const Tensor scale_msa = chunk_view(projected, adaln_rows, 6, 1); const Tensor gate_msa = chunk_view(projected, adaln_rows, 6, 2); @@ -684,7 +714,8 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, d_combined.t().Ptr(), seq_len, hidden, 6 * hidden, dt.S()); AttentionDev(d, params, - AttnWeightsDev{&block.qkv_proj, &block.q_norm, &block.k_norm, &block.out_proj}, + AttnWeightsDev{&block.qkv_proj, &block.q_norm, &block.k_norm, &block.out_proj, + &block.qkv_fp4, &block.out_fp4}, normed.t(), seq_len, &d_rope_cache.t(), &d_rope_pos.t(), inputs.cu_seqlens, num_reqs, dt, tmp.t()); glue->modulate_gate(d.q, stream.t().data, gate_msa.data, tmp.t().data, @@ -694,7 +725,8 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, glue->modulate_scale_shift(d.q, normed.t().data, shift_mlp.data, scale_mlp.data, d_combined.t().Ptr(), seq_len, hidden, 6 * hidden, dt.S()); - MlpDev(d, params, block.fc1, block.fc2, normed.t(), seq_len, dt, tmp.t()); + MlpDev(d, params, block.fc1, block.fc2, normed.t(), seq_len, dt, tmp.t(), &block.fc1_fp4, + &block.fc2_fp4); glue->modulate_gate(d.q, stream.t().data, gate_mlp.data, tmp.t().data, d_combined.t().Ptr(), seq_len, hidden, 6 * hidden, dt.S()); } @@ -702,7 +734,7 @@ MiniMaxH3DitOutputs MiniMaxH3DitForwardDevice(vt::Queue& queue, // --- final layer (minimax_h3_transformer.py:724-743) --- DBuf final_projected(d, dt.S(), {m, 2 * hidden}); AdalnProjectDev(d, t_emb_s.t(), m, params.time_embed_dim, weights.final_adaln_w, - weights.final_adaln_b, final_projected.t()); + weights.final_adaln_b, final_projected.t(), &weights.final_adaln_fp4); const Tensor final_shift = chunk_view(final_projected, m, 2, 0); const Tensor final_scale = chunk_view(final_projected, m, 2, 1); vt::RmsNormArgs final_args; @@ -813,6 +845,74 @@ void BindStreamedDitViews(const std::map& views, w.audio_out_b = view("final_layer.audio_out.bias"); } +// W-FP4a binder: the fp4-resident twin of BindStreamedDitViews. Every non-quantized +// tensor (norms, biases, fp32 islands) is bound from `views` exactly as above; each +// quantized projection is MOVED out of `fp4` into its Nvfp4Weight slot, and its bf16 +// `vt::Tensor` slot is left Empty(). A projection absent from `fp4` was stored +// unquantized in the checkpoint and falls back to a `views` bind, so an +// island-only-quantized file still lands on the same contract. +void BindStreamedDitViewsFp4(const std::map& views, + std::map& fp4, + const MiniMaxH3DitParams& params, MiniMaxH3DitWeights* out) { + auto view = [&](const std::string& name) -> Tensor { + const auto it = views.find(name); + VT_CHECK(it != views.end(), + "minimax_h3 nvfp4-fp4: checkpoint is missing a required tensor"); + return it->second; + }; + // Route a projection: fp4-resident when present in `fp4`, else its bf16 view. + auto proj = [&](const std::string& name, Nvfp4Weight& wdst, Tensor& tdst) { + const auto it = fp4.find(name); + if (it != fp4.end()) { + wdst = std::move(it->second); + tdst = Tensor{}; + } else { + tdst = view(name); + } + }; + MiniMaxH3DitWeights& w = *out; + w.video_patch_proj_w = view("video_patch_proj.weight"); + w.video_patch_proj_b = view("video_patch_proj.bias"); + w.audio_patch_proj_w = view("audio_patch_proj.weight"); + w.audio_patch_proj_b = view("audio_patch_proj.bias"); + proj("condition_proj.weight", w.condition_fp4, w.condition_proj_w); + w.condition_proj_b = view("condition_proj.bias"); + w.time_proj_in_w = view("time_embedder.proj_in.weight"); + w.time_proj_in_b = view("time_embedder.proj_in.bias"); + w.time_proj_out_w = view("time_embedder.proj_out.weight"); + w.time_proj_out_b = view("time_embedder.proj_out.bias"); + auto block = [&](const std::string& prefix, bool adaln) { + MiniMaxH3DitBlockWeights b; + b.norm1 = view(prefix + ".norm1.weight"); + b.norm2 = view(prefix + ".norm2.weight"); + proj(prefix + ".attn.qkv_proj.weight", b.qkv_fp4, b.qkv_proj); + b.q_norm = view(prefix + ".attn.q_norm.weight"); + b.k_norm = view(prefix + ".attn.k_norm.weight"); + proj(prefix + ".attn.out_proj.weight", b.out_fp4, b.out_proj); + proj(prefix + ".mlp.fc1.weight", b.fc1_fp4, b.fc1); + proj(prefix + ".mlp.fc2.weight", b.fc2_fp4, b.fc2); + if (adaln) { + proj(prefix + ".adaln_proj.linear.weight", b.adaln_fp4, b.adaln_w); + b.adaln_b = view(prefix + ".adaln_proj.linear.bias"); + } + return b; + }; + for (int64_t i = 0; i < params.token_refiner_num_layers; ++i) { + w.refiner.push_back(block("token_refiner.blocks." + std::to_string(i), false)); + } + w.refiner_final_norm = view("token_refiner.final_norm.weight"); + for (int64_t i = 0; i < params.num_layers; ++i) { + w.blocks.push_back(block("blocks." + std::to_string(i), true)); + } + w.final_norm = view("final_layer.norm.weight"); + proj("final_layer.adaln_proj.linear.weight", w.final_adaln_fp4, w.final_adaln_w); + w.final_adaln_b = view("final_layer.adaln_proj.linear.bias"); + w.video_out_w = view("final_layer.video_out.weight"); + w.video_out_b = view("final_layer.video_out.bias"); + w.audio_out_w = view("final_layer.audio_out.weight"); + w.audio_out_b = view("final_layer.audio_out.bias"); +} + } // namespace MiniMaxH3DitDeviceWeights StreamMiniMaxH3DitToDeviceBf16(vt::Queue& queue, const GgufFile& file, @@ -1043,4 +1143,131 @@ MiniMaxH3DitDeviceWeights StreamMiniMaxH3Nvfp4ToDeviceBf16(vt::Queue& queue, return staged; } +// W-FP4a: the fp4-RESIDENT NVFP4 streamer. Structurally identical to +// StreamMiniMaxH3Nvfp4ToDeviceBf16, except a U8-packed projection is KEPT as an +// Nvfp4Weight (host packed + E4M3 scale + f32 global) instead of being dequantized +// to bf16 and uploaded — so the device forward routes it through the Marlin W4A16 +// GEMM. Islands stay f32, norms/biases bf16. Peak device memory is ~1/4 of the bf16 +// arm because the ~16 GB of packed FP4 never expands to ~66 GB of bf16. +MiniMaxH3DitDeviceWeights StreamMiniMaxH3Nvfp4ToDeviceFp4(vt::Queue& queue, + const SafetensorsFile& file, + MiniMaxH3DitParams* out_params) { + vt::Backend& backend = vt::GetBackend(queue.device.type); + const bool trace = std::getenv("VT_H3_PROGRESS") != nullptr; + + auto is_sidecar = [](const std::string& n) { + return (n.size() > 12 && n.compare(n.size() - 12, 12, "weight_scale") == 0) || + (n.size() > 14 && n.compare(n.size() - 14, 14, "weight_scale_2") == 0); + }; + auto is_fp32_island = [](const std::string& n) { + return n.rfind("video_patch_proj.", 0) == 0 || n.rfind("audio_patch_proj.", 0) == 0 || + n.rfind("time_embedder.", 0) == 0 || n.rfind("final_layer.video_out.", 0) == 0 || + n.rfind("final_layer.audio_out.", 0) == 0 || n == "rope.inv_freq"; + }; + + // Pass 1: logical shapes (U8 packed [out, in/2] is logically [out, in]). + std::vector manifest; + for (const std::string& name : file.Names()) { + if (is_sidecar(name)) continue; + const StTensor& t = file.Get(name); + MiniMaxH3TensorSpec spec; + spec.name = name; + spec.shape = t.shape; + if (t.dtype == "U8") { + VT_CHECK(t.shape.size() == 2, "minimax_h3 nvfp4-fp4: a packed weight must be rank 2"); + spec.shape = {t.shape[0], t.shape[1] * 2}; + } + manifest.push_back(std::move(spec)); + } + const MiniMaxH3DitParams params = ParseMiniMaxH3DitParamsFromGgufManifest(manifest); + if (out_params != nullptr) *out_params = params; + + MiniMaxH3DitDeviceWeights staged; + std::map views; + std::map fp4; + size_t done = 0; + for (const MiniMaxH3TensorSpec& spec : manifest) { + const StTensor& t = file.Get(spec.name); + + if (spec.name == "rope.inv_freq") { + staged.rope_inv_freq_host = MiniMaxH3ReadSafetensorF32(t); + staged.weights.rope_inv_freq = vt::Tensor::Contiguous( + staged.rope_inv_freq_host.data(), DType::kF32, vt::Device{}, + {static_cast(staged.rope_inv_freq_host.size())}); + continue; + } + + // A packed projection -> keep the FP4 triple RESIDENT (no dequant, no upload; + // the dispatcher uploads + repacks lazily on first forward). + if (t.dtype == "U8") { + const int64_t out_dim = spec.shape[0], in_dim = spec.shape[1]; + const StTensor& scale = file.Get(spec.name + "_scale"); + const StTensor& global = file.Get(spec.name + "_scale_2"); + VT_CHECK(scale.dtype == "F8_E4M3", "minimax_h3 nvfp4-fp4: weight_scale must be F8_E4M3"); + VT_CHECK(global.dtype == "F32", "minimax_h3 nvfp4-fp4: weight_scale_2 must be F32"); + VT_CHECK(scale.shape.size() == 2 && scale.shape[0] == out_dim && + scale.shape[1] * 16 == in_dim, + "minimax_h3 nvfp4-fp4: weight_scale must be [out, in/16] (group size 16)"); + VT_CHECK(global.nbytes >= sizeof(float), "minimax_h3 nvfp4-fp4: weight_scale_2 too small"); + Nvfp4Weight w; + w.n = out_dim; + w.k = in_dim; + std::memcpy(&w.scale2, global.data, sizeof(float)); + w.packed.dtype = DType::kI8; + w.packed.rank = 2; + w.packed.shape[0] = out_dim; + w.packed.shape[1] = in_dim / 2; + w.packed.bytes.resize(static_cast(out_dim) * (in_dim / 2)); + VT_CHECK(t.nbytes == w.packed.bytes.size(), "minimax_h3 nvfp4-fp4: packed byte-size mismatch"); + std::memcpy(w.packed.bytes.data(), t.data, t.nbytes); + w.scale.dtype = DType::kI8; + w.scale.rank = 2; + w.scale.shape[0] = out_dim; + w.scale.shape[1] = in_dim / 16; + w.scale.bytes.resize(static_cast(out_dim) * (in_dim / 16)); + VT_CHECK(scale.nbytes == w.scale.bytes.size(), "minimax_h3 nvfp4-fp4: scale byte-size mismatch"); + std::memcpy(w.scale.bytes.data(), scale.data, scale.nbytes); + fp4[spec.name] = std::move(w); + } else { + // Island (f32) or norm/bias (bf16) -> upload a plain tensor, exactly like the + // bf16 streamer's non-U8 branch. + const bool island = is_fp32_island(spec.name); + const DType want = island ? DType::kF32 : DType::kBF16; + std::vector f32 = MiniMaxH3ReadSafetensorF32(t); + const void* src = nullptr; + size_t bytes = 0; + std::vector bf16; + if (island) { + src = f32.data(); + bytes = f32.size() * sizeof(float); + } else { + bf16.resize(f32.size()); + for (size_t i = 0; i < f32.size(); ++i) { + uint32_t bits; + std::memcpy(&bits, &f32[i], sizeof(bits)); + const uint32_t rounded = bits + 0x7FFFu + ((bits >> 16) & 1u); + bf16[i] = static_cast(rounded >> 16); + } + src = bf16.data(); + bytes = bf16.size() * sizeof(uint16_t); + } + void* pdev = backend.Alloc(bytes); + std::shared_ptr owner(pdev, [&backend](void* q) { backend.Free(q); }); + backend.Copy(queue, pdev, src, bytes); + backend.Synchronize(queue); // host buffers die at end of iteration + views[spec.name] = dense_attn::MakeTensor(pdev, want, queue.device, spec.shape); + staged.storage.push_back(std::move(owner)); + } + + if (trace && (++done % 50 == 0 || done == manifest.size())) { + std::fprintf(stderr, "[h3] nvfp4-fp4-streamed %zu/%zu tensors (last: %s)\n", done, + manifest.size(), spec.name.c_str()); + std::fflush(stderr); + } + } + + BindStreamedDitViewsFp4(views, fp4, params, &staged.weights); + return staged; +} + } // namespace vllm diff --git a/tests/vllm/models/test_minimax_h3.cpp b/tests/vllm/models/test_minimax_h3.cpp index 3bafa6b58..7c297187f 100644 --- a/tests/vllm/models/test_minimax_h3.cpp +++ b/tests/vllm/models/test_minimax_h3.cpp @@ -10,6 +10,7 @@ // that feeds RoPE), the flow-matching scheduler, the latent<->token packing, and // the full DiT forward all reproduce upstream's numbers. See // .agents/specs/minimax-h3.md sections 0 and 4. +#include "vllm/model_executor/models/dense_nvfp4_gemm.h" // W-FP4a: W4A16 exec stats #include "vllm/model_executor/models/minimax_h3.h" #include @@ -3087,6 +3088,67 @@ TEST_CASE("minimax_h3: an NVFP4 checkpoint loads into a runnable DiT") { CHECK(static_cast(got.video_logits.size()) == num_img * video_width); for (float v : got.video_logits) REQUIRE(std::isfinite(v)); for (float v : got.audio_logits) REQUIRE(std::isfinite(v)); + + // ── W-FP4a: the fp4 SPEED path vs the bf16 arm on the SAME loaded checkpoint ── + // The bf16 arm dequantizes each NVFP4 projection to bf16 and runs vt::MatmulBT; + // the fp4 arm keeps the packed FP4 resident and routes those GEMMs through + // dense_nvfp4::MatmulNvfp4W4A16D (Marlin W4A16 on sm_121a). Both consume the SAME + // fp4 bytes, so the delta is the GEMM PATH only — not quantization. On the CPU + // backend the dispatcher has no Marlin op, so it falls back to a redundant-dequant + // GEMM (numerically the bf16 arm's own math), which makes this a WIRING gate here: + // it proves the loader sets the fp4 slots and the forward routes them. The real + // Marlin-vs-bf16 numeric delta is measured on the GB10 (test_ops_nvfp4_matmul / + // test_linear_method gate the Marlin kernel itself on CUDA at 2e-3/8e-3). + { + vt::Queue q = vt::GetBackend(vt::DeviceType::kCPU).CreateQueue(); + vllm::MiniMaxH3DitParams bf16_params, fp4_params; + const vllm::MiniMaxH3DitDeviceWeights bf16_staged = + vllm::StreamMiniMaxH3Nvfp4ToDeviceBf16(q, st, &bf16_params); + const vllm::MiniMaxH3DitDeviceWeights fp4_staged = + vllm::StreamMiniMaxH3Nvfp4ToDeviceFp4(q, st, &fp4_params); + + // The fp4 loader must have kept the quantized projections PACKED (an Nvfp4Weight + // per projection) and left their bf16 tensor slot Empty(), while the bf16 loader + // did the opposite. Getting this backwards is the silent failure this asserts. + CHECK(!fp4_staged.weights.blocks[0].qkv_fp4.Empty()); + CHECK(fp4_staged.weights.blocks[0].qkv_proj.data == nullptr); + CHECK(bf16_staged.weights.blocks[0].qkv_fp4.Empty()); + CHECK(bf16_staged.weights.blocks[0].qkv_proj.data != nullptr); + // The 11 quantized projections of this reduced model (refiner: qkv/out/fc1/fc2; + // block: +adaln; condition_proj; final_adaln) all keep FP4. + CHECK(!fp4_staged.weights.condition_fp4.Empty()); + CHECK(!fp4_staged.weights.final_adaln_fp4.Empty()); + CHECK(!fp4_staged.weights.blocks[0].adaln_fp4.Empty()); + CHECK(fp4_staged.weights.refiner[0].adaln_fp4.Empty()); // refiner has no adaln + + const MiniMaxH3DitOutputs bf16_out = + MiniMaxH3DitForwardDevice(q, bf16_params, bf16_staged.weights, in, vt::DType::kBF16); + vllm::dense_nvfp4::ResetW4A16Stats(); + const MiniMaxH3DitOutputs fp4_out = + MiniMaxH3DitForwardDevice(q, fp4_params, fp4_staged.weights, in, vt::DType::kBF16); + const vllm::dense_nvfp4::Nvfp4W4A16Stats stats = vllm::dense_nvfp4::GetW4A16Stats(); + + // POSITIVE signal: the W4A16 dispatcher actually RAN for every quantized + // projection (11 GEMMs). On CPU these are `fallback_gemms`; on CUDA the same + // count lands as `marlin_gemms`. A silently-unwired forward would show zero. + const uint64_t w4a16_calls = stats.marlin_gemms + stats.fallback_gemms; + INFO("W4A16 GEMMs executed by the fp4 forward = " << w4a16_calls); + CHECK(w4a16_calls == 11); + + REQUIRE(fp4_out.video_logits.size() == bf16_out.video_logits.size()); + REQUIRE(fp4_out.audio_logits.size() == bf16_out.audio_logits.size()); + for (float v : fp4_out.video_logits) REQUIRE(std::isfinite(v)); + const double video_delta = + MaxAbsDiff(fp4_out.video_logits, bf16_out.video_logits.data(), fp4_out.video_logits.size()); + const double audio_delta = + MaxAbsDiff(fp4_out.audio_logits, bf16_out.audio_logits.data(), fp4_out.audio_logits.size()); + INFO("fp4-vs-bf16 (CPU fallback) video max|diff| = " << video_delta + << ", audio max|diff| = " << audio_delta); + // CPU fallback == the bf16 arm's own dequant+matmul, so the two agree to matmul + // reduction-order slack; a real fp4/bf16 divergence only appears on the GB10. + CHECK(video_delta <= 2e-3); + CHECK(audio_delta <= 2e-3); + } std::remove(path.c_str()); }